src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35
  36 struct iris_bo;
  37 struct iris_context;
  38 struct blorp_batch;
  39 struct blorp_params;
  40
  41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  44
  45 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  46 #define IRIS_MAX_VIEWPORTS 16
  47
  48 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  49 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  50 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  51 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  52 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  53 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  54 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  55 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  56 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  57 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  58 #define IRIS_DIRTY_SBE                      (1ull << 10)
  59 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  60 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  61 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  62 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  63 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  64 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  65 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  66 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  67 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  68 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  69 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  70 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  71 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  72 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  73 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  74 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  75 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  76 #define IRIS_DIRTY_VS                       (1ull << 28)
  77 #define IRIS_DIRTY_TCS                      (1ull << 29)
  78 #define IRIS_DIRTY_TES                      (1ull << 30)
  79 #define IRIS_DIRTY_GS                       (1ull << 31)
  80 #define IRIS_DIRTY_FS                       (1ull << 32)
  81 #define IRIS_DIRTY_CS                       (1ull << 33)
  82 #define IRIS_DIRTY_URB                      (1ull << 34)
  83 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  84 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  85 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  86 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  87 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  88 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 40)
  89 #define IRIS_DIRTY_WM                       (1ull << 41)
  90 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 42)
  91 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 43)
  92 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 44)
  93 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 45)
  94 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 46)
  95 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 47)
  96 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 48)
  97 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 49)
  98 #define IRIS_DIRTY_STREAMOUT                (1ull << 50)
  99 #define IRIS_DIRTY_VF_SGVS                  (1ull << 51)
 100
 101 /**
 102  * Non-orthogonal state (NOS) dependency flags.
 103  *
 104  * Shader programs may depend on non-orthogonal state.  These flags are
 105  * used to indicate that a shader's key depends on the state provided by
 106  * a certain Gallium CSO.
 107  */
 108 enum iris_nos_dep {
 109    IRIS_NOS_FRAMEBUFFER,
 110    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 111    IRIS_NOS_RASTERIZER,
 112    IRIS_NOS_BLEND,
 113
 114    IRIS_NOS_COUNT,
 115 };
 116
 117 struct iris_depth_stencil_alpha_state;
 118
 119 enum iris_program_cache_id {
 120    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 121    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 122    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 123    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 124    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 125    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 126    IRIS_CACHE_BLORP,
 127 };
 128
 129 /** @{
 130  *
 131  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
 132  * additional flushing control.
 133  *
 134  * The bits here are not the actual hardware values.  The actual values
 135  * shift around a bit per-generation, so we just have flags for each
 136  * potential operation, and use genxml to encode the actual packet.
 137  */
 138 enum pipe_control_flags
 139 {
 140    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 141    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 142    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 143    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 144    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 145    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 146    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 147    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 148    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 149    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 150    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 151    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 152    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 153    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 154    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 155    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 156    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 157    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 158    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 159    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 160    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 161    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 162    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 163    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 164 };
 165
 166 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 167    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 168     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 169     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 170
 171 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 172    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 173     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 174     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 175     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 176     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 177
 178 /** @} */
 179
 180 struct iris_compiled_shader {
 181    /** Reference to the uploaded assembly. */
 182    struct iris_state_ref assembly;
 183
 184    /** Pointer to the assembly in the BO's map. */
 185    void *map;
 186
 187    /** The program data (owned by the program cache hash table) */
 188    struct brw_stage_prog_data *prog_data;
 189
 190    /**
 191     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 192     * (the VUE-based information for transform feedback outputs).
 193     */
 194    uint32_t *streamout;
 195
 196    /**
 197     * Shader packets and other data derived from prog_data.  These must be
 198     * completely determined from prog_data.
 199     */
 200    uint8_t derived_data[0];
 201 };
 202
 203 struct iris_const_buffer {
 204    /** The resource and offset for the actual constant data */
 205    struct iris_state_ref data;
 206
 207    /** The resource and offset for the SURFACE_STATE for pull access. */
 208    struct iris_state_ref surface_state;
 209 };
 210
 211 struct iris_shader_state {
 212    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 213 };
 214
 215 struct iris_vtable {
 216    void (*destroy_state)(struct iris_context *ice);
 217    void (*init_render_context)(struct iris_screen *screen,
 218                                struct iris_batch *batch,
 219                                struct iris_vtable *vtbl,
 220                                struct pipe_debug_callback *dbg);
 221    void (*upload_render_state)(struct iris_context *ice,
 222                                struct iris_batch *batch,
 223                                const struct pipe_draw_info *draw);
 224    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 225                                  struct iris_bo *bo, uint32_t offset,
 226                                  uint64_t imm);
 227
 228    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 229    void (*store_derived_program_state)(const struct gen_device_info *devinfo,
 230                                        enum iris_program_cache_id cache_id,
 231                                        struct iris_compiled_shader *shader);
 232    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 233                                     const struct brw_vue_map *vue_map);
 234    void (*populate_vs_key)(const struct iris_context *ice,
 235                            struct brw_vs_prog_key *key);
 236    void (*populate_tcs_key)(const struct iris_context *ice,
 237                             struct brw_tcs_prog_key *key);
 238    void (*populate_tes_key)(const struct iris_context *ice,
 239                             struct brw_tes_prog_key *key);
 240    void (*populate_gs_key)(const struct iris_context *ice,
 241                            struct brw_gs_prog_key *key);
 242    void (*populate_fs_key)(const struct iris_context *ice,
 243                            struct brw_wm_prog_key *key);
 244 };
 245
 246 struct iris_border_color_pool {
 247    struct iris_bo *bo;
 248    void *map;
 249    unsigned insert_point;
 250
 251    /** Map from border colors to offsets in the buffer. */
 252    struct hash_table *ht;
 253 };
 254
 255 struct iris_context {
 256    struct pipe_context ctx;
 257
 258    struct pipe_debug_callback dbg;
 259
 260    struct slab_child_pool transfer_pool;
 261
 262    struct iris_vtable vtbl;
 263
 264    struct {
 265       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 266       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 267       struct brw_vue_map *last_vue_map;
 268
 269       struct iris_shader_state state[MESA_SHADER_STAGES];
 270
 271       struct u_upload_mgr *uploader;
 272       struct hash_table *cache;
 273
 274       unsigned urb_size;
 275    } shaders;
 276
 277    struct blorp_context blorp;
 278
 279    /** The main batch for rendering */
 280    struct iris_batch render_batch;
 281
 282    struct {
 283       uint64_t dirty;
 284       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 285       unsigned num_viewports;
 286       unsigned sample_mask;
 287       struct iris_blend_state *cso_blend;
 288       struct iris_rasterizer_state *cso_rast;
 289       struct iris_depth_stencil_alpha_state *cso_zsa;
 290       struct iris_vertex_element_state *cso_vertex_elements;
 291       struct pipe_blend_color blend_color;
 292       struct pipe_poly_stipple poly_stipple;
 293       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 294       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 295       struct pipe_stencil_ref stencil_ref;
 296       struct pipe_framebuffer_state framebuffer;
 297
 298       struct iris_genx_state *genx;
 299
 300       struct iris_state_ref sampler_table[MESA_SHADER_STAGES];
 301       bool need_border_colors;
 302       struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 303       struct iris_sampler_view *textures[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 304       unsigned num_samplers[MESA_SHADER_STAGES];
 305       unsigned num_textures[MESA_SHADER_STAGES];
 306
 307       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 308       bool streamout_active;
 309       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 310       uint32_t *streamout;
 311
 312       struct iris_state_ref unbound_tex;
 313
 314       struct u_upload_mgr *surface_uploader;
 315       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 316       // "I'm streaming this out at draw time and never want it again!"
 317       struct u_upload_mgr *dynamic_uploader;
 318
 319       struct iris_border_color_pool border_color_pool;
 320
 321       /**
 322        * Resources containing streamed state which our render context
 323        * currently points to.  Used to re-add these to the validation
 324        * list when we start a new batch and haven't resubmitted commands.
 325        */
 326       struct {
 327          struct pipe_resource *cc_vp;
 328          struct pipe_resource *sf_cl_vp;
 329          struct pipe_resource *color_calc;
 330          struct pipe_resource *scissor;
 331          struct pipe_resource *blend;
 332       } last_res;
 333    } state;
 334 };
 335
 336 #define perf_debug(dbg, ...) do {                      \
 337    if (INTEL_DEBUG & DEBUG_PERF)                       \
 338       dbg_printf(__VA_ARGS__);                         \
 339    if (unlikely(dbg))                                  \
 340       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 341 } while(0)
 342
 343 double get_time(void);
 344
 345 struct pipe_context *
 346 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 347
 348 void iris_init_blit_functions(struct pipe_context *ctx);
 349 void iris_init_clear_functions(struct pipe_context *ctx);
 350 void iris_init_program_functions(struct pipe_context *ctx);
 351 void iris_init_resource_functions(struct pipe_context *ctx);
 352 void iris_init_query_functions(struct pipe_context *ctx);
 353 void iris_update_compiled_shaders(struct iris_context *ice);
 354
 355 /* iris_blit.c */
 356 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 357                                   struct pipe_resource *p_res,
 358                                   enum isl_aux_usage aux_usage,
 359                                   bool is_render_target);
 360
 361 /* iris_draw.c */
 362
 363 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 364
 365 /* iris_pipe_control.c */
 366
 367 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 368                                   uint32_t flags);
 369 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 370                                   struct iris_bo *bo, uint32_t offset,
 371                                   uint64_t imm);
 372 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 373                                 uint32_t flags);
 374
 375 void iris_cache_sets_clear(struct iris_batch *batch);
 376 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 377 void iris_cache_flush_for_render(struct iris_batch *batch,
 378                                  struct iris_bo *bo,
 379                                  enum isl_format format,
 380                                  enum isl_aux_usage aux_usage);
 381 void iris_render_cache_add_bo(struct iris_batch *batch,
 382                               struct iris_bo *bo,
 383                               enum isl_format format,
 384                               enum isl_aux_usage aux_usage);
 385 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 386 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 387
 388 /* iris_blorp.c */
 389
 390 void gen9_init_blorp(struct iris_context *ice);
 391 void gen10_init_blorp(struct iris_context *ice);
 392
 393 /* iris_border_color.c */
 394
 395 void iris_init_border_color_pool(struct iris_context *ice);
 396 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 397 uint32_t iris_upload_border_color(struct iris_context *ice,
 398                                   union pipe_color_union *color);
 399
 400 /* iris_state.c */
 401
 402 void gen9_init_state(struct iris_context *ice);
 403 void gen10_init_state(struct iris_context *ice);
 404
 405 /* iris_program_cache.c */
 406
 407 void iris_init_program_cache(struct iris_context *ice);
 408 void iris_destroy_program_cache(struct iris_context *ice);
 409 void iris_print_program_cache(struct iris_context *ice);
 410 bool iris_bind_cached_shader(struct iris_context *ice,
 411                              enum iris_program_cache_id cache_id,
 412                              const void *key);
 413 void iris_upload_and_bind_shader(struct iris_context *ice,
 414                                  enum iris_program_cache_id cache_id,
 415                                  const void *key,
 416                                  const void *assembly,
 417                                  struct brw_stage_prog_data *prog_data,
 418                                  uint32_t *streamout);
 419 const void *iris_find_previous_compile(const struct iris_context *ice,
 420                                        enum iris_program_cache_id cache_id,
 421                                        unsigned program_string_id);
 422 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 423                               const void *key,
 424                               uint32_t key_size,
 425                               uint32_t *kernel_out,
 426                               void *prog_data_out);
 427 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 428                               const void *key, uint32_t key_size,
 429                               const void *kernel, uint32_t kernel_size,
 430                               const struct brw_stage_prog_data *prog_data,
 431                               uint32_t prog_data_size,
 432                               uint32_t *kernel_out,
 433                               void *prog_data_out);
 434
 435 #endif