src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/common/gen_debug.h"
  30 #include "iris_batch.h"
  31 #include "iris_screen.h"
  32
  33 struct iris_bo;
  34 struct iris_batch;
  35
  36 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  37 #define IRIS_MAX_VIEWPORTS 16
  38
  39 enum iris_dirty {
  40    IRIS_DIRTY_COLOR_CALC_STATE         = (1ull <<  0),
  41    IRIS_DIRTY_POLYGON_STIPPLE          = (1ull <<  1),
  42    IRIS_DIRTY_SCISSOR_RECT             = (1ull <<  2),
  43    IRIS_DIRTY_WM_DEPTH_STENCIL         = (1ull <<  3),
  44    IRIS_DIRTY_CC_VIEWPORT              = (1ull <<  4),
  45    IRIS_DIRTY_SF_CL_VIEWPORT           = (1ull <<  5),
  46    IRIS_DIRTY_PS_BLEND                 = (1ull <<  6),
  47    IRIS_DIRTY_BLEND_STATE              = (1ull <<  7),
  48    IRIS_DIRTY_RASTER                   = (1ull <<  8),
  49    IRIS_DIRTY_CLIP                     = (1ull <<  9),
  50    IRIS_DIRTY_SCISSOR                  = (1ull << 10),
  51    IRIS_DIRTY_LINE_STIPPLE             = (1ull << 11),
  52    IRIS_DIRTY_VERTEX_ELEMENTS          = (1ull << 12),
  53    IRIS_DIRTY_MULTISAMPLE              = (1ull << 13),
  54    IRIS_DIRTY_VERTEX_BUFFERS           = (1ull << 14),
  55    IRIS_DIRTY_SAMPLE_MASK              = (1ull << 15),
  56    IRIS_DIRTY_SAMPLER_STATES_VS        = (1ull << 16),
  57    IRIS_DIRTY_SAMPLER_STATES_TCS       = (1ull << 17),
  58    IRIS_DIRTY_SAMPLER_STATES_TES       = (1ull << 18),
  59    IRIS_DIRTY_SAMPLER_STATES_GS        = (1ull << 19),
  60    IRIS_DIRTY_SAMPLER_STATES_PS        = (1ull << 20),
  61    IRIS_DIRTY_SAMPLER_STATES_CS        = (1ull << 21),
  62    IRIS_DIRTY_UNCOMPILED_VS            = (1ull << 22),
  63    IRIS_DIRTY_UNCOMPILED_TCS           = (1ull << 23),
  64    IRIS_DIRTY_UNCOMPILED_TES           = (1ull << 24),
  65    IRIS_DIRTY_UNCOMPILED_GS            = (1ull << 25),
  66    IRIS_DIRTY_UNCOMPILED_FS            = (1ull << 26),
  67    IRIS_DIRTY_UNCOMPILED_CS            = (1ull << 27),
  68 };
  69
  70 struct iris_depth_stencil_alpha_state;
  71
  72 struct iris_context {
  73    struct pipe_context ctx;
  74
  75    struct pipe_debug_callback dbg;
  76
  77    struct {
  78       struct iris_uncompiled_shader *progs[MESA_SHADER_STAGES];
  79       struct brw_stage_prog_data *prog_data[MESA_SHADER_STAGES];
  80       struct brw_vue_map *last_vue_map;
  81    } shaders;
  82
  83    /** The main batch for rendering */
  84    struct iris_batch render_batch;
  85
  86    struct {
  87       uint64_t dirty;
  88       unsigned num_viewports; // XXX: can viewports + scissors be different?
  89       unsigned num_scissors;
  90       unsigned sample_mask;
  91       struct iris_blend_state *cso_blend;
  92       struct iris_rasterizer_state *cso_rast;
  93       struct iris_depth_stencil_alpha_state *cso_zsa;
  94       struct iris_vertex_element_state *cso_vertex_elements;
  95       struct iris_vertex_buffer_state *cso_vertex_buffers;
  96       struct iris_viewport_state *cso_vp;
  97       struct iris_depth_state *cso_depth;
  98       struct pipe_blend_color blend_color;
  99       struct pipe_poly_stipple poly_stipple;
 100       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 101       struct pipe_stencil_ref stencil_ref;
 102       struct pipe_framebuffer_state framebuffer;
 103
 104       struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 105    } state;
 106 };
 107
 108 #define perf_debug(dbg, ...) do {                      \
 109    if (INTEL_DEBUG & DEBUG_PERF)                       \
 110       dbg_printf(__VA_ARGS__);                         \
 111    if (unlikely(dbg))                                  \
 112       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 113 } while(0)
 114
 115 double get_time(void);
 116
 117 struct pipe_context *
 118 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 119
 120 void iris_init_blit_functions(struct pipe_context *ctx);
 121 void iris_init_clear_functions(struct pipe_context *ctx);
 122 void iris_init_program_functions(struct pipe_context *ctx);
 123 void iris_init_resource_functions(struct pipe_context *ctx);
 124 void iris_init_state_functions(struct pipe_context *ctx);
 125 void iris_init_query_functions(struct pipe_context *ctx);
 126
 127 void iris_upload_render_state(struct iris_context *ice,
 128                               struct iris_batch *batch,
 129                               const struct pipe_draw_info *draw);
 130 void iris_destroy_state(struct iris_context *ice);
 131
 132 void iris_update_compiled_shaders(struct iris_context *ice);
 133
 134 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 135
 136 #endif