src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/dev/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49 #define IRIS_MAX_CLIP_PLANES 8
  50
  51 enum iris_param_domain {
  52    BRW_PARAM_DOMAIN_BUILTIN = 0,
  53    BRW_PARAM_DOMAIN_IMAGE,
  54 };
  55
  56 enum {
  57    DRI_CONF_BO_REUSE_DISABLED,
  58    DRI_CONF_BO_REUSE_ALL
  59 };
  60
  61 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  62 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  63 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  64 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  65 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  66 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  67
  68 /**
  69  * Dirty flags.  When state changes, we flag some combination of these
  70  * to indicate that particular GPU commands need to be re-emitted.
  71  *
  72  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  73  * in rare cases they map to a group of related packets that need to be
  74  * emitted together.
  75  *
  76  * See iris_upload_render_state().
  77  */
  78 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  79 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  80 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  81 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  82 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  83 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  84 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  85 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  86 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  87 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  88 #define IRIS_DIRTY_SBE                      (1ull << 10)
  89 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  90 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  91 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  92 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  93 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  94 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  95 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  96 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  97 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  98 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  99 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
 100 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
 101 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
 102 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
 103 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
 104 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 105 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 106 #define IRIS_DIRTY_VS                       (1ull << 28)
 107 #define IRIS_DIRTY_TCS                      (1ull << 29)
 108 #define IRIS_DIRTY_TES                      (1ull << 30)
 109 #define IRIS_DIRTY_GS                       (1ull << 31)
 110 #define IRIS_DIRTY_FS                       (1ull << 32)
 111 #define IRIS_DIRTY_CS                       (1ull << 33)
 112 #define IRIS_DIRTY_URB                      (1ull << 34)
 113 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 114 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 115 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 116 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 117 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 118 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 119 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 120 #define IRIS_DIRTY_WM                       (1ull << 42)
 121 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 122 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 123 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 124 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 125 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 126 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 127 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 128 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 129 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 130 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 131 #define IRIS_DIRTY_VF                       (1ull << 53)
 132 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 133 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 134 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 135 #define IRIS_DIRTY_VF_STATISTICS            (1ull << 57)
 136
 137 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 138                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 139                                     IRIS_DIRTY_UNCOMPILED_CS | \
 140                                     IRIS_DIRTY_CONSTANTS_CS | \
 141                                     IRIS_DIRTY_BINDINGS_CS | \
 142                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 143
 144 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 145
 146 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 147                                  IRIS_DIRTY_BINDINGS_TCS | \
 148                                  IRIS_DIRTY_BINDINGS_TES | \
 149                                  IRIS_DIRTY_BINDINGS_GS  | \
 150                                  IRIS_DIRTY_BINDINGS_FS  | \
 151                                  IRIS_DIRTY_BINDINGS_CS)
 152
 153 /**
 154  * Non-orthogonal state (NOS) dependency flags.
 155  *
 156  * Shader programs may depend on non-orthogonal state.  These flags are
 157  * used to indicate that a shader's key depends on the state provided by
 158  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 159  * cause the driver to re-compute the shader key, possibly triggering a
 160  * shader recompile.
 161  */
 162 enum iris_nos_dep {
 163    IRIS_NOS_FRAMEBUFFER,
 164    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 165    IRIS_NOS_RASTERIZER,
 166    IRIS_NOS_BLEND,
 167    IRIS_NOS_LAST_VUE_MAP,
 168
 169    IRIS_NOS_COUNT,
 170 };
 171
 172 struct iris_depth_stencil_alpha_state;
 173
 174 /**
 175  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 176  */
 177 enum iris_program_cache_id {
 178    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 179    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 180    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 181    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 182    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 183    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 184    IRIS_CACHE_BLORP,
 185 };
 186
 187 /** @{
 188  *
 189  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 190  * synchronization, pipelined memory writes, and so on.
 191  *
 192  * The bits here are not the actual hardware values.  The actual fields
 193  * move between various generations, so we just have flags for each
 194  * potential operation, and use genxml to encode the actual packet.
 195  */
 196 enum pipe_control_flags
 197 {
 198    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 199    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 200    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 201    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 202    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 203    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 204    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 205    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 206    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 207    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 208    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 209    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 210    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 211    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 212    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 213    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 214    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 215    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 216    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 217    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 218    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 219    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 220    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 221    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 222 };
 223
 224 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 225    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 226     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 227     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 228
 229 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 230    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 231     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 232     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 233     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 234     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 235
 236 enum iris_predicate_state {
 237    /* The first two states are used if we can determine whether to draw
 238     * without having to look at the values in the query object buffer. This
 239     * will happen if there is no conditional render in progress, if the query
 240     * object is already completed or if something else has already added
 241     * samples to the preliminary result.
 242     */
 243    IRIS_PREDICATE_STATE_RENDER,
 244    IRIS_PREDICATE_STATE_DONT_RENDER,
 245
 246    /* In this case whether to draw or not depends on the result of an
 247     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 248     */
 249    IRIS_PREDICATE_STATE_USE_BIT,
 250 };
 251
 252 /** @} */
 253
 254 /**
 255  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
 256  * It primarily contains the NIR for the shader.
 257  *
 258  * Each API-facing shader can be compiled into multiple shader variants,
 259  * based on non-orthogonal state dependencies, recorded in the shader key.
 260  *
 261  * See iris_compiled_shader, which represents a compiled shader variant.
 262  */
 263 struct iris_uncompiled_shader {
 264    struct nir_shader *nir;
 265
 266    struct pipe_stream_output_info stream_output;
 267
 268    /* A SHA1 of the serialized NIR for the disk cache. */
 269    unsigned char nir_sha1[20];
 270
 271    unsigned program_id;
 272
 273    /** Bitfield of (1 << IRIS_NOS_*) flags. */
 274    unsigned nos;
 275
 276    /** Have any shader variants been compiled yet? */
 277    bool compiled_once;
 278
 279    /** Should we use ALT mode for math?  Useful for ARB programs. */
 280    bool use_alt_mode;
 281
 282    /** Constant data scraped from the shader by nir_opt_large_constants */
 283    struct pipe_resource *const_data;
 284
 285    /** Surface state for const_data */
 286    struct iris_state_ref const_data_state;
 287 };
 288
 289 enum iris_surface_group {
 290    IRIS_SURFACE_GROUP_RENDER_TARGET,
 291    IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
 292    IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
 293    IRIS_SURFACE_GROUP_TEXTURE,
 294    IRIS_SURFACE_GROUP_IMAGE,
 295    IRIS_SURFACE_GROUP_UBO,
 296    IRIS_SURFACE_GROUP_SSBO,
 297
 298    IRIS_SURFACE_GROUP_COUNT,
 299 };
 300
 301 enum {
 302    /* Invalid value for a binding table index. */
 303    IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
 304 };
 305
 306 struct iris_binding_table {
 307    uint32_t size_bytes;
 308
 309    /** Number of surfaces in each group, before compacting. */
 310    uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
 311
 312    /** Initial offset of each group. */
 313    uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
 314
 315    /** Mask of surfaces used in each group. */
 316    uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
 317 };
 318
 319 /**
 320  * A compiled shader variant, containing a pointer to the GPU assembly,
 321  * as well as program data and other packets needed by state upload.
 322  *
 323  * There can be several iris_compiled_shader variants per API-level shader
 324  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 325  */
 326 struct iris_compiled_shader {
 327    /** Reference to the uploaded assembly. */
 328    struct iris_state_ref assembly;
 329
 330    /** Pointer to the assembly in the BO's map. */
 331    void *map;
 332
 333    /** The program data (owned by the program cache hash table) */
 334    struct brw_stage_prog_data *prog_data;
 335
 336    /** A list of system values to be uploaded as uniforms. */
 337    enum brw_param_builtin *system_values;
 338    unsigned num_system_values;
 339
 340    /** Number of constbufs expected by the shader. */
 341    unsigned num_cbufs;
 342
 343    /**
 344     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 345     * (the VUE-based information for transform feedback outputs).
 346     */
 347    uint32_t *streamout;
 348
 349    struct iris_binding_table bt;
 350
 351    /**
 352     * Shader packets and other data derived from prog_data.  These must be
 353     * completely determined from prog_data.
 354     */
 355    uint8_t derived_data[0];
 356 };
 357
 358 /**
 359  * API context state that is replicated per shader stage.
 360  */
 361 struct iris_shader_state {
 362    /** Uniform Buffers */
 363    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 364    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 365
 366    bool sysvals_need_upload;
 367
 368    /** Shader Storage Buffers */
 369    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 370    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 371
 372    /** Shader Storage Images (image load store) */
 373    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 374
 375    struct iris_state_ref sampler_table;
 376    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 377    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 378
 379    /** Bitfield of which constant buffers are bound (non-null). */
 380    uint32_t bound_cbufs;
 381
 382    /** Bitfield of which image views are bound (non-null). */
 383    uint32_t bound_image_views;
 384
 385    /** Bitfield of which sampler views are bound (non-null). */
 386    uint32_t bound_sampler_views;
 387
 388    /** Bitfield of which shader storage buffers are bound (non-null). */
 389    uint32_t bound_ssbos;
 390
 391    /** Bitfield of which shader storage buffers are writable. */
 392    uint32_t writable_ssbos;
 393 };
 394
 395 /**
 396  * Gallium CSO for stream output (transform feedback) targets.
 397  */
 398 struct iris_stream_output_target {
 399    struct pipe_stream_output_target base;
 400
 401    /** Storage holding the offset where we're writing in the buffer */
 402    struct iris_state_ref offset;
 403
 404    /** Stride (bytes-per-vertex) during this transform feedback operation */
 405    uint16_t stride;
 406
 407    /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
 408    bool zeroed;
 409 };
 410
 411 /**
 412  * Virtual table for generation-specific (genxml) function calls.
 413  */
 414 struct iris_vtable {
 415    void (*destroy_state)(struct iris_context *ice);
 416    void (*init_render_context)(struct iris_screen *screen,
 417                                struct iris_batch *batch,
 418                                struct iris_vtable *vtbl,
 419                                struct pipe_debug_callback *dbg);
 420    void (*init_compute_context)(struct iris_screen *screen,
 421                                 struct iris_batch *batch,
 422                                 struct iris_vtable *vtbl,
 423                                 struct pipe_debug_callback *dbg);
 424    void (*upload_render_state)(struct iris_context *ice,
 425                                struct iris_batch *batch,
 426                                const struct pipe_draw_info *draw);
 427    void (*update_surface_base_address)(struct iris_batch *batch,
 428                                        struct iris_binder *binder);
 429    void (*upload_compute_state)(struct iris_context *ice,
 430                                 struct iris_batch *batch,
 431                                 const struct pipe_grid_info *grid);
 432    void (*rebind_buffer)(struct iris_context *ice,
 433                          struct iris_resource *res,
 434                          uint64_t old_address);
 435    void (*resolve_conditional_render)(struct iris_context *ice);
 436    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 437                                uint32_t src);
 438    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 439                                uint32_t src);
 440    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 441                                uint32_t val);
 442    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 443                                uint64_t val);
 444    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 445                                struct iris_bo *bo, uint32_t offset);
 446    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 447                                struct iris_bo *bo, uint32_t offset);
 448    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 449                                 struct iris_bo *bo, uint32_t offset,
 450                                 bool predicated);
 451    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 452                                 struct iris_bo *bo, uint32_t offset,
 453                                 bool predicated);
 454    void (*store_data_imm32)(struct iris_batch *batch,
 455                             struct iris_bo *bo, uint32_t offset,
 456                             uint32_t value);
 457    void (*store_data_imm64)(struct iris_batch *batch,
 458                             struct iris_bo *bo, uint32_t offset,
 459                             uint64_t value);
 460    void (*copy_mem_mem)(struct iris_batch *batch,
 461                         struct iris_bo *dst_bo, uint32_t dst_offset,
 462                         struct iris_bo *src_bo, uint32_t src_offset,
 463                         unsigned bytes);
 464    void (*emit_raw_pipe_control)(struct iris_batch *batch,
 465                                  const char *reason, uint32_t flags,
 466                                  struct iris_bo *bo, uint32_t offset,
 467                                  uint64_t imm);
 468
 469    void (*emit_mi_report_perf_count)(struct iris_batch *batch,
 470                                      struct iris_bo *bo,
 471                                      uint32_t offset_in_bytes,
 472                                      uint32_t report_id);
 473
 474    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 475    void (*store_derived_program_state)(struct iris_context *ice,
 476                                        enum iris_program_cache_id cache_id,
 477                                        struct iris_compiled_shader *shader);
 478    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 479                                     const struct brw_vue_map *vue_map);
 480    void (*populate_vs_key)(const struct iris_context *ice,
 481                            const struct shader_info *info,
 482                            gl_shader_stage last_stage,
 483                            struct brw_vs_prog_key *key);
 484    void (*populate_tcs_key)(const struct iris_context *ice,
 485                             struct brw_tcs_prog_key *key);
 486    void (*populate_tes_key)(const struct iris_context *ice,
 487                             const struct shader_info *info,
 488                             gl_shader_stage last_stage,
 489                             struct brw_tes_prog_key *key);
 490    void (*populate_gs_key)(const struct iris_context *ice,
 491                            const struct shader_info *info,
 492                            gl_shader_stage last_stage,
 493                            struct brw_gs_prog_key *key);
 494    void (*populate_fs_key)(const struct iris_context *ice,
 495                            const struct shader_info *info,
 496                            struct brw_wm_prog_key *key);
 497    void (*populate_cs_key)(const struct iris_context *ice,
 498                            struct brw_cs_prog_key *key);
 499    uint32_t (*mocs)(const struct iris_bo *bo);
 500    void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
 501 };
 502
 503 /**
 504  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 505  *
 506  * See iris_border_color.c for more information.
 507  */
 508 struct iris_border_color_pool {
 509    struct iris_bo *bo;
 510    void *map;
 511    unsigned insert_point;
 512
 513    /** Map from border colors to offsets in the buffer. */
 514    struct hash_table *ht;
 515 };
 516
 517 /**
 518  * The API context (derived from pipe_context).
 519  *
 520  * Most driver state is tracked here.
 521  */
 522 struct iris_context {
 523    struct pipe_context ctx;
 524
 525    /** A debug callback for KHR_debug output. */
 526    struct pipe_debug_callback dbg;
 527
 528    /** A device reset status callback for notifying that the GPU is hosed. */
 529    struct pipe_device_reset_callback reset;
 530
 531    /** Slab allocator for iris_transfer_map objects. */
 532    struct slab_child_pool transfer_pool;
 533
 534    struct iris_vtable vtbl;
 535
 536    struct blorp_context blorp;
 537
 538    struct iris_batch batches[IRIS_BATCH_COUNT];
 539
 540    struct u_upload_mgr *query_buffer_uploader;
 541
 542    struct {
 543       struct {
 544          /**
 545           * Either the value of BaseVertex for indexed draw calls or the value
 546           * of the argument <first> for non-indexed draw calls.
 547           */
 548          int firstvertex;
 549          int baseinstance;
 550       } params;
 551
 552       /**
 553        * Resource and offset that stores draw_parameters from the indirect
 554        * buffer or to the buffer that stures the previous values for non
 555        * indirect draws.
 556        */
 557       struct pipe_resource *draw_params_res;
 558       uint32_t draw_params_offset;
 559
 560       struct {
 561          /**
 562           * The value of DrawID. This always comes in from it's own vertex
 563           * buffer since it's not part of the indirect draw parameters.
 564           */
 565          int drawid;
 566
 567          /**
 568           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 569           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 570           */
 571          int is_indexed_draw;
 572       } derived_params;
 573
 574       /**
 575        * Resource and offset used for GL_ARB_shader_draw_parameters which
 576        * contains parameters that are not present in the indirect buffer as
 577        * drawid and is_indexed_draw. They will go in their own vertex element.
 578        */
 579       struct pipe_resource *derived_draw_params_res;
 580       uint32_t derived_draw_params_offset;
 581
 582       bool is_indirect;
 583    } draw;
 584
 585    struct {
 586       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 587       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 588       struct brw_vue_map *last_vue_map;
 589
 590       struct u_upload_mgr *uploader;
 591       struct hash_table *cache;
 592
 593       unsigned urb_size;
 594
 595       /** Is a GS or TES outputting points or lines? */
 596       bool output_topology_is_points_or_lines;
 597
 598       /* Track last VS URB entry size */
 599       unsigned last_vs_entry_size;
 600
 601       /**
 602        * Scratch buffers for various sizes and stages.
 603        *
 604        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 605        * and shader stage.
 606        */
 607       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 608    } shaders;
 609
 610    struct {
 611       struct iris_query *query;
 612       bool condition;
 613    } condition;
 614
 615    struct gen_perf_context *perf_ctx;
 616
 617    struct {
 618       uint64_t dirty;
 619       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 620
 621       unsigned num_viewports;
 622       unsigned sample_mask;
 623       struct iris_blend_state *cso_blend;
 624       struct iris_rasterizer_state *cso_rast;
 625       struct iris_depth_stencil_alpha_state *cso_zsa;
 626       struct iris_vertex_element_state *cso_vertex_elements;
 627       struct pipe_blend_color blend_color;
 628       struct pipe_poly_stipple poly_stipple;
 629       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 630       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 631       struct pipe_stencil_ref stencil_ref;
 632       struct pipe_framebuffer_state framebuffer;
 633       struct pipe_clip_state clip_planes;
 634
 635       float default_outer_level[4];
 636       float default_inner_level[2];
 637
 638       /** Bitfield of which vertex buffers are bound (non-null). */
 639       uint64_t bound_vertex_buffers;
 640
 641       bool primitive_restart;
 642       unsigned cut_index;
 643       enum pipe_prim_type prim_mode:8;
 644       bool prim_is_points_or_lines;
 645       uint8_t vertices_per_patch;
 646
 647       bool window_space_position;
 648
 649       /** The last compute grid size */
 650       uint32_t last_grid[3];
 651       /** Reference to the BO containing the compute grid size */
 652       struct iris_state_ref grid_size;
 653       /** Reference to the SURFACE_STATE for the compute grid resource */
 654       struct iris_state_ref grid_surf_state;
 655
 656       /**
 657        * Array of aux usages for drawing, altered to account for any
 658        * self-dependencies from resources bound for sampling and rendering.
 659        */
 660       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 661
 662       /** Bitfield of whether color blending is enabled for RT[i] */
 663       uint8_t blend_enables;
 664
 665       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 666       bool depth_writes_enabled;
 667
 668       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 669       bool stencil_writes_enabled;
 670
 671       /** GenX-specific current state */
 672       struct iris_genx_state *genx;
 673
 674       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 675
 676       /** Do vertex shader uses shader draw parameters ? */
 677       bool vs_uses_draw_params;
 678       bool vs_uses_derived_draw_params;
 679       bool vs_needs_sgvs_element;
 680
 681       /** Do vertex shader uses edge flag ? */
 682       bool vs_needs_edge_flag;
 683
 684       /** Do any samplers need border color?  One bit per shader stage. */
 685       uint8_t need_border_colors;
 686
 687       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 688       bool streamout_active;
 689
 690       bool statistics_counters_enabled;
 691
 692       /** Current conditional rendering mode */
 693       enum iris_predicate_state predicate;
 694
 695       /**
 696        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 697        * render context that needs to be uploaded to the compute context.
 698        */
 699       struct iris_bo *compute_predicate;
 700
 701       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 702       bool prims_generated_query_active;
 703
 704       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 705       uint32_t *streamout;
 706
 707       /** The SURFACE_STATE for a 1x1x1 null surface. */
 708       struct iris_state_ref unbound_tex;
 709
 710       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 711       struct iris_state_ref null_fb;
 712
 713       struct u_upload_mgr *surface_uploader;
 714       struct u_upload_mgr *dynamic_uploader;
 715
 716       struct iris_binder binder;
 717
 718       struct iris_border_color_pool border_color_pool;
 719
 720       /** The high 16-bits of the last VBO/index buffer addresses */
 721       uint16_t last_vbo_high_bits[33];
 722       uint16_t last_index_bo_high_bits;
 723
 724       /**
 725        * Resources containing streamed state which our render context
 726        * currently points to.  Used to re-add these to the validation
 727        * list when we start a new batch and haven't resubmitted commands.
 728        */
 729       struct {
 730          struct pipe_resource *cc_vp;
 731          struct pipe_resource *sf_cl_vp;
 732          struct pipe_resource *color_calc;
 733          struct pipe_resource *scissor;
 734          struct pipe_resource *blend;
 735          struct pipe_resource *index_buffer;
 736          struct pipe_resource *cs_thread_ids;
 737          struct pipe_resource *cs_desc;
 738       } last_res;
 739
 740       /** Records the size of variable-length state for INTEL_DEBUG=bat */
 741       struct hash_table_u64 *sizes;
 742
 743       /** Last rendering scale argument provided to genX(emit_hashing_mode). */
 744       unsigned current_hash_scale;
 745    } state;
 746 };
 747
 748 #define perf_debug(dbg, ...) do {                      \
 749    if (INTEL_DEBUG & DEBUG_PERF)                       \
 750       dbg_printf(__VA_ARGS__);                         \
 751    if (unlikely(dbg))                                  \
 752       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 753 } while(0)
 754
 755 double get_time(void);
 756
 757 struct pipe_context *
 758 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 759
 760 void iris_lost_context_state(struct iris_batch *batch);
 761
 762 void iris_init_blit_functions(struct pipe_context *ctx);
 763 void iris_init_clear_functions(struct pipe_context *ctx);
 764 void iris_init_program_functions(struct pipe_context *ctx);
 765 void iris_init_resource_functions(struct pipe_context *ctx);
 766 void iris_update_compiled_shaders(struct iris_context *ice);
 767 void iris_update_compiled_compute_shader(struct iris_context *ice);
 768 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 769                                     uint32_t *dst);
 770
 771
 772 /* iris_blit.c */
 773 void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
 774                                   struct blorp_surf *surf,
 775                                   struct pipe_resource *p_res,
 776                                   enum isl_aux_usage aux_usage,
 777                                   unsigned level,
 778                                   bool is_render_target);
 779 void iris_copy_region(struct blorp_context *blorp,
 780                       struct iris_batch *batch,
 781                       struct pipe_resource *dst,
 782                       unsigned dst_level,
 783                       unsigned dstx, unsigned dsty, unsigned dstz,
 784                       struct pipe_resource *src,
 785                       unsigned src_level,
 786                       const struct pipe_box *src_box);
 787
 788 /* iris_draw.c */
 789
 790 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 791 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 792
 793 /* iris_pipe_control.c */
 794
 795 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 796                                   const char *reason, uint32_t flags);
 797 void iris_emit_pipe_control_write(struct iris_batch *batch,
 798                                   const char *reason, uint32_t flags,
 799                                   struct iris_bo *bo, uint32_t offset,
 800                                   uint64_t imm);
 801 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 802                                 const char *reason, uint32_t flags);
 803
 804 void iris_init_flush_functions(struct pipe_context *ctx);
 805
 806 /* iris_border_color.c */
 807
 808 void iris_init_border_color_pool(struct iris_context *ice);
 809 void iris_destroy_border_color_pool(struct iris_context *ice);
 810 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 811 uint32_t iris_upload_border_color(struct iris_context *ice,
 812                                   union pipe_color_union *color);
 813
 814 /* iris_program.c */
 815 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
 816                                      struct pipe_shader_buffer *buf,
 817                                      struct iris_state_ref *surf_state,
 818                                      bool ssbo);
 819 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 820                                                gl_shader_stage stage);
 821 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 822                                        unsigned per_thread_scratch,
 823                                        gl_shader_stage stage);
 824 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
 825                                  enum iris_surface_group group,
 826                                  uint32_t index);
 827 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
 828                                  enum iris_surface_group group,
 829                                  uint32_t bti);
 830
 831 /* iris_disk_cache.c */
 832
 833 void iris_disk_cache_store(struct disk_cache *cache,
 834                            const struct iris_uncompiled_shader *ish,
 835                            const struct iris_compiled_shader *shader,
 836                            const void *prog_key,
 837                            uint32_t prog_key_size);
 838 struct iris_compiled_shader *
 839 iris_disk_cache_retrieve(struct iris_context *ice,
 840                          const struct iris_uncompiled_shader *ish,
 841                          const void *prog_key,
 842                          uint32_t prog_key_size);
 843
 844 /* iris_program_cache.c */
 845
 846 void iris_init_program_cache(struct iris_context *ice);
 847 void iris_destroy_program_cache(struct iris_context *ice);
 848 void iris_print_program_cache(struct iris_context *ice);
 849 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 850                                                      enum iris_program_cache_id,
 851                                                      uint32_t key_size,
 852                                                      const void *key);
 853 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 854                                                 enum iris_program_cache_id,
 855                                                 uint32_t key_size,
 856                                                 const void *key,
 857                                                 const void *assembly,
 858                                                 struct brw_stage_prog_data *,
 859                                                 uint32_t *streamout,
 860                                                 enum brw_param_builtin *sysv,
 861                                                 unsigned num_system_values,
 862                                                 unsigned num_cbufs,
 863                                                 const struct iris_binding_table *bt);
 864 const void *iris_find_previous_compile(const struct iris_context *ice,
 865                                        enum iris_program_cache_id cache_id,
 866                                        unsigned program_string_id);
 867 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 868                               const void *key,
 869                               uint32_t key_size,
 870                               uint32_t *kernel_out,
 871                               void *prog_data_out);
 872 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 873                               const void *key, uint32_t key_size,
 874                               const void *kernel, uint32_t kernel_size,
 875                               const struct brw_stage_prog_data *prog_data,
 876                               uint32_t prog_data_size,
 877                               uint32_t *kernel_out,
 878                               void *prog_data_out);
 879
 880 /* iris_resolve.c */
 881
 882 void iris_predraw_resolve_inputs(struct iris_context *ice,
 883                                  struct iris_batch *batch,
 884                                  bool *draw_aux_buffer_disabled,
 885                                  gl_shader_stage stage,
 886                                  bool consider_framebuffer);
 887 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 888                                       struct iris_batch *batch,
 889                                       bool *draw_aux_buffer_disabled);
 890 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 891                                            struct iris_batch *batch);
 892 void iris_cache_sets_clear(struct iris_batch *batch);
 893 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 894 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 895 void iris_cache_flush_for_render(struct iris_batch *batch,
 896                                  struct iris_bo *bo,
 897                                  enum isl_format format,
 898                                  enum isl_aux_usage aux_usage);
 899 void iris_render_cache_add_bo(struct iris_batch *batch,
 900                               struct iris_bo *bo,
 901                               enum isl_format format,
 902                               enum isl_aux_usage aux_usage);
 903 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 904 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 905 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
 906                                struct pipe_driver_query_info *info);
 907 int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
 908                                      unsigned index,
 909                                      struct pipe_driver_query_group_info *info);
 910
 911 /* iris_state.c */
 912 void gen9_toggle_preemption(struct iris_context *ice,
 913                             struct iris_batch *batch,
 914                             const struct pipe_draw_info *draw);
 915
 916 #ifdef genX
 917 #  include "iris_genx_protos.h"
 918 #else
 919 #  define genX(x) gen4_##x
 920 #  include "iris_genx_protos.h"
 921 #  undef genX
 922 #  define genX(x) gen5_##x
 923 #  include "iris_genx_protos.h"
 924 #  undef genX
 925 #  define genX(x) gen6_##x
 926 #  include "iris_genx_protos.h"
 927 #  undef genX
 928 #  define genX(x) gen7_##x
 929 #  include "iris_genx_protos.h"
 930 #  undef genX
 931 #  define genX(x) gen75_##x
 932 #  include "iris_genx_protos.h"
 933 #  undef genX
 934 #  define genX(x) gen8_##x
 935 #  include "iris_genx_protos.h"
 936 #  undef genX
 937 #  define genX(x) gen9_##x
 938 #  include "iris_genx_protos.h"
 939 #  undef genX
 940 #  define genX(x) gen10_##x
 941 #  include "iris_genx_protos.h"
 942 #  undef genX
 943 #  define genX(x) gen11_##x
 944 #  include "iris_genx_protos.h"
 945 #  undef genX
 946 #  define genX(x) gen12_##x
 947 #  include "iris_genx_protos.h"
 948 #  undef genX
 949 #endif
 950
 951 #endif