2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_CONTEXT_H
24 #define IRIS_CONTEXT_H
26 #include "pipe/p_context.h"
27 #include "pipe/p_state.h"
28 #include "util/u_debug.h"
29 #include "intel/blorp/blorp.h"
30 #include "intel/dev/gen_debug.h"
31 #include "intel/common/gen_l3_config.h"
32 #include "intel/compiler/brw_compiler.h"
33 #include "iris_batch.h"
34 #include "iris_binder.h"
35 #include "iris_fence.h"
36 #include "iris_resource.h"
37 #include "iris_screen.h"
44 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
45 #define IRIS_MAX_TEXTURE_SAMPLERS 32
46 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
47 #define IRIS_MAX_ABOS 16
48 #define IRIS_MAX_SSBOS 16
49 #define IRIS_MAX_VIEWPORTS 16
50 #define IRIS_MAX_CLIP_PLANES 8
52 enum iris_param_domain
{
53 BRW_PARAM_DOMAIN_BUILTIN
= 0,
54 BRW_PARAM_DOMAIN_IMAGE
,
58 DRI_CONF_BO_REUSE_DISABLED
,
62 #define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
63 #define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
64 #define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
65 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
66 #define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
67 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
70 * Dirty flags. When state changes, we flag some combination of these
71 * to indicate that particular GPU commands need to be re-emitted.
73 * Each bit typically corresponds to a single 3DSTATE_* command packet, but
74 * in rare cases they map to a group of related packets that need to be
77 * See iris_upload_render_state().
79 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
80 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
81 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
82 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
83 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
84 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
85 #define IRIS_DIRTY_PS_BLEND (1ull << 6)
86 #define IRIS_DIRTY_BLEND_STATE (1ull << 7)
87 #define IRIS_DIRTY_RASTER (1ull << 8)
88 #define IRIS_DIRTY_CLIP (1ull << 9)
89 #define IRIS_DIRTY_SBE (1ull << 10)
90 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
91 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
92 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
93 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
94 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
95 #define IRIS_DIRTY_SAMPLER_STATES_VS (1ull << 16)
96 #define IRIS_DIRTY_SAMPLER_STATES_TCS (1ull << 17)
97 #define IRIS_DIRTY_SAMPLER_STATES_TES (1ull << 18)
98 #define IRIS_DIRTY_SAMPLER_STATES_GS (1ull << 19)
99 #define IRIS_DIRTY_SAMPLER_STATES_PS (1ull << 20)
100 #define IRIS_DIRTY_SAMPLER_STATES_CS (1ull << 21)
101 #define IRIS_DIRTY_UNCOMPILED_VS (1ull << 22)
102 #define IRIS_DIRTY_UNCOMPILED_TCS (1ull << 23)
103 #define IRIS_DIRTY_UNCOMPILED_TES (1ull << 24)
104 #define IRIS_DIRTY_UNCOMPILED_GS (1ull << 25)
105 #define IRIS_DIRTY_UNCOMPILED_FS (1ull << 26)
106 #define IRIS_DIRTY_UNCOMPILED_CS (1ull << 27)
107 #define IRIS_DIRTY_VS (1ull << 28)
108 #define IRIS_DIRTY_TCS (1ull << 29)
109 #define IRIS_DIRTY_TES (1ull << 30)
110 #define IRIS_DIRTY_GS (1ull << 31)
111 #define IRIS_DIRTY_FS (1ull << 32)
112 #define IRIS_DIRTY_CS (1ull << 33)
113 #define IRIS_DIRTY_URB (1ull << 34)
114 #define IRIS_SHIFT_FOR_DIRTY_CONSTANTS 35
115 #define IRIS_DIRTY_CONSTANTS_VS (1ull << 35)
116 #define IRIS_DIRTY_CONSTANTS_TCS (1ull << 36)
117 #define IRIS_DIRTY_CONSTANTS_TES (1ull << 37)
118 #define IRIS_DIRTY_CONSTANTS_GS (1ull << 38)
119 #define IRIS_DIRTY_CONSTANTS_FS (1ull << 39)
120 #define IRIS_DIRTY_CONSTANTS_CS (1ull << 40)
121 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 41)
122 #define IRIS_DIRTY_WM (1ull << 42)
123 #define IRIS_DIRTY_BINDINGS_VS (1ull << 43)
124 #define IRIS_DIRTY_BINDINGS_TCS (1ull << 44)
125 #define IRIS_DIRTY_BINDINGS_TES (1ull << 45)
126 #define IRIS_DIRTY_BINDINGS_GS (1ull << 46)
127 #define IRIS_DIRTY_BINDINGS_FS (1ull << 47)
128 #define IRIS_DIRTY_BINDINGS_CS (1ull << 48)
129 #define IRIS_DIRTY_SO_BUFFERS (1ull << 49)
130 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 50)
131 #define IRIS_DIRTY_STREAMOUT (1ull << 51)
132 #define IRIS_DIRTY_VF_SGVS (1ull << 52)
133 #define IRIS_DIRTY_VF (1ull << 53)
134 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54)
135 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 55)
136 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
137 #define IRIS_DIRTY_VF_STATISTICS (1ull << 57)
138 #define IRIS_DIRTY_PMA_FIX (1ull << 58)
139 #define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 59)
140 #define IRIS_DIRTY_RENDER_BUFFER (1ull << 60)
142 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
143 IRIS_DIRTY_SAMPLER_STATES_CS | \
144 IRIS_DIRTY_UNCOMPILED_CS | \
145 IRIS_DIRTY_CONSTANTS_CS | \
146 IRIS_DIRTY_BINDINGS_CS | \
147 IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
149 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
151 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS | \
152 IRIS_DIRTY_BINDINGS_TCS | \
153 IRIS_DIRTY_BINDINGS_TES | \
154 IRIS_DIRTY_BINDINGS_GS | \
155 IRIS_DIRTY_BINDINGS_FS | \
156 IRIS_DIRTY_BINDINGS_CS | \
157 IRIS_DIRTY_RENDER_BUFFER)
160 * Non-orthogonal state (NOS) dependency flags.
162 * Shader programs may depend on non-orthogonal state. These flags are
163 * used to indicate that a shader's key depends on the state provided by
164 * a certain Gallium CSO. Changing any CSOs marked as a dependency will
165 * cause the driver to re-compute the shader key, possibly triggering a
169 IRIS_NOS_FRAMEBUFFER
,
170 IRIS_NOS_DEPTH_STENCIL_ALPHA
,
173 IRIS_NOS_LAST_VUE_MAP
,
180 * Program cache keys for state based recompiles.
183 struct iris_base_prog_key
{
184 unsigned program_string_id
;
187 struct iris_vue_prog_key
{
188 struct iris_base_prog_key base
;
190 unsigned nr_userclip_plane_consts
:4;
193 struct iris_vs_prog_key
{
194 struct iris_vue_prog_key vue
;
197 struct iris_tcs_prog_key
{
198 struct iris_vue_prog_key vue
;
200 uint16_t tes_primitive_mode
;
202 uint8_t input_vertices
;
204 bool quads_workaround
;
206 /** A bitfield of per-patch outputs written. */
207 uint32_t patch_outputs_written
;
209 /** A bitfield of per-vertex outputs written. */
210 uint64_t outputs_written
;
213 struct iris_tes_prog_key
{
214 struct iris_vue_prog_key vue
;
216 /** A bitfield of per-patch inputs read. */
217 uint32_t patch_inputs_read
;
219 /** A bitfield of per-vertex inputs read. */
220 uint64_t inputs_read
;
223 struct iris_gs_prog_key
{
224 struct iris_vue_prog_key vue
;
227 struct iris_fs_prog_key
{
228 struct iris_base_prog_key base
;
230 unsigned nr_color_regions
:5;
232 bool alpha_test_replicate_alpha
:1;
233 bool alpha_to_coverage
:1;
234 bool clamp_fragment_color
:1;
235 bool persample_interp
:1;
236 bool multisample_fbo
:1;
237 bool force_dual_color_blend
:1;
238 bool coherent_fb_fetch
:1;
240 uint8_t color_outputs_valid
;
241 uint64_t input_slots_valid
;
244 struct iris_cs_prog_key
{
245 struct iris_base_prog_key base
;
250 struct iris_depth_stencil_alpha_state
;
253 * Cache IDs for the in-memory program cache (ice->shaders.cache).
255 enum iris_program_cache_id
{
256 IRIS_CACHE_VS
= MESA_SHADER_VERTEX
,
257 IRIS_CACHE_TCS
= MESA_SHADER_TESS_CTRL
,
258 IRIS_CACHE_TES
= MESA_SHADER_TESS_EVAL
,
259 IRIS_CACHE_GS
= MESA_SHADER_GEOMETRY
,
260 IRIS_CACHE_FS
= MESA_SHADER_FRAGMENT
,
261 IRIS_CACHE_CS
= MESA_SHADER_COMPUTE
,
267 * Defines for PIPE_CONTROL operations, which trigger cache flushes,
268 * synchronization, pipelined memory writes, and so on.
270 * The bits here are not the actual hardware values. The actual fields
271 * move between various generations, so we just have flags for each
272 * potential operation, and use genxml to encode the actual packet.
274 enum pipe_control_flags
276 PIPE_CONTROL_FLUSH_LLC
= (1 << 1),
277 PIPE_CONTROL_LRI_POST_SYNC_OP
= (1 << 2),
278 PIPE_CONTROL_STORE_DATA_INDEX
= (1 << 3),
279 PIPE_CONTROL_CS_STALL
= (1 << 4),
280 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
= (1 << 5),
281 PIPE_CONTROL_SYNC_GFDT
= (1 << 6),
282 PIPE_CONTROL_TLB_INVALIDATE
= (1 << 7),
283 PIPE_CONTROL_MEDIA_STATE_CLEAR
= (1 << 8),
284 PIPE_CONTROL_WRITE_IMMEDIATE
= (1 << 9),
285 PIPE_CONTROL_WRITE_DEPTH_COUNT
= (1 << 10),
286 PIPE_CONTROL_WRITE_TIMESTAMP
= (1 << 11),
287 PIPE_CONTROL_DEPTH_STALL
= (1 << 12),
288 PIPE_CONTROL_RENDER_TARGET_FLUSH
= (1 << 13),
289 PIPE_CONTROL_INSTRUCTION_INVALIDATE
= (1 << 14),
290 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
= (1 << 15),
291 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
= (1 << 16),
292 PIPE_CONTROL_NOTIFY_ENABLE
= (1 << 17),
293 PIPE_CONTROL_FLUSH_ENABLE
= (1 << 18),
294 PIPE_CONTROL_DATA_CACHE_FLUSH
= (1 << 19),
295 PIPE_CONTROL_VF_CACHE_INVALIDATE
= (1 << 20),
296 PIPE_CONTROL_CONST_CACHE_INVALIDATE
= (1 << 21),
297 PIPE_CONTROL_STATE_CACHE_INVALIDATE
= (1 << 22),
298 PIPE_CONTROL_STALL_AT_SCOREBOARD
= (1 << 23),
299 PIPE_CONTROL_DEPTH_CACHE_FLUSH
= (1 << 24),
300 PIPE_CONTROL_TILE_CACHE_FLUSH
= (1 << 25),
301 PIPE_CONTROL_FLUSH_HDC
= (1 << 26),
304 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
305 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
306 PIPE_CONTROL_DATA_CACHE_FLUSH | \
307 PIPE_CONTROL_RENDER_TARGET_FLUSH)
309 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
310 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
311 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
312 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
313 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
314 PIPE_CONTROL_INSTRUCTION_INVALIDATE)
316 enum iris_predicate_state
{
317 /* The first two states are used if we can determine whether to draw
318 * without having to look at the values in the query object buffer. This
319 * will happen if there is no conditional render in progress, if the query
320 * object is already completed or if something else has already added
321 * samples to the preliminary result.
323 IRIS_PREDICATE_STATE_RENDER
,
324 IRIS_PREDICATE_STATE_DONT_RENDER
,
326 /* In this case whether to draw or not depends on the result of an
327 * MI_PREDICATE command so the predicate enable bit needs to be checked.
329 IRIS_PREDICATE_STATE_USE_BIT
,
335 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
336 * It primarily contains the NIR for the shader.
338 * Each API-facing shader can be compiled into multiple shader variants,
339 * based on non-orthogonal state dependencies, recorded in the shader key.
341 * See iris_compiled_shader, which represents a compiled shader variant.
343 struct iris_uncompiled_shader
{
344 struct nir_shader
*nir
;
346 struct pipe_stream_output_info stream_output
;
348 /* A SHA1 of the serialized NIR for the disk cache. */
349 unsigned char nir_sha1
[20];
353 /** Bitfield of (1 << IRIS_NOS_*) flags. */
356 /** Have any shader variants been compiled yet? */
359 /** Should we use ALT mode for math? Useful for ARB programs. */
362 bool needs_edge_flag
;
364 /** Constant data scraped from the shader by nir_opt_large_constants */
365 struct pipe_resource
*const_data
;
367 /** Surface state for const_data */
368 struct iris_state_ref const_data_state
;
371 enum iris_surface_group
{
372 IRIS_SURFACE_GROUP_RENDER_TARGET
,
373 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
,
374 IRIS_SURFACE_GROUP_CS_WORK_GROUPS
,
375 IRIS_SURFACE_GROUP_TEXTURE
,
376 IRIS_SURFACE_GROUP_IMAGE
,
377 IRIS_SURFACE_GROUP_UBO
,
378 IRIS_SURFACE_GROUP_SSBO
,
380 IRIS_SURFACE_GROUP_COUNT
,
384 /* Invalid value for a binding table index. */
385 IRIS_SURFACE_NOT_USED
= 0xa0a0a0a0,
388 struct iris_binding_table
{
391 /** Number of surfaces in each group, before compacting. */
392 uint32_t sizes
[IRIS_SURFACE_GROUP_COUNT
];
394 /** Initial offset of each group. */
395 uint32_t offsets
[IRIS_SURFACE_GROUP_COUNT
];
397 /** Mask of surfaces used in each group. */
398 uint64_t used_mask
[IRIS_SURFACE_GROUP_COUNT
];
402 * A compiled shader variant, containing a pointer to the GPU assembly,
403 * as well as program data and other packets needed by state upload.
405 * There can be several iris_compiled_shader variants per API-level shader
406 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
408 struct iris_compiled_shader
{
409 /** Reference to the uploaded assembly. */
410 struct iris_state_ref assembly
;
412 /** Pointer to the assembly in the BO's map. */
415 /** The program data (owned by the program cache hash table) */
416 struct brw_stage_prog_data
*prog_data
;
418 /** A list of system values to be uploaded as uniforms. */
419 enum brw_param_builtin
*system_values
;
420 unsigned num_system_values
;
422 /** Number of constbufs expected by the shader. */
426 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
427 * (the VUE-based information for transform feedback outputs).
431 struct iris_binding_table bt
;
434 * Shader packets and other data derived from prog_data. These must be
435 * completely determined from prog_data.
437 uint8_t derived_data
[0];
441 * API context state that is replicated per shader stage.
443 struct iris_shader_state
{
444 /** Uniform Buffers */
445 struct pipe_shader_buffer constbuf
[PIPE_MAX_CONSTANT_BUFFERS
];
446 struct iris_state_ref constbuf_surf_state
[PIPE_MAX_CONSTANT_BUFFERS
];
448 bool sysvals_need_upload
;
450 /** Shader Storage Buffers */
451 struct pipe_shader_buffer ssbo
[PIPE_MAX_SHADER_BUFFERS
];
452 struct iris_state_ref ssbo_surf_state
[PIPE_MAX_SHADER_BUFFERS
];
454 /** Shader Storage Images (image load store) */
455 struct iris_image_view image
[PIPE_MAX_SHADER_IMAGES
];
457 struct iris_state_ref sampler_table
;
458 struct iris_sampler_state
*samplers
[IRIS_MAX_TEXTURE_SAMPLERS
];
459 struct iris_sampler_view
*textures
[IRIS_MAX_TEXTURE_SAMPLERS
];
461 /** Bitfield of which constant buffers are bound (non-null). */
462 uint32_t bound_cbufs
;
464 /** Bitfield of which image views are bound (non-null). */
465 uint32_t bound_image_views
;
467 /** Bitfield of which sampler views are bound (non-null). */
468 uint32_t bound_sampler_views
;
470 /** Bitfield of which shader storage buffers are bound (non-null). */
471 uint32_t bound_ssbos
;
473 /** Bitfield of which shader storage buffers are writable. */
474 uint32_t writable_ssbos
;
478 * Gallium CSO for stream output (transform feedback) targets.
480 struct iris_stream_output_target
{
481 struct pipe_stream_output_target base
;
483 /** Storage holding the offset where we're writing in the buffer */
484 struct iris_state_ref offset
;
486 /** Stride (bytes-per-vertex) during this transform feedback operation */
489 /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
494 * Virtual table for generation-specific (genxml) function calls.
497 void (*destroy_state
)(struct iris_context
*ice
);
498 void (*init_render_context
)(struct iris_batch
*batch
);
499 void (*init_compute_context
)(struct iris_batch
*batch
);
500 void (*upload_render_state
)(struct iris_context
*ice
,
501 struct iris_batch
*batch
,
502 const struct pipe_draw_info
*draw
);
503 void (*update_surface_base_address
)(struct iris_batch
*batch
,
504 struct iris_binder
*binder
);
505 void (*upload_compute_state
)(struct iris_context
*ice
,
506 struct iris_batch
*batch
,
507 const struct pipe_grid_info
*grid
);
508 void (*rebind_buffer
)(struct iris_context
*ice
,
509 struct iris_resource
*res
);
510 void (*resolve_conditional_render
)(struct iris_context
*ice
);
511 void (*load_register_reg32
)(struct iris_batch
*batch
, uint32_t dst
,
513 void (*load_register_reg64
)(struct iris_batch
*batch
, uint32_t dst
,
515 void (*load_register_imm32
)(struct iris_batch
*batch
, uint32_t reg
,
517 void (*load_register_imm64
)(struct iris_batch
*batch
, uint32_t reg
,
519 void (*load_register_mem32
)(struct iris_batch
*batch
, uint32_t reg
,
520 struct iris_bo
*bo
, uint32_t offset
);
521 void (*load_register_mem64
)(struct iris_batch
*batch
, uint32_t reg
,
522 struct iris_bo
*bo
, uint32_t offset
);
523 void (*store_register_mem32
)(struct iris_batch
*batch
, uint32_t reg
,
524 struct iris_bo
*bo
, uint32_t offset
,
526 void (*store_register_mem64
)(struct iris_batch
*batch
, uint32_t reg
,
527 struct iris_bo
*bo
, uint32_t offset
,
529 void (*store_data_imm32
)(struct iris_batch
*batch
,
530 struct iris_bo
*bo
, uint32_t offset
,
532 void (*store_data_imm64
)(struct iris_batch
*batch
,
533 struct iris_bo
*bo
, uint32_t offset
,
535 void (*copy_mem_mem
)(struct iris_batch
*batch
,
536 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
537 struct iris_bo
*src_bo
, uint32_t src_offset
,
539 void (*emit_raw_pipe_control
)(struct iris_batch
*batch
,
540 const char *reason
, uint32_t flags
,
541 struct iris_bo
*bo
, uint32_t offset
,
544 void (*emit_mi_report_perf_count
)(struct iris_batch
*batch
,
546 uint32_t offset_in_bytes
,
549 unsigned (*derived_program_state_size
)(enum iris_program_cache_id id
);
550 void (*store_derived_program_state
)(struct iris_context
*ice
,
551 enum iris_program_cache_id cache_id
,
552 struct iris_compiled_shader
*shader
);
553 uint32_t *(*create_so_decl_list
)(const struct pipe_stream_output_info
*sol
,
554 const struct brw_vue_map
*vue_map
);
555 void (*populate_vs_key
)(const struct iris_context
*ice
,
556 const struct shader_info
*info
,
557 gl_shader_stage last_stage
,
558 struct iris_vs_prog_key
*key
);
559 void (*populate_tcs_key
)(const struct iris_context
*ice
,
560 struct iris_tcs_prog_key
*key
);
561 void (*populate_tes_key
)(const struct iris_context
*ice
,
562 const struct shader_info
*info
,
563 gl_shader_stage last_stage
,
564 struct iris_tes_prog_key
*key
);
565 void (*populate_gs_key
)(const struct iris_context
*ice
,
566 const struct shader_info
*info
,
567 gl_shader_stage last_stage
,
568 struct iris_gs_prog_key
*key
);
569 void (*populate_fs_key
)(const struct iris_context
*ice
,
570 const struct shader_info
*info
,
571 struct iris_fs_prog_key
*key
);
572 void (*populate_cs_key
)(const struct iris_context
*ice
,
573 struct iris_cs_prog_key
*key
);
574 uint32_t (*mocs
)(const struct iris_bo
*bo
, const struct isl_device
*isl_dev
);
575 void (*lost_genx_state
)(struct iris_context
*ice
, struct iris_batch
*batch
);
579 * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
581 * See iris_border_color.c for more information.
583 struct iris_border_color_pool
{
586 unsigned insert_point
;
588 /** Map from border colors to offsets in the buffer. */
589 struct hash_table
*ht
;
593 * The API context (derived from pipe_context).
595 * Most driver state is tracked here.
597 struct iris_context
{
598 struct pipe_context ctx
;
600 /** A debug callback for KHR_debug output. */
601 struct pipe_debug_callback dbg
;
603 /** A device reset status callback for notifying that the GPU is hosed. */
604 struct pipe_device_reset_callback reset
;
606 /** Slab allocator for iris_transfer_map objects. */
607 struct slab_child_pool transfer_pool
;
609 struct iris_vtable vtbl
;
611 struct blorp_context blorp
;
613 struct iris_batch batches
[IRIS_BATCH_COUNT
];
615 struct u_upload_mgr
*query_buffer_uploader
;
620 * Either the value of BaseVertex for indexed draw calls or the value
621 * of the argument <first> for non-indexed draw calls.
628 * Are the above values the ones stored in the draw_params buffer?
629 * If so, we can compare them against new values to see if anything
630 * changed. If not, we need to assume they changed.
635 * Resource and offset that stores draw_parameters from the indirect
636 * buffer or to the buffer that stures the previous values for non
639 struct iris_state_ref draw_params
;
643 * The value of DrawID. This always comes in from it's own vertex
644 * buffer since it's not part of the indirect draw parameters.
649 * Stores if an indexed or non-indexed draw (~0/0). Useful to
650 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
656 * Resource and offset used for GL_ARB_shader_draw_parameters which
657 * contains parameters that are not present in the indirect buffer as
658 * drawid and is_indexed_draw. They will go in their own vertex element.
660 struct iris_state_ref derived_draw_params
;
664 struct iris_uncompiled_shader
*uncompiled
[MESA_SHADER_STAGES
];
665 struct iris_compiled_shader
*prog
[MESA_SHADER_STAGES
];
666 struct brw_vue_map
*last_vue_map
;
668 struct u_upload_mgr
*uploader
;
669 struct hash_table
*cache
;
671 /** Is a GS or TES outputting points or lines? */
672 bool output_topology_is_points_or_lines
;
675 * Scratch buffers for various sizes and stages.
677 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
680 struct iris_bo
*scratch_bos
[1 << 4][MESA_SHADER_STAGES
];
684 struct iris_query
*query
;
688 struct gen_perf_context
*perf_ctx
;
690 /** Frame number for debug prints */
695 uint64_t dirty_for_nos
[IRIS_NOS_COUNT
];
697 unsigned num_viewports
;
698 unsigned sample_mask
;
699 struct iris_blend_state
*cso_blend
;
700 struct iris_rasterizer_state
*cso_rast
;
701 struct iris_depth_stencil_alpha_state
*cso_zsa
;
702 struct iris_vertex_element_state
*cso_vertex_elements
;
703 struct pipe_blend_color blend_color
;
704 struct pipe_poly_stipple poly_stipple
;
705 struct pipe_viewport_state viewports
[IRIS_MAX_VIEWPORTS
];
706 struct pipe_scissor_state scissors
[IRIS_MAX_VIEWPORTS
];
707 struct pipe_stencil_ref stencil_ref
;
708 struct pipe_framebuffer_state framebuffer
;
709 struct pipe_clip_state clip_planes
;
711 float default_outer_level
[4];
712 float default_inner_level
[2];
714 /** Bitfield of which vertex buffers are bound (non-null). */
715 uint64_t bound_vertex_buffers
;
717 bool primitive_restart
;
719 enum pipe_prim_type prim_mode
:8;
720 bool prim_is_points_or_lines
;
721 uint8_t vertices_per_patch
;
723 bool window_space_position
;
725 /** The last compute grid size */
726 uint32_t last_grid
[3];
727 /** Reference to the BO containing the compute grid size */
728 struct iris_state_ref grid_size
;
729 /** Reference to the SURFACE_STATE for the compute grid resource */
730 struct iris_state_ref grid_surf_state
;
733 * Array of aux usages for drawing, altered to account for any
734 * self-dependencies from resources bound for sampling and rendering.
736 enum isl_aux_usage draw_aux_usage
[BRW_MAX_DRAW_BUFFERS
];
738 enum gen_urb_deref_block_size urb_deref_block_size
;
740 /** Bitfield of whether color blending is enabled for RT[i] */
741 uint8_t blend_enables
;
743 /** Are depth writes enabled? (Depth buffer may or may not exist.) */
744 bool depth_writes_enabled
;
746 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */
747 bool stencil_writes_enabled
;
749 /** GenX-specific current state */
750 struct iris_genx_state
*genx
;
752 struct iris_shader_state shaders
[MESA_SHADER_STAGES
];
754 /** Do vertex shader uses shader draw parameters ? */
755 bool vs_uses_draw_params
;
756 bool vs_uses_derived_draw_params
;
757 bool vs_needs_sgvs_element
;
759 /** Do vertex shader uses edge flag ? */
760 bool vs_needs_edge_flag
;
762 /** Do any samplers need border color? One bit per shader stage. */
763 uint8_t need_border_colors
;
765 struct pipe_stream_output_target
*so_target
[PIPE_MAX_SO_BUFFERS
];
766 bool streamout_active
;
768 bool statistics_counters_enabled
;
770 /** Current conditional rendering mode */
771 enum iris_predicate_state predicate
;
774 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
775 * render context that needs to be uploaded to the compute context.
777 struct iris_bo
*compute_predicate
;
779 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
780 bool prims_generated_query_active
;
782 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
785 /** The SURFACE_STATE for a 1x1x1 null surface. */
786 struct iris_state_ref unbound_tex
;
788 /** The SURFACE_STATE for a framebuffer-sized null surface. */
789 struct iris_state_ref null_fb
;
791 struct u_upload_mgr
*surface_uploader
;
792 struct u_upload_mgr
*dynamic_uploader
;
794 struct iris_binder binder
;
796 struct iris_border_color_pool border_color_pool
;
798 /** The high 16-bits of the last VBO/index buffer addresses */
799 uint16_t last_vbo_high_bits
[33];
800 uint16_t last_index_bo_high_bits
;
803 * Resources containing streamed state which our render context
804 * currently points to. Used to re-add these to the validation
805 * list when we start a new batch and haven't resubmitted commands.
808 struct pipe_resource
*cc_vp
;
809 struct pipe_resource
*sf_cl_vp
;
810 struct pipe_resource
*color_calc
;
811 struct pipe_resource
*scissor
;
812 struct pipe_resource
*blend
;
813 struct pipe_resource
*index_buffer
;
814 struct pipe_resource
*cs_thread_ids
;
815 struct pipe_resource
*cs_desc
;
818 /** Records the size of variable-length state for INTEL_DEBUG=bat */
819 struct hash_table_u64
*sizes
;
821 /** Last rendering scale argument provided to genX(emit_hashing_mode). */
822 unsigned current_hash_scale
;
826 #define perf_debug(dbg, ...) do { \
827 if (INTEL_DEBUG & DEBUG_PERF) \
828 dbg_printf(__VA_ARGS__); \
830 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
833 double get_time(void);
835 struct pipe_context
*
836 iris_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
);
838 void iris_lost_context_state(struct iris_batch
*batch
);
840 void iris_init_blit_functions(struct pipe_context
*ctx
);
841 void iris_init_clear_functions(struct pipe_context
*ctx
);
842 void iris_init_program_functions(struct pipe_context
*ctx
);
843 void iris_init_resource_functions(struct pipe_context
*ctx
);
844 void iris_init_perfquery_functions(struct pipe_context
*ctx
);
845 void iris_update_compiled_shaders(struct iris_context
*ice
);
846 void iris_update_compiled_compute_shader(struct iris_context
*ice
);
847 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
852 void iris_blorp_surf_for_resource(struct iris_vtable
*vtbl
,
853 struct isl_device
*isl_dev
,
854 struct blorp_surf
*surf
,
855 struct pipe_resource
*p_res
,
856 enum isl_aux_usage aux_usage
,
858 bool is_render_target
);
859 void iris_copy_region(struct blorp_context
*blorp
,
860 struct iris_batch
*batch
,
861 struct pipe_resource
*dst
,
863 unsigned dstx
, unsigned dsty
, unsigned dstz
,
864 struct pipe_resource
*src
,
866 const struct pipe_box
*src_box
);
870 void iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
871 void iris_launch_grid(struct pipe_context
*, const struct pipe_grid_info
*);
873 /* iris_pipe_control.c */
875 void iris_emit_pipe_control_flush(struct iris_batch
*batch
,
876 const char *reason
, uint32_t flags
);
877 void iris_emit_pipe_control_write(struct iris_batch
*batch
,
878 const char *reason
, uint32_t flags
,
879 struct iris_bo
*bo
, uint32_t offset
,
881 void iris_emit_end_of_pipe_sync(struct iris_batch
*batch
,
882 const char *reason
, uint32_t flags
);
883 void iris_flush_all_caches(struct iris_batch
*batch
);
885 #define iris_handle_always_flush_cache(batch) \
886 if (unlikely(batch->screen->driconf.always_flush_cache)) \
887 iris_flush_all_caches(batch);
889 void iris_init_flush_functions(struct pipe_context
*ctx
);
891 /* iris_border_color.c */
893 void iris_init_border_color_pool(struct iris_context
*ice
);
894 void iris_destroy_border_color_pool(struct iris_context
*ice
);
895 void iris_border_color_pool_reserve(struct iris_context
*ice
, unsigned count
);
896 uint32_t iris_upload_border_color(struct iris_context
*ice
,
897 union pipe_color_union
*color
);
900 void iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
901 struct pipe_shader_buffer
*buf
,
902 struct iris_state_ref
*surf_state
,
904 const struct shader_info
*iris_get_shader_info(const struct iris_context
*ice
,
905 gl_shader_stage stage
);
906 struct iris_bo
*iris_get_scratch_space(struct iris_context
*ice
,
907 unsigned per_thread_scratch
,
908 gl_shader_stage stage
);
909 uint32_t iris_group_index_to_bti(const struct iris_binding_table
*bt
,
910 enum iris_surface_group group
,
912 uint32_t iris_bti_to_group_index(const struct iris_binding_table
*bt
,
913 enum iris_surface_group group
,
916 /* iris_disk_cache.c */
918 void iris_disk_cache_store(struct disk_cache
*cache
,
919 const struct iris_uncompiled_shader
*ish
,
920 const struct iris_compiled_shader
*shader
,
921 const void *prog_key
,
922 uint32_t prog_key_size
);
923 struct iris_compiled_shader
*
924 iris_disk_cache_retrieve(struct iris_context
*ice
,
925 const struct iris_uncompiled_shader
*ish
,
926 const void *prog_key
,
927 uint32_t prog_key_size
);
929 /* iris_program_cache.c */
931 void iris_init_program_cache(struct iris_context
*ice
);
932 void iris_destroy_program_cache(struct iris_context
*ice
);
933 void iris_print_program_cache(struct iris_context
*ice
);
934 struct iris_compiled_shader
*iris_find_cached_shader(struct iris_context
*ice
,
935 enum iris_program_cache_id
,
938 struct iris_compiled_shader
*iris_upload_shader(struct iris_context
*ice
,
939 enum iris_program_cache_id
,
942 const void *assembly
,
943 struct brw_stage_prog_data
*,
945 enum brw_param_builtin
*sysv
,
946 unsigned num_system_values
,
948 const struct iris_binding_table
*bt
);
949 const void *iris_find_previous_compile(const struct iris_context
*ice
,
950 enum iris_program_cache_id cache_id
,
951 unsigned program_string_id
);
952 bool iris_blorp_lookup_shader(struct blorp_batch
*blorp_batch
,
955 uint32_t *kernel_out
,
956 void *prog_data_out
);
957 bool iris_blorp_upload_shader(struct blorp_batch
*blorp_batch
,
958 const void *key
, uint32_t key_size
,
959 const void *kernel
, uint32_t kernel_size
,
960 const struct brw_stage_prog_data
*prog_data
,
961 uint32_t prog_data_size
,
962 uint32_t *kernel_out
,
963 void *prog_data_out
);
967 void iris_predraw_resolve_inputs(struct iris_context
*ice
,
968 struct iris_batch
*batch
,
969 bool *draw_aux_buffer_disabled
,
970 gl_shader_stage stage
,
971 bool consider_framebuffer
);
972 void iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
973 struct iris_batch
*batch
,
974 bool *draw_aux_buffer_disabled
);
975 void iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
976 struct iris_batch
*batch
);
977 void iris_cache_sets_clear(struct iris_batch
*batch
);
978 void iris_flush_depth_and_render_caches(struct iris_batch
*batch
);
979 void iris_cache_flush_for_read(struct iris_batch
*batch
, struct iris_bo
*bo
);
980 void iris_cache_flush_for_render(struct iris_batch
*batch
,
982 enum isl_format format
,
983 enum isl_aux_usage aux_usage
);
984 void iris_render_cache_add_bo(struct iris_batch
*batch
,
986 enum isl_format format
,
987 enum isl_aux_usage aux_usage
);
988 void iris_cache_flush_for_depth(struct iris_batch
*batch
, struct iris_bo
*bo
);
989 void iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
);
990 int iris_get_driver_query_info(struct pipe_screen
*pscreen
, unsigned index
,
991 struct pipe_driver_query_info
*info
);
992 int iris_get_driver_query_group_info(struct pipe_screen
*pscreen
,
994 struct pipe_driver_query_group_info
*info
);
997 void gen9_toggle_preemption(struct iris_context
*ice
,
998 struct iris_batch
*batch
,
999 const struct pipe_draw_info
*draw
);
1002 # include "iris_genx_protos.h"
1004 # define genX(x) gen4_##x
1005 # include "iris_genx_protos.h"
1007 # define genX(x) gen5_##x
1008 # include "iris_genx_protos.h"
1010 # define genX(x) gen6_##x
1011 # include "iris_genx_protos.h"
1013 # define genX(x) gen7_##x
1014 # include "iris_genx_protos.h"
1016 # define genX(x) gen75_##x
1017 # include "iris_genx_protos.h"
1019 # define genX(x) gen8_##x
1020 # include "iris_genx_protos.h"
1022 # define genX(x) gen9_##x
1023 # include "iris_genx_protos.h"
1025 # define genX(x) gen10_##x
1026 # include "iris_genx_protos.h"
1028 # define genX(x) gen11_##x
1029 # include "iris_genx_protos.h"
1031 # define genX(x) gen12_##x
1032 # include "iris_genx_protos.h"