src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/dev/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49 #define IRIS_MAX_CLIP_PLANES 8
  50
  51 enum iris_param_domain {
  52    BRW_PARAM_DOMAIN_BUILTIN = 0,
  53    BRW_PARAM_DOMAIN_IMAGE,
  54 };
  55
  56 enum {
  57    DRI_CONF_BO_REUSE_DISABLED,
  58    DRI_CONF_BO_REUSE_ALL
  59 };
  60
  61 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  62 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  63 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  64 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  65 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  66 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  67
  68 /**
  69  * Dirty flags.  When state changes, we flag some combination of these
  70  * to indicate that particular GPU commands need to be re-emitted.
  71  *
  72  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  73  * in rare cases they map to a group of related packets that need to be
  74  * emitted together.
  75  *
  76  * See iris_upload_render_state().
  77  */
  78 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  79 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  80 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  81 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  82 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  83 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  84 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  85 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  86 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  87 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  88 #define IRIS_DIRTY_SBE                      (1ull << 10)
  89 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  90 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  91 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  92 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  93 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  94 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  95 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  96 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  97 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  98 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  99 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
 100 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
 101 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
 102 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
 103 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
 104 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 105 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 106 #define IRIS_DIRTY_VS                       (1ull << 28)
 107 #define IRIS_DIRTY_TCS                      (1ull << 29)
 108 #define IRIS_DIRTY_TES                      (1ull << 30)
 109 #define IRIS_DIRTY_GS                       (1ull << 31)
 110 #define IRIS_DIRTY_FS                       (1ull << 32)
 111 #define IRIS_DIRTY_CS                       (1ull << 33)
 112 #define IRIS_DIRTY_URB                      (1ull << 34)
 113 #define IRIS_SHIFT_FOR_DIRTY_CONSTANTS      35
 114 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 115 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 116 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 117 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 118 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 119 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 120 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 121 #define IRIS_DIRTY_WM                       (1ull << 42)
 122 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 123 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 124 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 125 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 126 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 127 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 128 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 129 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 130 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 131 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 132 #define IRIS_DIRTY_VF                       (1ull << 53)
 133 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 134 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 135 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 136 #define IRIS_DIRTY_VF_STATISTICS            (1ull << 57)
 137
 138 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 139                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 140                                     IRIS_DIRTY_UNCOMPILED_CS | \
 141                                     IRIS_DIRTY_CONSTANTS_CS | \
 142                                     IRIS_DIRTY_BINDINGS_CS | \
 143                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 144
 145 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 146
 147 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 148                                  IRIS_DIRTY_BINDINGS_TCS | \
 149                                  IRIS_DIRTY_BINDINGS_TES | \
 150                                  IRIS_DIRTY_BINDINGS_GS  | \
 151                                  IRIS_DIRTY_BINDINGS_FS  | \
 152                                  IRIS_DIRTY_BINDINGS_CS)
 153
 154 /**
 155  * Non-orthogonal state (NOS) dependency flags.
 156  *
 157  * Shader programs may depend on non-orthogonal state.  These flags are
 158  * used to indicate that a shader's key depends on the state provided by
 159  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 160  * cause the driver to re-compute the shader key, possibly triggering a
 161  * shader recompile.
 162  */
 163 enum iris_nos_dep {
 164    IRIS_NOS_FRAMEBUFFER,
 165    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 166    IRIS_NOS_RASTERIZER,
 167    IRIS_NOS_BLEND,
 168    IRIS_NOS_LAST_VUE_MAP,
 169
 170    IRIS_NOS_COUNT,
 171 };
 172
 173 struct iris_depth_stencil_alpha_state;
 174
 175 /**
 176  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 177  */
 178 enum iris_program_cache_id {
 179    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 180    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 181    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 182    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 183    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 184    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 185    IRIS_CACHE_BLORP,
 186 };
 187
 188 /** @{
 189  *
 190  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 191  * synchronization, pipelined memory writes, and so on.
 192  *
 193  * The bits here are not the actual hardware values.  The actual fields
 194  * move between various generations, so we just have flags for each
 195  * potential operation, and use genxml to encode the actual packet.
 196  */
 197 enum pipe_control_flags
 198 {
 199    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 200    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 201    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 202    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 203    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 204    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 205    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 206    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 207    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 208    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 209    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 210    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 211    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 212    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 213    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 214    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 215    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 216    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 217    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 218    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 219    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 220    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 221    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 222    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 223 };
 224
 225 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 226    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 227     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 228     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 229
 230 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 231    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 232     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 233     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 234     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 235     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 236
 237 enum iris_predicate_state {
 238    /* The first two states are used if we can determine whether to draw
 239     * without having to look at the values in the query object buffer. This
 240     * will happen if there is no conditional render in progress, if the query
 241     * object is already completed or if something else has already added
 242     * samples to the preliminary result.
 243     */
 244    IRIS_PREDICATE_STATE_RENDER,
 245    IRIS_PREDICATE_STATE_DONT_RENDER,
 246
 247    /* In this case whether to draw or not depends on the result of an
 248     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 249     */
 250    IRIS_PREDICATE_STATE_USE_BIT,
 251 };
 252
 253 /** @} */
 254
 255 /**
 256  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
 257  * It primarily contains the NIR for the shader.
 258  *
 259  * Each API-facing shader can be compiled into multiple shader variants,
 260  * based on non-orthogonal state dependencies, recorded in the shader key.
 261  *
 262  * See iris_compiled_shader, which represents a compiled shader variant.
 263  */
 264 struct iris_uncompiled_shader {
 265    struct nir_shader *nir;
 266
 267    struct pipe_stream_output_info stream_output;
 268
 269    /* A SHA1 of the serialized NIR for the disk cache. */
 270    unsigned char nir_sha1[20];
 271
 272    unsigned program_id;
 273
 274    /** Bitfield of (1 << IRIS_NOS_*) flags. */
 275    unsigned nos;
 276
 277    /** Have any shader variants been compiled yet? */
 278    bool compiled_once;
 279
 280    /** Should we use ALT mode for math?  Useful for ARB programs. */
 281    bool use_alt_mode;
 282
 283    /** Constant data scraped from the shader by nir_opt_large_constants */
 284    struct pipe_resource *const_data;
 285
 286    /** Surface state for const_data */
 287    struct iris_state_ref const_data_state;
 288 };
 289
 290 enum iris_surface_group {
 291    IRIS_SURFACE_GROUP_RENDER_TARGET,
 292    IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
 293    IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
 294    IRIS_SURFACE_GROUP_TEXTURE,
 295    IRIS_SURFACE_GROUP_IMAGE,
 296    IRIS_SURFACE_GROUP_UBO,
 297    IRIS_SURFACE_GROUP_SSBO,
 298
 299    IRIS_SURFACE_GROUP_COUNT,
 300 };
 301
 302 enum {
 303    /* Invalid value for a binding table index. */
 304    IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
 305 };
 306
 307 struct iris_binding_table {
 308    uint32_t size_bytes;
 309
 310    /** Number of surfaces in each group, before compacting. */
 311    uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
 312
 313    /** Initial offset of each group. */
 314    uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
 315
 316    /** Mask of surfaces used in each group. */
 317    uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
 318 };
 319
 320 /**
 321  * A compiled shader variant, containing a pointer to the GPU assembly,
 322  * as well as program data and other packets needed by state upload.
 323  *
 324  * There can be several iris_compiled_shader variants per API-level shader
 325  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 326  */
 327 struct iris_compiled_shader {
 328    /** Reference to the uploaded assembly. */
 329    struct iris_state_ref assembly;
 330
 331    /** Pointer to the assembly in the BO's map. */
 332    void *map;
 333
 334    /** The program data (owned by the program cache hash table) */
 335    struct brw_stage_prog_data *prog_data;
 336
 337    /** A list of system values to be uploaded as uniforms. */
 338    enum brw_param_builtin *system_values;
 339    unsigned num_system_values;
 340
 341    /** Number of constbufs expected by the shader. */
 342    unsigned num_cbufs;
 343
 344    /**
 345     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 346     * (the VUE-based information for transform feedback outputs).
 347     */
 348    uint32_t *streamout;
 349
 350    struct iris_binding_table bt;
 351
 352    /**
 353     * Shader packets and other data derived from prog_data.  These must be
 354     * completely determined from prog_data.
 355     */
 356    uint8_t derived_data[0];
 357 };
 358
 359 /**
 360  * API context state that is replicated per shader stage.
 361  */
 362 struct iris_shader_state {
 363    /** Uniform Buffers */
 364    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 365    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 366
 367    bool sysvals_need_upload;
 368
 369    /** Shader Storage Buffers */
 370    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 371    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 372
 373    /** Shader Storage Images (image load store) */
 374    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 375
 376    struct iris_state_ref sampler_table;
 377    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 378    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 379
 380    /** Bitfield of which constant buffers are bound (non-null). */
 381    uint32_t bound_cbufs;
 382
 383    /** Bitfield of which image views are bound (non-null). */
 384    uint32_t bound_image_views;
 385
 386    /** Bitfield of which sampler views are bound (non-null). */
 387    uint32_t bound_sampler_views;
 388
 389    /** Bitfield of which shader storage buffers are bound (non-null). */
 390    uint32_t bound_ssbos;
 391
 392    /** Bitfield of which shader storage buffers are writable. */
 393    uint32_t writable_ssbos;
 394 };
 395
 396 /**
 397  * Gallium CSO for stream output (transform feedback) targets.
 398  */
 399 struct iris_stream_output_target {
 400    struct pipe_stream_output_target base;
 401
 402    /** Storage holding the offset where we're writing in the buffer */
 403    struct iris_state_ref offset;
 404
 405    /** Stride (bytes-per-vertex) during this transform feedback operation */
 406    uint16_t stride;
 407
 408    /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
 409    bool zeroed;
 410 };
 411
 412 /**
 413  * Virtual table for generation-specific (genxml) function calls.
 414  */
 415 struct iris_vtable {
 416    void (*destroy_state)(struct iris_context *ice);
 417    void (*init_render_context)(struct iris_screen *screen,
 418                                struct iris_batch *batch,
 419                                struct iris_vtable *vtbl,
 420                                struct pipe_debug_callback *dbg);
 421    void (*init_compute_context)(struct iris_screen *screen,
 422                                 struct iris_batch *batch,
 423                                 struct iris_vtable *vtbl,
 424                                 struct pipe_debug_callback *dbg);
 425    void (*upload_render_state)(struct iris_context *ice,
 426                                struct iris_batch *batch,
 427                                const struct pipe_draw_info *draw);
 428    void (*update_surface_base_address)(struct iris_batch *batch,
 429                                        struct iris_binder *binder);
 430    void (*upload_compute_state)(struct iris_context *ice,
 431                                 struct iris_batch *batch,
 432                                 const struct pipe_grid_info *grid);
 433    void (*rebind_buffer)(struct iris_context *ice,
 434                          struct iris_resource *res,
 435                          uint64_t old_address);
 436    void (*resolve_conditional_render)(struct iris_context *ice);
 437    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 438                                uint32_t src);
 439    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 440                                uint32_t src);
 441    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 442                                uint32_t val);
 443    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 444                                uint64_t val);
 445    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 446                                struct iris_bo *bo, uint32_t offset);
 447    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 448                                struct iris_bo *bo, uint32_t offset);
 449    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 450                                 struct iris_bo *bo, uint32_t offset,
 451                                 bool predicated);
 452    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 453                                 struct iris_bo *bo, uint32_t offset,
 454                                 bool predicated);
 455    void (*store_data_imm32)(struct iris_batch *batch,
 456                             struct iris_bo *bo, uint32_t offset,
 457                             uint32_t value);
 458    void (*store_data_imm64)(struct iris_batch *batch,
 459                             struct iris_bo *bo, uint32_t offset,
 460                             uint64_t value);
 461    void (*copy_mem_mem)(struct iris_batch *batch,
 462                         struct iris_bo *dst_bo, uint32_t dst_offset,
 463                         struct iris_bo *src_bo, uint32_t src_offset,
 464                         unsigned bytes);
 465    void (*emit_raw_pipe_control)(struct iris_batch *batch,
 466                                  const char *reason, uint32_t flags,
 467                                  struct iris_bo *bo, uint32_t offset,
 468                                  uint64_t imm);
 469
 470    void (*emit_mi_report_perf_count)(struct iris_batch *batch,
 471                                      struct iris_bo *bo,
 472                                      uint32_t offset_in_bytes,
 473                                      uint32_t report_id);
 474
 475    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 476    void (*store_derived_program_state)(struct iris_context *ice,
 477                                        enum iris_program_cache_id cache_id,
 478                                        struct iris_compiled_shader *shader);
 479    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 480                                     const struct brw_vue_map *vue_map);
 481    void (*populate_vs_key)(const struct iris_context *ice,
 482                            const struct shader_info *info,
 483                            gl_shader_stage last_stage,
 484                            struct brw_vs_prog_key *key);
 485    void (*populate_tcs_key)(const struct iris_context *ice,
 486                             struct brw_tcs_prog_key *key);
 487    void (*populate_tes_key)(const struct iris_context *ice,
 488                             const struct shader_info *info,
 489                             gl_shader_stage last_stage,
 490                             struct brw_tes_prog_key *key);
 491    void (*populate_gs_key)(const struct iris_context *ice,
 492                            const struct shader_info *info,
 493                            gl_shader_stage last_stage,
 494                            struct brw_gs_prog_key *key);
 495    void (*populate_fs_key)(const struct iris_context *ice,
 496                            const struct shader_info *info,
 497                            struct brw_wm_prog_key *key);
 498    void (*populate_cs_key)(const struct iris_context *ice,
 499                            struct brw_cs_prog_key *key);
 500    uint32_t (*mocs)(const struct iris_bo *bo);
 501    void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
 502 };
 503
 504 /**
 505  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 506  *
 507  * See iris_border_color.c for more information.
 508  */
 509 struct iris_border_color_pool {
 510    struct iris_bo *bo;
 511    void *map;
 512    unsigned insert_point;
 513
 514    /** Map from border colors to offsets in the buffer. */
 515    struct hash_table *ht;
 516 };
 517
 518 /**
 519  * The API context (derived from pipe_context).
 520  *
 521  * Most driver state is tracked here.
 522  */
 523 struct iris_context {
 524    struct pipe_context ctx;
 525
 526    /** A debug callback for KHR_debug output. */
 527    struct pipe_debug_callback dbg;
 528
 529    /** A device reset status callback for notifying that the GPU is hosed. */
 530    struct pipe_device_reset_callback reset;
 531
 532    /** Slab allocator for iris_transfer_map objects. */
 533    struct slab_child_pool transfer_pool;
 534
 535    struct iris_vtable vtbl;
 536
 537    struct blorp_context blorp;
 538
 539    struct iris_batch batches[IRIS_BATCH_COUNT];
 540
 541    struct u_upload_mgr *query_buffer_uploader;
 542
 543    struct {
 544       struct {
 545          /**
 546           * Either the value of BaseVertex for indexed draw calls or the value
 547           * of the argument <first> for non-indexed draw calls.
 548           */
 549          int firstvertex;
 550          int baseinstance;
 551       } params;
 552
 553       /**
 554        * Resource and offset that stores draw_parameters from the indirect
 555        * buffer or to the buffer that stures the previous values for non
 556        * indirect draws.
 557        */
 558       struct pipe_resource *draw_params_res;
 559       uint32_t draw_params_offset;
 560
 561       struct {
 562          /**
 563           * The value of DrawID. This always comes in from it's own vertex
 564           * buffer since it's not part of the indirect draw parameters.
 565           */
 566          int drawid;
 567
 568          /**
 569           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 570           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 571           */
 572          int is_indexed_draw;
 573       } derived_params;
 574
 575       /**
 576        * Resource and offset used for GL_ARB_shader_draw_parameters which
 577        * contains parameters that are not present in the indirect buffer as
 578        * drawid and is_indexed_draw. They will go in their own vertex element.
 579        */
 580       struct pipe_resource *derived_draw_params_res;
 581       uint32_t derived_draw_params_offset;
 582
 583       bool is_indirect;
 584    } draw;
 585
 586    struct {
 587       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 588       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 589       struct brw_vue_map *last_vue_map;
 590
 591       struct u_upload_mgr *uploader;
 592       struct hash_table *cache;
 593
 594       unsigned urb_size;
 595
 596       /** Is a GS or TES outputting points or lines? */
 597       bool output_topology_is_points_or_lines;
 598
 599       /* Track last VS URB entry size */
 600       unsigned last_vs_entry_size;
 601
 602       /**
 603        * Scratch buffers for various sizes and stages.
 604        *
 605        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 606        * and shader stage.
 607        */
 608       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 609    } shaders;
 610
 611    struct {
 612       struct iris_query *query;
 613       bool condition;
 614    } condition;
 615
 616    struct gen_perf_context *perf_ctx;
 617
 618    struct {
 619       uint64_t dirty;
 620       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 621
 622       unsigned num_viewports;
 623       unsigned sample_mask;
 624       struct iris_blend_state *cso_blend;
 625       struct iris_rasterizer_state *cso_rast;
 626       struct iris_depth_stencil_alpha_state *cso_zsa;
 627       struct iris_vertex_element_state *cso_vertex_elements;
 628       struct pipe_blend_color blend_color;
 629       struct pipe_poly_stipple poly_stipple;
 630       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 631       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 632       struct pipe_stencil_ref stencil_ref;
 633       struct pipe_framebuffer_state framebuffer;
 634       struct pipe_clip_state clip_planes;
 635
 636       float default_outer_level[4];
 637       float default_inner_level[2];
 638
 639       /** Bitfield of which vertex buffers are bound (non-null). */
 640       uint64_t bound_vertex_buffers;
 641
 642       bool primitive_restart;
 643       unsigned cut_index;
 644       enum pipe_prim_type prim_mode:8;
 645       bool prim_is_points_or_lines;
 646       uint8_t vertices_per_patch;
 647
 648       bool window_space_position;
 649
 650       /** The last compute grid size */
 651       uint32_t last_grid[3];
 652       /** Reference to the BO containing the compute grid size */
 653       struct iris_state_ref grid_size;
 654       /** Reference to the SURFACE_STATE for the compute grid resource */
 655       struct iris_state_ref grid_surf_state;
 656
 657       /**
 658        * Array of aux usages for drawing, altered to account for any
 659        * self-dependencies from resources bound for sampling and rendering.
 660        */
 661       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 662
 663       /** Bitfield of whether color blending is enabled for RT[i] */
 664       uint8_t blend_enables;
 665
 666       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 667       bool depth_writes_enabled;
 668
 669       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 670       bool stencil_writes_enabled;
 671
 672       /** GenX-specific current state */
 673       struct iris_genx_state *genx;
 674
 675       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 676
 677       /** Do vertex shader uses shader draw parameters ? */
 678       bool vs_uses_draw_params;
 679       bool vs_uses_derived_draw_params;
 680       bool vs_needs_sgvs_element;
 681
 682       /** Do vertex shader uses edge flag ? */
 683       bool vs_needs_edge_flag;
 684
 685       /** Do any samplers need border color?  One bit per shader stage. */
 686       uint8_t need_border_colors;
 687
 688       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 689       bool streamout_active;
 690
 691       bool statistics_counters_enabled;
 692
 693       /** Current conditional rendering mode */
 694       enum iris_predicate_state predicate;
 695
 696       /**
 697        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 698        * render context that needs to be uploaded to the compute context.
 699        */
 700       struct iris_bo *compute_predicate;
 701
 702       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 703       bool prims_generated_query_active;
 704
 705       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 706       uint32_t *streamout;
 707
 708       /** The SURFACE_STATE for a 1x1x1 null surface. */
 709       struct iris_state_ref unbound_tex;
 710
 711       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 712       struct iris_state_ref null_fb;
 713
 714       struct u_upload_mgr *surface_uploader;
 715       struct u_upload_mgr *dynamic_uploader;
 716
 717       struct iris_binder binder;
 718
 719       struct iris_border_color_pool border_color_pool;
 720
 721       /** The high 16-bits of the last VBO/index buffer addresses */
 722       uint16_t last_vbo_high_bits[33];
 723       uint16_t last_index_bo_high_bits;
 724
 725       /**
 726        * Resources containing streamed state which our render context
 727        * currently points to.  Used to re-add these to the validation
 728        * list when we start a new batch and haven't resubmitted commands.
 729        */
 730       struct {
 731          struct pipe_resource *cc_vp;
 732          struct pipe_resource *sf_cl_vp;
 733          struct pipe_resource *color_calc;
 734          struct pipe_resource *scissor;
 735          struct pipe_resource *blend;
 736          struct pipe_resource *index_buffer;
 737          struct pipe_resource *cs_thread_ids;
 738          struct pipe_resource *cs_desc;
 739       } last_res;
 740
 741       /** Records the size of variable-length state for INTEL_DEBUG=bat */
 742       struct hash_table_u64 *sizes;
 743
 744       /** Last rendering scale argument provided to genX(emit_hashing_mode). */
 745       unsigned current_hash_scale;
 746    } state;
 747 };
 748
 749 #define perf_debug(dbg, ...) do {                      \
 750    if (INTEL_DEBUG & DEBUG_PERF)                       \
 751       dbg_printf(__VA_ARGS__);                         \
 752    if (unlikely(dbg))                                  \
 753       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 754 } while(0)
 755
 756 double get_time(void);
 757
 758 struct pipe_context *
 759 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 760
 761 void iris_lost_context_state(struct iris_batch *batch);
 762
 763 void iris_init_blit_functions(struct pipe_context *ctx);
 764 void iris_init_clear_functions(struct pipe_context *ctx);
 765 void iris_init_program_functions(struct pipe_context *ctx);
 766 void iris_init_resource_functions(struct pipe_context *ctx);
 767 void iris_update_compiled_shaders(struct iris_context *ice);
 768 void iris_update_compiled_compute_shader(struct iris_context *ice);
 769 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 770                                     uint32_t *dst);
 771
 772
 773 /* iris_blit.c */
 774 void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
 775                                   struct blorp_surf *surf,
 776                                   struct pipe_resource *p_res,
 777                                   enum isl_aux_usage aux_usage,
 778                                   unsigned level,
 779                                   bool is_render_target);
 780 void iris_copy_region(struct blorp_context *blorp,
 781                       struct iris_batch *batch,
 782                       struct pipe_resource *dst,
 783                       unsigned dst_level,
 784                       unsigned dstx, unsigned dsty, unsigned dstz,
 785                       struct pipe_resource *src,
 786                       unsigned src_level,
 787                       const struct pipe_box *src_box);
 788
 789 /* iris_draw.c */
 790
 791 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 792 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 793
 794 /* iris_pipe_control.c */
 795
 796 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 797                                   const char *reason, uint32_t flags);
 798 void iris_emit_pipe_control_write(struct iris_batch *batch,
 799                                   const char *reason, uint32_t flags,
 800                                   struct iris_bo *bo, uint32_t offset,
 801                                   uint64_t imm);
 802 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 803                                 const char *reason, uint32_t flags);
 804 void iris_flush_all_caches(struct iris_batch *batch);
 805
 806 #define iris_handle_always_flush_cache(batch) \
 807    if (unlikely(batch->screen->driconf.always_flush_cache)) \
 808       iris_flush_all_caches(batch);
 809
 810 void iris_init_flush_functions(struct pipe_context *ctx);
 811
 812 /* iris_border_color.c */
 813
 814 void iris_init_border_color_pool(struct iris_context *ice);
 815 void iris_destroy_border_color_pool(struct iris_context *ice);
 816 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 817 uint32_t iris_upload_border_color(struct iris_context *ice,
 818                                   union pipe_color_union *color);
 819
 820 /* iris_program.c */
 821 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
 822                                      struct pipe_shader_buffer *buf,
 823                                      struct iris_state_ref *surf_state,
 824                                      bool ssbo);
 825 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 826                                                gl_shader_stage stage);
 827 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 828                                        unsigned per_thread_scratch,
 829                                        gl_shader_stage stage);
 830 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
 831                                  enum iris_surface_group group,
 832                                  uint32_t index);
 833 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
 834                                  enum iris_surface_group group,
 835                                  uint32_t bti);
 836
 837 /* iris_disk_cache.c */
 838
 839 void iris_disk_cache_store(struct disk_cache *cache,
 840                            const struct iris_uncompiled_shader *ish,
 841                            const struct iris_compiled_shader *shader,
 842                            const void *prog_key,
 843                            uint32_t prog_key_size);
 844 struct iris_compiled_shader *
 845 iris_disk_cache_retrieve(struct iris_context *ice,
 846                          const struct iris_uncompiled_shader *ish,
 847                          const void *prog_key,
 848                          uint32_t prog_key_size);
 849
 850 /* iris_program_cache.c */
 851
 852 void iris_init_program_cache(struct iris_context *ice);
 853 void iris_destroy_program_cache(struct iris_context *ice);
 854 void iris_print_program_cache(struct iris_context *ice);
 855 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 856                                                      enum iris_program_cache_id,
 857                                                      uint32_t key_size,
 858                                                      const void *key);
 859 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 860                                                 enum iris_program_cache_id,
 861                                                 uint32_t key_size,
 862                                                 const void *key,
 863                                                 const void *assembly,
 864                                                 struct brw_stage_prog_data *,
 865                                                 uint32_t *streamout,
 866                                                 enum brw_param_builtin *sysv,
 867                                                 unsigned num_system_values,
 868                                                 unsigned num_cbufs,
 869                                                 const struct iris_binding_table *bt);
 870 const void *iris_find_previous_compile(const struct iris_context *ice,
 871                                        enum iris_program_cache_id cache_id,
 872                                        unsigned program_string_id);
 873 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 874                               const void *key,
 875                               uint32_t key_size,
 876                               uint32_t *kernel_out,
 877                               void *prog_data_out);
 878 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 879                               const void *key, uint32_t key_size,
 880                               const void *kernel, uint32_t kernel_size,
 881                               const struct brw_stage_prog_data *prog_data,
 882                               uint32_t prog_data_size,
 883                               uint32_t *kernel_out,
 884                               void *prog_data_out);
 885
 886 /* iris_resolve.c */
 887
 888 void iris_predraw_resolve_inputs(struct iris_context *ice,
 889                                  struct iris_batch *batch,
 890                                  bool *draw_aux_buffer_disabled,
 891                                  gl_shader_stage stage,
 892                                  bool consider_framebuffer);
 893 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 894                                       struct iris_batch *batch,
 895                                       bool *draw_aux_buffer_disabled);
 896 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 897                                            struct iris_batch *batch);
 898 void iris_cache_sets_clear(struct iris_batch *batch);
 899 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 900 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 901 void iris_cache_flush_for_render(struct iris_batch *batch,
 902                                  struct iris_bo *bo,
 903                                  enum isl_format format,
 904                                  enum isl_aux_usage aux_usage);
 905 void iris_render_cache_add_bo(struct iris_batch *batch,
 906                               struct iris_bo *bo,
 907                               enum isl_format format,
 908                               enum isl_aux_usage aux_usage);
 909 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 910 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 911 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
 912                                struct pipe_driver_query_info *info);
 913 int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
 914                                      unsigned index,
 915                                      struct pipe_driver_query_group_info *info);
 916
 917 /* iris_state.c */
 918 void gen9_toggle_preemption(struct iris_context *ice,
 919                             struct iris_batch *batch,
 920                             const struct pipe_draw_info *draw);
 921
 922 #ifdef genX
 923 #  include "iris_genx_protos.h"
 924 #else
 925 #  define genX(x) gen4_##x
 926 #  include "iris_genx_protos.h"
 927 #  undef genX
 928 #  define genX(x) gen5_##x
 929 #  include "iris_genx_protos.h"
 930 #  undef genX
 931 #  define genX(x) gen6_##x
 932 #  include "iris_genx_protos.h"
 933 #  undef genX
 934 #  define genX(x) gen7_##x
 935 #  include "iris_genx_protos.h"
 936 #  undef genX
 937 #  define genX(x) gen75_##x
 938 #  include "iris_genx_protos.h"
 939 #  undef genX
 940 #  define genX(x) gen8_##x
 941 #  include "iris_genx_protos.h"
 942 #  undef genX
 943 #  define genX(x) gen9_##x
 944 #  include "iris_genx_protos.h"
 945 #  undef genX
 946 #  define genX(x) gen10_##x
 947 #  include "iris_genx_protos.h"
 948 #  undef genX
 949 #  define genX(x) gen11_##x
 950 #  include "iris_genx_protos.h"
 951 #  undef genX
 952 #  define genX(x) gen12_##x
 953 #  include "iris_genx_protos.h"
 954 #  undef genX
 955 #endif
 956
 957 #endif