src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/dev/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49 #define IRIS_MAX_CLIP_PLANES 8
  50
  51 enum iris_param_domain {
  52    BRW_PARAM_DOMAIN_BUILTIN = 0,
  53    BRW_PARAM_DOMAIN_IMAGE,
  54 };
  55
  56 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  57 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  58 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  59 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  60 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  61 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  62
  63 /**
  64  * Dirty flags.  When state changes, we flag some combination of these
  65  * to indicate that particular GPU commands need to be re-emitted.
  66  *
  67  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  68  * in rare cases they map to a group of related packets that need to be
  69  * emitted together.
  70  *
  71  * See iris_upload_render_state().
  72  */
  73 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  74 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  75 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  76 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  77 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  78 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  79 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  80 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  81 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  82 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  83 #define IRIS_DIRTY_SBE                      (1ull << 10)
  84 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  85 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  86 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  87 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  88 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  89 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  90 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  91 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  92 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  93 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  94 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  95 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  96 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  97 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  98 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  99 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 100 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 101 #define IRIS_DIRTY_VS                       (1ull << 28)
 102 #define IRIS_DIRTY_TCS                      (1ull << 29)
 103 #define IRIS_DIRTY_TES                      (1ull << 30)
 104 #define IRIS_DIRTY_GS                       (1ull << 31)
 105 #define IRIS_DIRTY_FS                       (1ull << 32)
 106 #define IRIS_DIRTY_CS                       (1ull << 33)
 107 #define IRIS_DIRTY_URB                      (1ull << 34)
 108 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 109 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 110 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 111 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 112 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 113 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 114 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 115 #define IRIS_DIRTY_WM                       (1ull << 42)
 116 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 117 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 118 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 119 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 120 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 121 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 122 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 123 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 124 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 125 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 126 #define IRIS_DIRTY_VF                       (1ull << 53)
 127 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 128 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 129 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 130 #define IRIS_DIRTY_VF_STATISTICS            (1ull << 57)
 131
 132 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 133                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 134                                     IRIS_DIRTY_UNCOMPILED_CS | \
 135                                     IRIS_DIRTY_CONSTANTS_CS | \
 136                                     IRIS_DIRTY_BINDINGS_CS | \
 137                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 138
 139 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 140
 141 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 142                                  IRIS_DIRTY_BINDINGS_TCS | \
 143                                  IRIS_DIRTY_BINDINGS_TES | \
 144                                  IRIS_DIRTY_BINDINGS_GS  | \
 145                                  IRIS_DIRTY_BINDINGS_FS  | \
 146                                  IRIS_DIRTY_BINDINGS_CS)
 147
 148 /**
 149  * Non-orthogonal state (NOS) dependency flags.
 150  *
 151  * Shader programs may depend on non-orthogonal state.  These flags are
 152  * used to indicate that a shader's key depends on the state provided by
 153  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 154  * cause the driver to re-compute the shader key, possibly triggering a
 155  * shader recompile.
 156  */
 157 enum iris_nos_dep {
 158    IRIS_NOS_FRAMEBUFFER,
 159    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 160    IRIS_NOS_RASTERIZER,
 161    IRIS_NOS_BLEND,
 162    IRIS_NOS_LAST_VUE_MAP,
 163
 164    IRIS_NOS_COUNT,
 165 };
 166
 167 struct iris_depth_stencil_alpha_state;
 168
 169 /**
 170  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 171  */
 172 enum iris_program_cache_id {
 173    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 174    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 175    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 176    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 177    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 178    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 179    IRIS_CACHE_BLORP,
 180 };
 181
 182 /** @{
 183  *
 184  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 185  * synchronization, pipelined memory writes, and so on.
 186  *
 187  * The bits here are not the actual hardware values.  The actual fields
 188  * move between various generations, so we just have flags for each
 189  * potential operation, and use genxml to encode the actual packet.
 190  */
 191 enum pipe_control_flags
 192 {
 193    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 194    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 195    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 196    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 197    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 198    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 199    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 200    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 201    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 202    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 203    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 204    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 205    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 206    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 207    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 208    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 209    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 210    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 211    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 212    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 213    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 214    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 215    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 216    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 217 };
 218
 219 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 220    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 221     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 222     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 223
 224 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 225    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 226     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 227     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 228     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 229     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 230
 231 enum iris_predicate_state {
 232    /* The first two states are used if we can determine whether to draw
 233     * without having to look at the values in the query object buffer. This
 234     * will happen if there is no conditional render in progress, if the query
 235     * object is already completed or if something else has already added
 236     * samples to the preliminary result.
 237     */
 238    IRIS_PREDICATE_STATE_RENDER,
 239    IRIS_PREDICATE_STATE_DONT_RENDER,
 240
 241    /* In this case whether to draw or not depends on the result of an
 242     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 243     */
 244    IRIS_PREDICATE_STATE_USE_BIT,
 245 };
 246
 247 /** @} */
 248
 249 /**
 250  * A compiled shader variant, containing a pointer to the GPU assembly,
 251  * as well as program data and other packets needed by state upload.
 252  *
 253  * There can be several iris_compiled_shader variants per API-level shader
 254  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 255  */
 256 struct iris_compiled_shader {
 257    /** Reference to the uploaded assembly. */
 258    struct iris_state_ref assembly;
 259
 260    /** Pointer to the assembly in the BO's map. */
 261    void *map;
 262
 263    /** The program data (owned by the program cache hash table) */
 264    struct brw_stage_prog_data *prog_data;
 265
 266    /** A list of system values to be uploaded as uniforms. */
 267    enum brw_param_builtin *system_values;
 268    unsigned num_system_values;
 269
 270    /** Number of constbufs expected by the shader. */
 271    unsigned num_cbufs;
 272
 273    /**
 274     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 275     * (the VUE-based information for transform feedback outputs).
 276     */
 277    uint32_t *streamout;
 278
 279    /**
 280     * Shader packets and other data derived from prog_data.  These must be
 281     * completely determined from prog_data.
 282     */
 283    uint8_t derived_data[0];
 284 };
 285
 286 /**
 287  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 288  */
 289 struct iris_const_buffer {
 290    /** The resource and offset for the actual constant data */
 291    struct iris_state_ref data;
 292
 293    /** The resource and offset for the SURFACE_STATE for pull access. */
 294    struct iris_state_ref surface_state;
 295 };
 296
 297 /**
 298  * API context state that is replicated per shader stage.
 299  */
 300 struct iris_shader_state {
 301    /** Uniform Buffers */
 302    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 303
 304    struct pipe_constant_buffer cbuf0;
 305    bool cbuf0_needs_upload;
 306
 307    /** Shader Storage Buffers */
 308    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 309    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 310
 311    /** Shader Storage Images (image load store) */
 312    struct {
 313       struct pipe_resource *res;
 314       struct iris_state_ref surface_state;
 315       unsigned access;
 316
 317       /** Gen8-only uniform data for image lowering */
 318       struct brw_image_param param;
 319    } image[PIPE_MAX_SHADER_IMAGES];
 320
 321    struct iris_state_ref sampler_table;
 322    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 323    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 324
 325    /** Bitfield of which constant buffers are bound (non-null). */
 326    uint32_t bound_cbufs;
 327
 328    /** Bitfield of which image views are bound (non-null). */
 329    uint32_t bound_image_views;
 330
 331    /** Bitfield of which sampler views are bound (non-null). */
 332    uint32_t bound_sampler_views;
 333
 334    /** Bitfield of which shader storage buffers are bound (non-null). */
 335    uint32_t bound_ssbos;
 336
 337    /** Bitfield of which shader storage buffers are writable. */
 338    uint32_t writable_ssbos;
 339 };
 340
 341 /**
 342  * Gallium CSO for stream output (transform feedback) targets.
 343  */
 344 struct iris_stream_output_target {
 345    struct pipe_stream_output_target base;
 346
 347    /** Storage holding the offset where we're writing in the buffer */
 348    struct iris_state_ref offset;
 349
 350    /** Stride (dwords-per-vertex) during this transform feedback operation */
 351    uint16_t stride;
 352 };
 353
 354 /**
 355  * Virtual table for generation-specific (genxml) function calls.
 356  */
 357 struct iris_vtable {
 358    void (*destroy_state)(struct iris_context *ice);
 359    void (*init_render_context)(struct iris_screen *screen,
 360                                struct iris_batch *batch,
 361                                struct iris_vtable *vtbl,
 362                                struct pipe_debug_callback *dbg);
 363    void (*init_compute_context)(struct iris_screen *screen,
 364                                 struct iris_batch *batch,
 365                                 struct iris_vtable *vtbl,
 366                                 struct pipe_debug_callback *dbg);
 367    void (*upload_render_state)(struct iris_context *ice,
 368                                struct iris_batch *batch,
 369                                const struct pipe_draw_info *draw);
 370    void (*update_surface_base_address)(struct iris_batch *batch,
 371                                        struct iris_binder *binder);
 372    void (*upload_compute_state)(struct iris_context *ice,
 373                                 struct iris_batch *batch,
 374                                 const struct pipe_grid_info *grid);
 375    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 376                                uint32_t src);
 377    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 378                                uint32_t src);
 379    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 380                                uint32_t val);
 381    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 382                                uint64_t val);
 383    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 384                                struct iris_bo *bo, uint32_t offset);
 385    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 386                                struct iris_bo *bo, uint32_t offset);
 387    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 388                                 struct iris_bo *bo, uint32_t offset,
 389                                 bool predicated);
 390    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 391                                 struct iris_bo *bo, uint32_t offset,
 392                                 bool predicated);
 393    void (*store_data_imm32)(struct iris_batch *batch,
 394                             struct iris_bo *bo, uint32_t offset,
 395                             uint32_t value);
 396    void (*store_data_imm64)(struct iris_batch *batch,
 397                             struct iris_bo *bo, uint32_t offset,
 398                             uint64_t value);
 399    void (*copy_mem_mem)(struct iris_batch *batch,
 400                         struct iris_bo *dst_bo, uint32_t dst_offset,
 401                         struct iris_bo *src_bo, uint32_t src_offset,
 402                         unsigned bytes);
 403    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 404                                  struct iris_bo *bo, uint32_t offset,
 405                                  uint64_t imm);
 406
 407    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 408    void (*store_derived_program_state)(struct iris_context *ice,
 409                                        enum iris_program_cache_id cache_id,
 410                                        struct iris_compiled_shader *shader);
 411    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 412                                     const struct brw_vue_map *vue_map);
 413    void (*populate_vs_key)(const struct iris_context *ice,
 414                            const struct shader_info *info,
 415                            struct brw_vs_prog_key *key);
 416    void (*populate_tcs_key)(const struct iris_context *ice,
 417                             struct brw_tcs_prog_key *key);
 418    void (*populate_tes_key)(const struct iris_context *ice,
 419                             struct brw_tes_prog_key *key);
 420    void (*populate_gs_key)(const struct iris_context *ice,
 421                            struct brw_gs_prog_key *key);
 422    void (*populate_fs_key)(const struct iris_context *ice,
 423                            struct brw_wm_prog_key *key);
 424    void (*populate_cs_key)(const struct iris_context *ice,
 425                            struct brw_cs_prog_key *key);
 426    uint32_t (*mocs)(const struct iris_bo *bo);
 427 };
 428
 429 /**
 430  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 431  *
 432  * See iris_border_color.c for more information.
 433  */
 434 struct iris_border_color_pool {
 435    struct iris_bo *bo;
 436    void *map;
 437    unsigned insert_point;
 438
 439    /** Map from border colors to offsets in the buffer. */
 440    struct hash_table *ht;
 441 };
 442
 443 /**
 444  * The API context (derived from pipe_context).
 445  *
 446  * Most driver state is tracked here.
 447  */
 448 struct iris_context {
 449    struct pipe_context ctx;
 450
 451    /** A debug callback for KHR_debug output. */
 452    struct pipe_debug_callback dbg;
 453
 454    /** Slab allocator for iris_transfer_map objects. */
 455    struct slab_child_pool transfer_pool;
 456
 457    struct iris_vtable vtbl;
 458
 459    struct blorp_context blorp;
 460
 461    struct iris_batch batches[IRIS_BATCH_COUNT];
 462
 463    struct u_upload_mgr *query_buffer_uploader;
 464
 465    struct {
 466       struct {
 467          /**
 468           * Either the value of BaseVertex for indexed draw calls or the value
 469           * of the argument <first> for non-indexed draw calls.
 470           */
 471          int firstvertex;
 472          int baseinstance;
 473       } params;
 474
 475       /**
 476        * Resource and offset that stores draw_parameters from the indirect
 477        * buffer or to the buffer that stures the previous values for non
 478        * indirect draws.
 479        */
 480       struct pipe_resource *draw_params_res;
 481       uint32_t draw_params_offset;
 482
 483       struct {
 484          /**
 485           * The value of DrawID. This always comes in from it's own vertex
 486           * buffer since it's not part of the indirect draw parameters.
 487           */
 488          int drawid;
 489
 490          /**
 491           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 492           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 493           */
 494          int is_indexed_draw;
 495       } derived_params;
 496
 497       /**
 498        * Resource and offset used for GL_ARB_shader_draw_parameters which
 499        * contains parameters that are not present in the indirect buffer as
 500        * drawid and is_indexed_draw. They will go in their own vertex element.
 501        */
 502       struct pipe_resource *derived_draw_params_res;
 503       uint32_t derived_draw_params_offset;
 504
 505       bool is_indirect;
 506    } draw;
 507
 508    struct {
 509       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 510       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 511       struct brw_vue_map *last_vue_map;
 512
 513       struct u_upload_mgr *uploader;
 514       struct hash_table *cache;
 515
 516       unsigned urb_size;
 517
 518       /* Track last VS URB entry size */
 519       unsigned last_vs_entry_size;
 520
 521       /**
 522        * Scratch buffers for various sizes and stages.
 523        *
 524        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 525        * and shader stage.
 526        */
 527       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 528    } shaders;
 529
 530    struct {
 531       struct iris_query *query;
 532       bool condition;
 533    } condition;
 534
 535    struct {
 536       uint64_t dirty;
 537       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 538
 539       unsigned num_viewports;
 540       unsigned sample_mask;
 541       struct iris_blend_state *cso_blend;
 542       struct iris_rasterizer_state *cso_rast;
 543       struct iris_depth_stencil_alpha_state *cso_zsa;
 544       struct iris_vertex_element_state *cso_vertex_elements;
 545       struct pipe_blend_color blend_color;
 546       struct pipe_poly_stipple poly_stipple;
 547       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 548       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 549       struct pipe_stencil_ref stencil_ref;
 550       struct pipe_framebuffer_state framebuffer;
 551       struct pipe_clip_state clip_planes;
 552
 553       float default_outer_level[4];
 554       float default_inner_level[2];
 555
 556       /** Bitfield of which vertex buffers are bound (non-null). */
 557       uint64_t bound_vertex_buffers;
 558
 559       bool primitive_restart;
 560       unsigned cut_index;
 561       enum pipe_prim_type prim_mode:8;
 562       uint8_t vertices_per_patch;
 563
 564       /** The last compute grid size */
 565       uint32_t last_grid[3];
 566       /** Reference to the BO containing the compute grid size */
 567       struct iris_state_ref grid_size;
 568       /** Reference to the SURFACE_STATE for the compute grid resource */
 569       struct iris_state_ref grid_surf_state;
 570
 571       /**
 572        * Array of aux usages for drawing, altered to account for any
 573        * self-dependencies from resources bound for sampling and rendering.
 574        */
 575       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 576
 577       /** Bitfield of whether color blending is enabled for RT[i] */
 578       uint8_t blend_enables;
 579
 580       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 581       bool depth_writes_enabled;
 582
 583       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 584       bool stencil_writes_enabled;
 585
 586       /** GenX-specific current state */
 587       struct iris_genx_state *genx;
 588
 589       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 590
 591       /** Do vertex shader uses shader draw parameters ? */
 592       bool vs_uses_draw_params;
 593       bool vs_uses_derived_draw_params;
 594       bool vs_needs_sgvs_element;
 595
 596       /** Do vertex shader uses edge flag ? */
 597       bool vs_needs_edge_flag;
 598
 599       /** Do any samplers need border color?  One bit per shader stage. */
 600       uint8_t need_border_colors;
 601
 602       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 603       bool streamout_active;
 604
 605       bool statistics_counters_enabled;
 606
 607       /** Current conditional rendering mode */
 608       enum iris_predicate_state predicate;
 609
 610       /**
 611        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 612        * render context that needs to be uploaded to the compute context.
 613        */
 614       struct iris_bo *compute_predicate;
 615
 616       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 617       bool prims_generated_query_active;
 618
 619       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 620       uint32_t *streamout;
 621
 622       /** Current strides for each streamout buffer */
 623       uint16_t *streamout_strides;
 624
 625       /** The SURFACE_STATE for a 1x1x1 null surface. */
 626       struct iris_state_ref unbound_tex;
 627
 628       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 629       struct iris_state_ref null_fb;
 630
 631       struct u_upload_mgr *surface_uploader;
 632       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 633       // "I'm streaming this out at draw time and never want it again!"
 634       struct u_upload_mgr *dynamic_uploader;
 635
 636       struct iris_binder binder;
 637
 638       struct iris_border_color_pool border_color_pool;
 639
 640       /** The high 16-bits of the last VBO/index buffer addresses */
 641       uint16_t last_vbo_high_bits[33];
 642       uint16_t last_index_bo_high_bits;
 643
 644       /**
 645        * Resources containing streamed state which our render context
 646        * currently points to.  Used to re-add these to the validation
 647        * list when we start a new batch and haven't resubmitted commands.
 648        */
 649       struct {
 650          struct pipe_resource *cc_vp;
 651          struct pipe_resource *sf_cl_vp;
 652          struct pipe_resource *color_calc;
 653          struct pipe_resource *scissor;
 654          struct pipe_resource *blend;
 655          struct pipe_resource *index_buffer;
 656       } last_res;
 657    } state;
 658 };
 659
 660 #define perf_debug(dbg, ...) do {                      \
 661    if (INTEL_DEBUG & DEBUG_PERF)                       \
 662       dbg_printf(__VA_ARGS__);                         \
 663    if (unlikely(dbg))                                  \
 664       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 665 } while(0)
 666
 667 double get_time(void);
 668
 669 struct pipe_context *
 670 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 671
 672 void iris_init_blit_functions(struct pipe_context *ctx);
 673 void iris_init_clear_functions(struct pipe_context *ctx);
 674 void iris_init_program_functions(struct pipe_context *ctx);
 675 void iris_init_resource_functions(struct pipe_context *ctx);
 676 void iris_init_query_functions(struct pipe_context *ctx);
 677 void iris_update_compiled_shaders(struct iris_context *ice);
 678 void iris_update_compiled_compute_shader(struct iris_context *ice);
 679 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 680                                     uint32_t *dst);
 681
 682
 683 /* iris_blit.c */
 684 void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
 685                                   struct blorp_surf *surf,
 686                                   struct pipe_resource *p_res,
 687                                   enum isl_aux_usage aux_usage,
 688                                   unsigned level,
 689                                   bool is_render_target);
 690 void iris_copy_region(struct blorp_context *blorp,
 691                       struct iris_batch *batch,
 692                       struct pipe_resource *dst,
 693                       unsigned dst_level,
 694                       unsigned dstx, unsigned dsty, unsigned dstz,
 695                       struct pipe_resource *src,
 696                       unsigned src_level,
 697                       const struct pipe_box *src_box);
 698
 699 /* iris_draw.c */
 700
 701 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 702 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 703
 704 /* iris_pipe_control.c */
 705
 706 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 707                                   uint32_t flags);
 708 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 709                                   struct iris_bo *bo, uint32_t offset,
 710                                   uint64_t imm);
 711 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 712                                 uint32_t flags);
 713
 714 void iris_init_flush_functions(struct pipe_context *ctx);
 715
 716 /* iris_blorp.c */
 717 void gen8_init_blorp(struct iris_context *ice);
 718 void gen9_init_blorp(struct iris_context *ice);
 719 void gen10_init_blorp(struct iris_context *ice);
 720 void gen11_init_blorp(struct iris_context *ice);
 721
 722 /* iris_border_color.c */
 723
 724 void iris_init_border_color_pool(struct iris_context *ice);
 725 void iris_destroy_border_color_pool(struct iris_context *ice);
 726 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 727 uint32_t iris_upload_border_color(struct iris_context *ice,
 728                                   union pipe_color_union *color);
 729
 730 /* iris_state.c */
 731 void gen8_init_state(struct iris_context *ice);
 732 void gen9_init_state(struct iris_context *ice);
 733 void gen10_init_state(struct iris_context *ice);
 734 void gen11_init_state(struct iris_context *ice);
 735 void gen8_emit_urb_setup(struct iris_context *ice,
 736                           struct iris_batch *batch,
 737                           const unsigned size[4],
 738                           bool tess_present, bool gs_present);
 739 void gen9_emit_urb_setup(struct iris_context *ice,
 740                           struct iris_batch *batch,
 741                           const unsigned size[4],
 742                           bool tess_present, bool gs_present);
 743 void gen10_emit_urb_setup(struct iris_context *ice,
 744                           struct iris_batch *batch,
 745                           const unsigned size[4],
 746                           bool tess_present, bool gs_present);
 747 void gen11_emit_urb_setup(struct iris_context *ice,
 748                           struct iris_batch *batch,
 749                           const unsigned size[4],
 750                           bool tess_present, bool gs_present);
 751
 752 /* iris_program.c */
 753 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 754                                                gl_shader_stage stage);
 755 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 756                                        unsigned per_thread_scratch,
 757                                        gl_shader_stage stage);
 758
 759 /* iris_program_cache.c */
 760
 761 void iris_init_program_cache(struct iris_context *ice);
 762 void iris_destroy_program_cache(struct iris_context *ice);
 763 void iris_print_program_cache(struct iris_context *ice);
 764 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 765                                                      enum iris_program_cache_id,
 766                                                      uint32_t key_size,
 767                                                      const void *key);
 768 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 769                                                 enum iris_program_cache_id,
 770                                                 uint32_t key_size,
 771                                                 const void *key,
 772                                                 const void *assembly,
 773                                                 struct brw_stage_prog_data *,
 774                                                 uint32_t *streamout,
 775                                                 enum brw_param_builtin *sysv,
 776                                                 unsigned num_system_values,
 777                                                 unsigned num_cbufs);
 778 const void *iris_find_previous_compile(const struct iris_context *ice,
 779                                        enum iris_program_cache_id cache_id,
 780                                        unsigned program_string_id);
 781 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 782                               const void *key,
 783                               uint32_t key_size,
 784                               uint32_t *kernel_out,
 785                               void *prog_data_out);
 786 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 787                               const void *key, uint32_t key_size,
 788                               const void *kernel, uint32_t kernel_size,
 789                               const struct brw_stage_prog_data *prog_data,
 790                               uint32_t prog_data_size,
 791                               uint32_t *kernel_out,
 792                               void *prog_data_out);
 793
 794 /* iris_query.c */
 795
 796 void iris_math_div32_gpr0(struct iris_context *ice,
 797                           struct iris_batch *batch,
 798                           uint32_t D);
 799
 800 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 801                              uint64_t gpu_timestamp);
 802 void iris_resolve_conditional_render(struct iris_context *ice);
 803
 804 /* iris_resolve.c */
 805
 806 void iris_predraw_resolve_inputs(struct iris_context *ice,
 807                                  struct iris_batch *batch,
 808                                  bool *draw_aux_buffer_disabled,
 809                                  gl_shader_stage stage,
 810                                  bool consider_framebuffer);
 811 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 812                                       struct iris_batch *batch,
 813                                       bool *draw_aux_buffer_disabled);
 814 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 815                                            struct iris_batch *batch);
 816 void iris_cache_sets_clear(struct iris_batch *batch);
 817 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 818 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 819 void iris_cache_flush_for_render(struct iris_batch *batch,
 820                                  struct iris_bo *bo,
 821                                  enum isl_format format,
 822                                  enum isl_aux_usage aux_usage);
 823 void iris_render_cache_add_bo(struct iris_batch *batch,
 824                               struct iris_bo *bo,
 825                               enum isl_format format,
 826                               enum isl_aux_usage aux_usage);
 827 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 828 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 829
 830 #endif