src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49
  50 /**
  51  * Dirty flags.  When state changes, we flag some combination of these
  52  * to indicate that particular GPU commands need to be re-emitted.
  53  *
  54  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  55  * in rare cases they map to a group of related packets that need to be
  56  * emitted together.
  57  *
  58  * See iris_upload_render_state().
  59  */
  60 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  61 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  62 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  63 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  64 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  65 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  66 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  67 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  68 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  69 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  70 #define IRIS_DIRTY_SBE                      (1ull << 10)
  71 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  72 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  73 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  74 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  75 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  76 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  77 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  78 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  79 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  80 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  81 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  82 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  83 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  84 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  85 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  86 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  87 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  88 #define IRIS_DIRTY_VS                       (1ull << 28)
  89 #define IRIS_DIRTY_TCS                      (1ull << 29)
  90 #define IRIS_DIRTY_TES                      (1ull << 30)
  91 #define IRIS_DIRTY_GS                       (1ull << 31)
  92 #define IRIS_DIRTY_FS                       (1ull << 32)
  93 #define IRIS_DIRTY_CS                       (1ull << 33)
  94 #define IRIS_DIRTY_URB                      (1ull << 34)
  95 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  96 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  97 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  98 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  99 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 100 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 101 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 102 #define IRIS_DIRTY_WM                       (1ull << 42)
 103 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 104 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 105 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 106 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 107 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 108 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 109 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 110 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 111 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 112 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 113 #define IRIS_DIRTY_VF                       (1ull << 53)
 114 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 115
 116 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 117                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 118                                     IRIS_DIRTY_UNCOMPILED_CS | \
 119                                     IRIS_DIRTY_CONSTANTS_CS | \
 120                                     IRIS_DIRTY_BINDINGS_CS)
 121
 122 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 123
 124 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 125                                  IRIS_DIRTY_BINDINGS_TCS | \
 126                                  IRIS_DIRTY_BINDINGS_TES | \
 127                                  IRIS_DIRTY_BINDINGS_GS  | \
 128                                  IRIS_DIRTY_BINDINGS_FS  | \
 129                                  IRIS_DIRTY_BINDINGS_CS)
 130
 131 /**
 132  * Non-orthogonal state (NOS) dependency flags.
 133  *
 134  * Shader programs may depend on non-orthogonal state.  These flags are
 135  * used to indicate that a shader's key depends on the state provided by
 136  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 137  * cause the driver to re-compute the shader key, possibly triggering a
 138  * shader recompile.
 139  */
 140 enum iris_nos_dep {
 141    IRIS_NOS_FRAMEBUFFER,
 142    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 143    IRIS_NOS_RASTERIZER,
 144    IRIS_NOS_BLEND,
 145    IRIS_NOS_LAST_VUE_MAP,
 146
 147    IRIS_NOS_COUNT,
 148 };
 149
 150 struct iris_depth_stencil_alpha_state;
 151
 152 /**
 153  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 154  */
 155 enum iris_program_cache_id {
 156    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 157    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 158    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 159    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 160    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 161    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 162    IRIS_CACHE_BLORP,
 163 };
 164
 165 /** @{
 166  *
 167  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 168  * synchronization, pipelined memory writes, and so on.
 169  *
 170  * The bits here are not the actual hardware values.  The actual fields
 171  * move between various generations, so we just have flags for each
 172  * potential operation, and use genxml to encode the actual packet.
 173  */
 174 enum pipe_control_flags
 175 {
 176    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 177    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 178    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 179    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 180    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 181    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 182    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 183    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 184    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 185    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 186    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 187    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 188    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 189    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 190    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 191    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 192    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 193    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 194    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 195    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 196    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 197    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 198    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 199    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 200 };
 201
 202 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 203    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 204     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 205     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 206
 207 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 208    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 209     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 210     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 211     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 212     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 213
 214 enum iris_predicate_state {
 215    /* The first two states are used if we can determine whether to draw
 216     * without having to look at the values in the query object buffer. This
 217     * will happen if there is no conditional render in progress, if the query
 218     * object is already completed or if something else has already added
 219     * samples to the preliminary result.
 220     */
 221    IRIS_PREDICATE_STATE_RENDER,
 222    IRIS_PREDICATE_STATE_DONT_RENDER,
 223
 224    /* In this case whether to draw or not depends on the result of an
 225     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 226     */
 227    IRIS_PREDICATE_STATE_USE_BIT,
 228 };
 229
 230 /** @} */
 231
 232 /**
 233  * A compiled shader variant, containing a pointer to the GPU assembly,
 234  * as well as program data and other packets needed by state upload.
 235  *
 236  * There can be several iris_compiled_shader variants per API-level shader
 237  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 238  */
 239 struct iris_compiled_shader {
 240    /** Reference to the uploaded assembly. */
 241    struct iris_state_ref assembly;
 242
 243    /** Pointer to the assembly in the BO's map. */
 244    void *map;
 245
 246    /** The program data (owned by the program cache hash table) */
 247    struct brw_stage_prog_data *prog_data;
 248
 249    /** A list of system values to be uploaded as uniforms. */
 250    enum brw_param_builtin *system_values;
 251    unsigned num_system_values;
 252
 253    /**
 254     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 255     * (the VUE-based information for transform feedback outputs).
 256     */
 257    uint32_t *streamout;
 258
 259    /**
 260     * Shader packets and other data derived from prog_data.  These must be
 261     * completely determined from prog_data.
 262     */
 263    uint8_t derived_data[0];
 264 };
 265
 266 /**
 267  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 268  */
 269 struct iris_const_buffer {
 270    /** The resource and offset for the actual constant data */
 271    struct iris_state_ref data;
 272
 273    /** The resource and offset for the SURFACE_STATE for pull access. */
 274    struct iris_state_ref surface_state;
 275 };
 276
 277 /**
 278  * API context state that is replicated per shader stage.
 279  */
 280 struct iris_shader_state {
 281    /** Uniform Buffers */
 282    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 283
 284    struct pipe_constant_buffer cbuf0;
 285    bool cbuf0_needs_upload;
 286
 287    /** Shader Storage Buffers */
 288    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 289    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 290
 291    /** Shader Storage Images (image load store) */
 292    struct {
 293       struct pipe_resource *res;
 294       struct iris_state_ref surface_state;
 295       unsigned access;
 296    } image[PIPE_MAX_SHADER_IMAGES];
 297
 298    struct iris_state_ref sampler_table;
 299    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 300    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 301
 302    /** Bitfield of which image views are bound (non-null). */
 303    uint32_t bound_image_views;
 304
 305    /** Bitfield of which sampler views are bound (non-null). */
 306    uint32_t bound_sampler_views;
 307 };
 308
 309 /**
 310  * Gallium CSO for stream output (transform feedback) targets.
 311  */
 312 struct iris_stream_output_target {
 313    struct pipe_stream_output_target base;
 314
 315    /** Storage holding the offset where we're writing in the buffer */
 316    struct iris_state_ref offset;
 317 };
 318
 319 /**
 320  * Virtual table for generation-specific (genxml) function calls.
 321  */
 322 struct iris_vtable {
 323    void (*destroy_state)(struct iris_context *ice);
 324    void (*init_render_context)(struct iris_screen *screen,
 325                                struct iris_batch *batch,
 326                                struct iris_vtable *vtbl,
 327                                struct pipe_debug_callback *dbg);
 328    void (*init_compute_context)(struct iris_screen *screen,
 329                                 struct iris_batch *batch,
 330                                 struct iris_vtable *vtbl,
 331                                 struct pipe_debug_callback *dbg);
 332    void (*upload_render_state)(struct iris_context *ice,
 333                                struct iris_batch *batch,
 334                                const struct pipe_draw_info *draw);
 335    void (*update_surface_base_address)(struct iris_batch *batch,
 336                                        struct iris_binder *binder);
 337    void (*upload_compute_state)(struct iris_context *ice,
 338                                 struct iris_batch *batch,
 339                                 const struct pipe_grid_info *grid);
 340    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 341                                uint32_t src);
 342    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 343                                uint32_t src);
 344    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 345                                uint32_t val);
 346    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 347                                uint64_t val);
 348    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 349                                struct iris_bo *bo, uint32_t offset);
 350    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 351                                struct iris_bo *bo, uint32_t offset);
 352    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 353                                 struct iris_bo *bo, uint32_t offset,
 354                                 bool predicated);
 355    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 356                                 struct iris_bo *bo, uint32_t offset,
 357                                 bool predicated);
 358    void (*store_data_imm32)(struct iris_batch *batch,
 359                             struct iris_bo *bo, uint32_t offset,
 360                             uint32_t value);
 361    void (*store_data_imm64)(struct iris_batch *batch,
 362                             struct iris_bo *bo, uint32_t offset,
 363                             uint64_t value);
 364    void (*copy_mem_mem)(struct iris_batch *batch,
 365                         struct iris_bo *dst_bo, uint32_t dst_offset,
 366                         struct iris_bo *src_bo, uint32_t src_offset,
 367                         unsigned bytes);
 368    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 369                                  struct iris_bo *bo, uint32_t offset,
 370                                  uint64_t imm);
 371
 372    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 373    void (*store_derived_program_state)(struct iris_context *ice,
 374                                        enum iris_program_cache_id cache_id,
 375                                        struct iris_compiled_shader *shader);
 376    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 377                                     const struct brw_vue_map *vue_map);
 378    void (*populate_vs_key)(const struct iris_context *ice,
 379                            const struct shader_info *info,
 380                            struct brw_vs_prog_key *key);
 381    void (*populate_tcs_key)(const struct iris_context *ice,
 382                             struct brw_tcs_prog_key *key);
 383    void (*populate_tes_key)(const struct iris_context *ice,
 384                             struct brw_tes_prog_key *key);
 385    void (*populate_gs_key)(const struct iris_context *ice,
 386                            struct brw_gs_prog_key *key);
 387    void (*populate_fs_key)(const struct iris_context *ice,
 388                            struct brw_wm_prog_key *key);
 389    void (*populate_cs_key)(const struct iris_context *ice,
 390                            struct brw_cs_prog_key *key);
 391 };
 392
 393 /**
 394  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 395  *
 396  * See iris_border_color.c for more information.
 397  */
 398 struct iris_border_color_pool {
 399    struct iris_bo *bo;
 400    void *map;
 401    unsigned insert_point;
 402
 403    /** Map from border colors to offsets in the buffer. */
 404    struct hash_table *ht;
 405 };
 406
 407 /**
 408  * The API context (derived from pipe_context).
 409  *
 410  * Most driver state is tracked here.
 411  */
 412 struct iris_context {
 413    struct pipe_context ctx;
 414
 415    /** A debug callback for KHR_debug output. */
 416    struct pipe_debug_callback dbg;
 417
 418    /** Slab allocator for iris_transfer_map objects. */
 419    struct slab_child_pool transfer_pool;
 420
 421    struct iris_vtable vtbl;
 422
 423    struct blorp_context blorp;
 424
 425    struct iris_batch batches[IRIS_BATCH_COUNT];
 426
 427    struct {
 428       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 429       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 430       struct brw_vue_map *last_vue_map;
 431
 432       struct u_upload_mgr *uploader;
 433       struct hash_table *cache;
 434
 435       unsigned urb_size;
 436
 437       /**
 438        * Scratch buffers for various sizes and stages.
 439        *
 440        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 441        * and shader stage.
 442        */
 443       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 444    } shaders;
 445
 446    struct {
 447       uint64_t dirty;
 448       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 449
 450       unsigned num_viewports;
 451       unsigned sample_mask;
 452       struct iris_blend_state *cso_blend;
 453       struct iris_rasterizer_state *cso_rast;
 454       struct iris_depth_stencil_alpha_state *cso_zsa;
 455       struct iris_vertex_element_state *cso_vertex_elements;
 456       struct pipe_blend_color blend_color;
 457       struct pipe_poly_stipple poly_stipple;
 458       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 459       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 460       struct pipe_stencil_ref stencil_ref;
 461       struct pipe_framebuffer_state framebuffer;
 462       struct pipe_clip_state clip_planes;
 463
 464       float default_outer_level[4];
 465       float default_inner_level[2];
 466
 467       /** Bitfield of which vertex buffers are bound (non-null). */
 468       uint64_t bound_vertex_buffers;
 469
 470       bool primitive_restart;
 471       unsigned cut_index;
 472       enum pipe_prim_type prim_mode:8;
 473       uint8_t vertices_per_patch;
 474
 475       /** The last compute grid size */
 476       uint32_t last_grid[3];
 477       /** Reference to the BO containing the compute grid size */
 478       struct iris_state_ref grid_size;
 479       /** Reference to the SURFACE_STATE for the compute grid resource */
 480       struct iris_state_ref grid_surf_state;
 481
 482       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 483       bool depth_writes_enabled;
 484
 485       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 486       bool stencil_writes_enabled;
 487
 488       /** GenX-specific current state */
 489       struct iris_genx_state *genx;
 490
 491       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 492
 493       /** Do any samplers (for any stage) need border color? */
 494       bool need_border_colors;
 495
 496       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 497       bool streamout_active;
 498
 499       bool statistics_counters_enabled;
 500
 501       /** Current conditional rendering mode */
 502       enum iris_predicate_state predicate;
 503
 504       /**
 505        * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
 506        * render context that needs to be uploaded to the compute context.
 507        */
 508       struct iris_bo *compute_predicate;
 509
 510       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 511       bool prims_generated_query_active;
 512
 513       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 514       uint32_t *streamout;
 515
 516       /** The SURFACE_STATE for a 1x1x1 null surface. */
 517       struct iris_state_ref unbound_tex;
 518
 519       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 520       struct iris_state_ref null_fb;
 521
 522       struct u_upload_mgr *surface_uploader;
 523       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 524       // "I'm streaming this out at draw time and never want it again!"
 525       struct u_upload_mgr *dynamic_uploader;
 526
 527       struct iris_binder binder;
 528
 529       struct iris_border_color_pool border_color_pool;
 530
 531       /** The high 16-bits of the last VBO/index buffer addresses */
 532       uint16_t last_vbo_high_bits[33];
 533       uint16_t last_index_bo_high_bits;
 534
 535       /**
 536        * Resources containing streamed state which our render context
 537        * currently points to.  Used to re-add these to the validation
 538        * list when we start a new batch and haven't resubmitted commands.
 539        */
 540       struct {
 541          struct pipe_resource *cc_vp;
 542          struct pipe_resource *sf_cl_vp;
 543          struct pipe_resource *color_calc;
 544          struct pipe_resource *scissor;
 545          struct pipe_resource *blend;
 546          struct pipe_resource *index_buffer;
 547       } last_res;
 548    } state;
 549 };
 550
 551 #define perf_debug(dbg, ...) do {                      \
 552    if (INTEL_DEBUG & DEBUG_PERF)                       \
 553       dbg_printf(__VA_ARGS__);                         \
 554    if (unlikely(dbg))                                  \
 555       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 556 } while(0)
 557
 558 double get_time(void);
 559
 560 struct pipe_context *
 561 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 562
 563 void iris_init_blit_functions(struct pipe_context *ctx);
 564 void iris_init_clear_functions(struct pipe_context *ctx);
 565 void iris_init_program_functions(struct pipe_context *ctx);
 566 void iris_init_resource_functions(struct pipe_context *ctx);
 567 void iris_init_query_functions(struct pipe_context *ctx);
 568 void iris_update_compiled_shaders(struct iris_context *ice);
 569 void iris_update_compiled_compute_shader(struct iris_context *ice);
 570 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 571                                     uint32_t *dst);
 572
 573
 574 /* iris_blit.c */
 575 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 576                                   struct pipe_resource *p_res,
 577                                   enum isl_aux_usage aux_usage,
 578                                   bool is_render_target);
 579
 580 /* iris_draw.c */
 581
 582 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 583 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 584
 585 /* iris_pipe_control.c */
 586
 587 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 588                                   uint32_t flags);
 589 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 590                                   struct iris_bo *bo, uint32_t offset,
 591                                   uint64_t imm);
 592 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 593                                 uint32_t flags);
 594
 595 void iris_init_flush_functions(struct pipe_context *ctx);
 596
 597 /* iris_blorp.c */
 598
 599 void gen9_init_blorp(struct iris_context *ice);
 600 void gen10_init_blorp(struct iris_context *ice);
 601 void gen11_init_blorp(struct iris_context *ice);
 602
 603 /* iris_border_color.c */
 604
 605 void iris_init_border_color_pool(struct iris_context *ice);
 606 void iris_destroy_border_color_pool(struct iris_context *ice);
 607 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 608 uint32_t iris_upload_border_color(struct iris_context *ice,
 609                                   union pipe_color_union *color);
 610
 611 /* iris_state.c */
 612
 613 void gen9_init_state(struct iris_context *ice);
 614 void gen10_init_state(struct iris_context *ice);
 615 void gen11_init_state(struct iris_context *ice);
 616
 617 /* iris_program.c */
 618 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 619                                                gl_shader_stage stage);
 620 unsigned iris_get_shader_num_ubos(const struct iris_context *ice,
 621                                   gl_shader_stage stage);
 622 uint32_t iris_get_scratch_space(struct iris_context *ice,
 623                                 unsigned per_thread_scratch,
 624                                 gl_shader_stage stage);
 625
 626 /* iris_program_cache.c */
 627
 628 void iris_init_program_cache(struct iris_context *ice);
 629 void iris_destroy_program_cache(struct iris_context *ice);
 630 void iris_print_program_cache(struct iris_context *ice);
 631 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 632                                                      enum iris_program_cache_id,
 633                                                      uint32_t key_size,
 634                                                      const void *key);
 635 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 636                                                 enum iris_program_cache_id,
 637                                                 uint32_t key_size,
 638                                                 const void *key,
 639                                                 const void *assembly,
 640                                                 struct brw_stage_prog_data *,
 641                                                 uint32_t *streamout,
 642                                                 enum brw_param_builtin *sysv,
 643                                                 unsigned num_system_values);
 644 const void *iris_find_previous_compile(const struct iris_context *ice,
 645                                        enum iris_program_cache_id cache_id,
 646                                        unsigned program_string_id);
 647 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 648                               const void *key,
 649                               uint32_t key_size,
 650                               uint32_t *kernel_out,
 651                               void *prog_data_out);
 652 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 653                               const void *key, uint32_t key_size,
 654                               const void *kernel, uint32_t kernel_size,
 655                               const struct brw_stage_prog_data *prog_data,
 656                               uint32_t prog_data_size,
 657                               uint32_t *kernel_out,
 658                               void *prog_data_out);
 659
 660 /* iris_query.c */
 661
 662 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 663                              uint64_t gpu_timestamp);
 664
 665 /* iris_resolve.c */
 666
 667 void iris_predraw_resolve_inputs(struct iris_context *ice,
 668                                  struct iris_batch *batch);
 669 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 670                                       struct iris_batch *batch);
 671 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 672                                            struct iris_batch *batch);
 673 void iris_cache_sets_clear(struct iris_batch *batch);
 674 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 675 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 676 void iris_cache_flush_for_render(struct iris_batch *batch,
 677                                  struct iris_bo *bo,
 678                                  enum isl_format format,
 679                                  enum isl_aux_usage aux_usage);
 680 void iris_render_cache_add_bo(struct iris_batch *batch,
 681                               struct iris_bo *bo,
 682                               enum isl_format format,
 683                               enum isl_aux_usage aux_usage);
 684 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 685 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 686
 687 #endif