src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35
  36 struct iris_bo;
  37 struct iris_context;
  38 struct blorp_batch;
  39 struct blorp_params;
  40
  41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  44
  45 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  46 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  47 #define IRIS_MAX_ABOS 16
  48 #define IRIS_MAX_SSBOS 16
  49 #define IRIS_MAX_VIEWPORTS 16
  50
  51 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  52 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  53 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  54 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  55 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  56 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  57 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  58 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  59 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  60 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  61 #define IRIS_DIRTY_SBE                      (1ull << 10)
  62 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  63 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  64 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  65 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  66 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  67 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  68 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  69 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  70 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  71 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  72 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  73 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  74 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  75 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  76 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  77 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  78 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  79 #define IRIS_DIRTY_VS                       (1ull << 28)
  80 #define IRIS_DIRTY_TCS                      (1ull << 29)
  81 #define IRIS_DIRTY_TES                      (1ull << 30)
  82 #define IRIS_DIRTY_GS                       (1ull << 31)
  83 #define IRIS_DIRTY_FS                       (1ull << 32)
  84 #define IRIS_DIRTY_CS                       (1ull << 33)
  85 #define IRIS_DIRTY_URB                      (1ull << 34)
  86 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  87 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  88 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  89 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  90 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  91 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 40)
  92 #define IRIS_DIRTY_WM                       (1ull << 41)
  93 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 42)
  94 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 43)
  95 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 44)
  96 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 45)
  97 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 46)
  98 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 47)
  99 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 48)
 100 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 49)
 101 #define IRIS_DIRTY_STREAMOUT                (1ull << 50)
 102 #define IRIS_DIRTY_VF_SGVS                  (1ull << 51)
 103
 104 /**
 105  * Non-orthogonal state (NOS) dependency flags.
 106  *
 107  * Shader programs may depend on non-orthogonal state.  These flags are
 108  * used to indicate that a shader's key depends on the state provided by
 109  * a certain Gallium CSO.
 110  */
 111 enum iris_nos_dep {
 112    IRIS_NOS_FRAMEBUFFER,
 113    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 114    IRIS_NOS_RASTERIZER,
 115    IRIS_NOS_BLEND,
 116
 117    IRIS_NOS_COUNT,
 118 };
 119
 120 struct iris_depth_stencil_alpha_state;
 121
 122 enum iris_program_cache_id {
 123    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 124    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 125    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 126    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 127    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 128    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 129    IRIS_CACHE_BLORP,
 130 };
 131
 132 /** @{
 133  *
 134  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
 135  * additional flushing control.
 136  *
 137  * The bits here are not the actual hardware values.  The actual values
 138  * shift around a bit per-generation, so we just have flags for each
 139  * potential operation, and use genxml to encode the actual packet.
 140  */
 141 enum pipe_control_flags
 142 {
 143    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 144    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 145    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 146    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 147    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 148    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 149    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 150    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 151    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 152    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 153    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 154    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 155    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 156    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 157    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 158    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 159    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 160    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 161    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 162    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 163    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 164    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 165    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 166    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 167 };
 168
 169 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 170    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 171     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 172     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 173
 174 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 175    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 176     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 177     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 178     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 179     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 180
 181 /** @} */
 182
 183 struct iris_compiled_shader {
 184    /** Reference to the uploaded assembly. */
 185    struct iris_state_ref assembly;
 186
 187    /** Pointer to the assembly in the BO's map. */
 188    void *map;
 189
 190    /** The program data (owned by the program cache hash table) */
 191    struct brw_stage_prog_data *prog_data;
 192
 193    /**
 194     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 195     * (the VUE-based information for transform feedback outputs).
 196     */
 197    uint32_t *streamout;
 198
 199    /**
 200     * Shader packets and other data derived from prog_data.  These must be
 201     * completely determined from prog_data.
 202     */
 203    uint8_t derived_data[0];
 204 };
 205
 206 struct iris_const_buffer {
 207    /** The resource and offset for the actual constant data */
 208    struct iris_state_ref data;
 209
 210    /** The resource and offset for the SURFACE_STATE for pull access. */
 211    struct iris_state_ref surface_state;
 212 };
 213
 214 struct iris_shader_state {
 215    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 216    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 217    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 218 };
 219
 220 struct iris_vtable {
 221    void (*destroy_state)(struct iris_context *ice);
 222    void (*init_render_context)(struct iris_screen *screen,
 223                                struct iris_batch *batch,
 224                                struct iris_vtable *vtbl,
 225                                struct pipe_debug_callback *dbg);
 226    void (*upload_render_state)(struct iris_context *ice,
 227                                struct iris_batch *batch,
 228                                const struct pipe_draw_info *draw);
 229    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 230                                  struct iris_bo *bo, uint32_t offset,
 231                                  uint64_t imm);
 232
 233    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 234    void (*store_derived_program_state)(const struct gen_device_info *devinfo,
 235                                        enum iris_program_cache_id cache_id,
 236                                        struct iris_compiled_shader *shader);
 237    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 238                                     const struct brw_vue_map *vue_map);
 239    void (*populate_vs_key)(const struct iris_context *ice,
 240                            struct brw_vs_prog_key *key);
 241    void (*populate_tcs_key)(const struct iris_context *ice,
 242                             struct brw_tcs_prog_key *key);
 243    void (*populate_tes_key)(const struct iris_context *ice,
 244                             struct brw_tes_prog_key *key);
 245    void (*populate_gs_key)(const struct iris_context *ice,
 246                            struct brw_gs_prog_key *key);
 247    void (*populate_fs_key)(const struct iris_context *ice,
 248                            struct brw_wm_prog_key *key);
 249 };
 250
 251 struct iris_border_color_pool {
 252    struct iris_bo *bo;
 253    void *map;
 254    unsigned insert_point;
 255
 256    /** Map from border colors to offsets in the buffer. */
 257    struct hash_table *ht;
 258 };
 259
 260 struct iris_context {
 261    struct pipe_context ctx;
 262
 263    struct pipe_debug_callback dbg;
 264
 265    struct slab_child_pool transfer_pool;
 266
 267    struct iris_vtable vtbl;
 268
 269    struct {
 270       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 271       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 272       struct brw_vue_map *last_vue_map;
 273
 274       struct iris_shader_state state[MESA_SHADER_STAGES];
 275
 276       struct u_upload_mgr *uploader;
 277       struct hash_table *cache;
 278
 279       unsigned urb_size;
 280    } shaders;
 281
 282    struct blorp_context blorp;
 283
 284    /** The main batch for rendering */
 285    struct iris_batch render_batch;
 286
 287    struct {
 288       uint64_t dirty;
 289       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 290       unsigned num_viewports;
 291       unsigned sample_mask;
 292       struct iris_blend_state *cso_blend;
 293       struct iris_rasterizer_state *cso_rast;
 294       struct iris_depth_stencil_alpha_state *cso_zsa;
 295       struct iris_vertex_element_state *cso_vertex_elements;
 296       struct pipe_blend_color blend_color;
 297       struct pipe_poly_stipple poly_stipple;
 298       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 299       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 300       struct pipe_stencil_ref stencil_ref;
 301       struct pipe_framebuffer_state framebuffer;
 302
 303       struct iris_genx_state *genx;
 304
 305       struct iris_state_ref sampler_table[MESA_SHADER_STAGES];
 306       bool need_border_colors;
 307       struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 308       struct iris_sampler_view *textures[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 309       unsigned num_samplers[MESA_SHADER_STAGES];
 310       unsigned num_textures[MESA_SHADER_STAGES];
 311
 312       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 313       bool streamout_active;
 314       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 315       uint32_t *streamout;
 316
 317       /** The SURFACE_STATE for a 1x1x1 null surface. */
 318       struct iris_state_ref unbound_tex;
 319
 320       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 321       struct iris_state_ref null_fb;
 322
 323       struct u_upload_mgr *surface_uploader;
 324       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 325       // "I'm streaming this out at draw time and never want it again!"
 326       struct u_upload_mgr *dynamic_uploader;
 327
 328       struct iris_border_color_pool border_color_pool;
 329
 330       /**
 331        * Resources containing streamed state which our render context
 332        * currently points to.  Used to re-add these to the validation
 333        * list when we start a new batch and haven't resubmitted commands.
 334        */
 335       struct {
 336          struct pipe_resource *cc_vp;
 337          struct pipe_resource *sf_cl_vp;
 338          struct pipe_resource *color_calc;
 339          struct pipe_resource *scissor;
 340          struct pipe_resource *blend;
 341       } last_res;
 342    } state;
 343 };
 344
 345 #define perf_debug(dbg, ...) do {                      \
 346    if (INTEL_DEBUG & DEBUG_PERF)                       \
 347       dbg_printf(__VA_ARGS__);                         \
 348    if (unlikely(dbg))                                  \
 349       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 350 } while(0)
 351
 352 double get_time(void);
 353
 354 struct pipe_context *
 355 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 356
 357 void iris_init_blit_functions(struct pipe_context *ctx);
 358 void iris_init_clear_functions(struct pipe_context *ctx);
 359 void iris_init_program_functions(struct pipe_context *ctx);
 360 void iris_init_resource_functions(struct pipe_context *ctx);
 361 void iris_init_query_functions(struct pipe_context *ctx);
 362 void iris_update_compiled_shaders(struct iris_context *ice);
 363
 364 /* iris_blit.c */
 365 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 366                                   struct pipe_resource *p_res,
 367                                   enum isl_aux_usage aux_usage,
 368                                   bool is_render_target);
 369
 370 /* iris_draw.c */
 371
 372 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 373
 374 /* iris_pipe_control.c */
 375
 376 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 377                                   uint32_t flags);
 378 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 379                                   struct iris_bo *bo, uint32_t offset,
 380                                   uint64_t imm);
 381 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 382                                 uint32_t flags);
 383
 384 void iris_cache_sets_clear(struct iris_batch *batch);
 385 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 386 void iris_cache_flush_for_render(struct iris_batch *batch,
 387                                  struct iris_bo *bo,
 388                                  enum isl_format format,
 389                                  enum isl_aux_usage aux_usage);
 390 void iris_render_cache_add_bo(struct iris_batch *batch,
 391                               struct iris_bo *bo,
 392                               enum isl_format format,
 393                               enum isl_aux_usage aux_usage);
 394 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 395 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 396
 397 void iris_init_flush_functions(struct pipe_context *ctx);
 398
 399 /* iris_blorp.c */
 400
 401 void gen9_init_blorp(struct iris_context *ice);
 402 void gen10_init_blorp(struct iris_context *ice);
 403
 404 /* iris_border_color.c */
 405
 406 void iris_init_border_color_pool(struct iris_context *ice);
 407 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 408 uint32_t iris_upload_border_color(struct iris_context *ice,
 409                                   union pipe_color_union *color);
 410
 411 /* iris_state.c */
 412
 413 void gen9_init_state(struct iris_context *ice);
 414 void gen10_init_state(struct iris_context *ice);
 415
 416 /* iris_program.c */
 417 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 418                                                gl_shader_stage stage);
 419
 420 /* iris_program_cache.c */
 421
 422 void iris_init_program_cache(struct iris_context *ice);
 423 void iris_destroy_program_cache(struct iris_context *ice);
 424 void iris_print_program_cache(struct iris_context *ice);
 425 bool iris_bind_cached_shader(struct iris_context *ice,
 426                              enum iris_program_cache_id cache_id,
 427                              const void *key);
 428 void iris_unbind_shader(struct iris_context *ice,
 429                         enum iris_program_cache_id cache_id);
 430 void iris_upload_and_bind_shader(struct iris_context *ice,
 431                                  enum iris_program_cache_id cache_id,
 432                                  const void *key,
 433                                  const void *assembly,
 434                                  struct brw_stage_prog_data *prog_data,
 435                                  uint32_t *streamout);
 436 const void *iris_find_previous_compile(const struct iris_context *ice,
 437                                        enum iris_program_cache_id cache_id,
 438                                        unsigned program_string_id);
 439 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 440                               const void *key,
 441                               uint32_t key_size,
 442                               uint32_t *kernel_out,
 443                               void *prog_data_out);
 444 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 445                               const void *key, uint32_t key_size,
 446                               const void *kernel, uint32_t kernel_size,
 447                               const struct brw_stage_prog_data *prog_data,
 448                               uint32_t prog_data_size,
 449                               uint32_t *kernel_out,
 450                               void *prog_data_out);
 451
 452 #endif