src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_resource.h"
  34 #include "iris_screen.h"
  35
  36 struct iris_bo;
  37 struct iris_context;
  38 struct blorp_batch;
  39 struct blorp_params;
  40
  41 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  42 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  43 #define IRIS_MAX_ABOS 16
  44 #define IRIS_MAX_SSBOS 16
  45 #define IRIS_MAX_VIEWPORTS 16
  46
  47 /**
  48  * Dirty flags.  When state changes, we flag some combination of these
  49  * to indicate that particular GPU commands need to be re-emitted.
  50  *
  51  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  52  * in rare cases they map to a group of related packets that need to be
  53  * emitted together.
  54  *
  55  * See iris_upload_render_state().
  56  */
  57 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  58 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  59 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  60 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  61 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  62 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  63 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  64 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  65 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  66 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  67 #define IRIS_DIRTY_SBE                      (1ull << 10)
  68 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  69 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  70 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  71 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  72 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  73 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  74 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  75 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  76 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  77 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  78 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  79 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  80 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  81 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  82 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  83 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  84 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  85 #define IRIS_DIRTY_VS                       (1ull << 28)
  86 #define IRIS_DIRTY_TCS                      (1ull << 29)
  87 #define IRIS_DIRTY_TES                      (1ull << 30)
  88 #define IRIS_DIRTY_GS                       (1ull << 31)
  89 #define IRIS_DIRTY_FS                       (1ull << 32)
  90 #define IRIS_DIRTY_CS                       (1ull << 33)
  91 #define IRIS_DIRTY_URB                      (1ull << 34)
  92 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  93 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  94 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  95 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  96 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  97 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 40)
  98 #define IRIS_DIRTY_WM                       (1ull << 41)
  99 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 42)
 100 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 43)
 101 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 44)
 102 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 45)
 103 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 46)
 104 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 47)
 105 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 48)
 106 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 49)
 107 #define IRIS_DIRTY_STREAMOUT                (1ull << 50)
 108 #define IRIS_DIRTY_VF_SGVS                  (1ull << 51)
 109
 110 /**
 111  * Non-orthogonal state (NOS) dependency flags.
 112  *
 113  * Shader programs may depend on non-orthogonal state.  These flags are
 114  * used to indicate that a shader's key depends on the state provided by
 115  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 116  * cause the driver to re-compute the shader key, possibly triggering a
 117  * shader recompile.
 118  */
 119 enum iris_nos_dep {
 120    IRIS_NOS_FRAMEBUFFER,
 121    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 122    IRIS_NOS_RASTERIZER,
 123    IRIS_NOS_BLEND,
 124    IRIS_NOS_LAST_VUE_MAP,
 125
 126    IRIS_NOS_COUNT,
 127 };
 128
 129 struct iris_depth_stencil_alpha_state;
 130
 131 /**
 132  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 133  */
 134 enum iris_program_cache_id {
 135    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 136    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 137    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 138    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 139    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 140    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 141    IRIS_CACHE_BLORP,
 142 };
 143
 144 /** @{
 145  *
 146  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 147  * synchronization, pipelined memory writes, and so on.
 148  *
 149  * The bits here are not the actual hardware values.  The actual fields
 150  * move between various generations, so we just have flags for each
 151  * potential operation, and use genxml to encode the actual packet.
 152  */
 153 enum pipe_control_flags
 154 {
 155    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 156    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 157    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 158    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 159    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 160    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 161    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 162    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 163    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 164    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 165    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 166    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 167    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 168    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 169    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 170    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 171    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 172    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 173    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 174    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 175    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 176    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 177    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 178    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 179 };
 180
 181 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 182    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 183     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 184     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 185
 186 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 187    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 188     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 189     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 190     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 191     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 192
 193 /** @} */
 194
 195 /**
 196  * A compiled shader variant, containing a pointer to the GPU assembly,
 197  * as well as program data and other packets needed by state upload.
 198  *
 199  * There can be several iris_compiled_shader variants per API-level shader
 200  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 201  */
 202 struct iris_compiled_shader {
 203    /** Reference to the uploaded assembly. */
 204    struct iris_state_ref assembly;
 205
 206    /** Pointer to the assembly in the BO's map. */
 207    void *map;
 208
 209    /** The program data (owned by the program cache hash table) */
 210    struct brw_stage_prog_data *prog_data;
 211
 212    /**
 213     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 214     * (the VUE-based information for transform feedback outputs).
 215     */
 216    uint32_t *streamout;
 217
 218    /**
 219     * Shader packets and other data derived from prog_data.  These must be
 220     * completely determined from prog_data.
 221     */
 222    uint8_t derived_data[0];
 223 };
 224
 225 /**
 226  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 227  */
 228 struct iris_const_buffer {
 229    /** The resource and offset for the actual constant data */
 230    struct iris_state_ref data;
 231
 232    /** The resource and offset for the SURFACE_STATE for pull access. */
 233    struct iris_state_ref surface_state;
 234 };
 235
 236 /**
 237  * API context state that is replicated per shader stage.
 238  */
 239 struct iris_shader_state {
 240    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 241    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 242    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 243
 244    struct iris_state_ref sampler_table;
 245    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 246    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 247    unsigned num_samplers;
 248    unsigned num_textures;
 249 };
 250
 251 /**
 252  * Virtual table for generation-specific (genxml) function calls.
 253  */
 254 struct iris_vtable {
 255    void (*destroy_state)(struct iris_context *ice);
 256    void (*init_render_context)(struct iris_screen *screen,
 257                                struct iris_batch *batch,
 258                                struct iris_vtable *vtbl,
 259                                struct pipe_debug_callback *dbg);
 260    void (*upload_render_state)(struct iris_context *ice,
 261                                struct iris_batch *batch,
 262                                const struct pipe_draw_info *draw);
 263    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 264                                  struct iris_bo *bo, uint32_t offset,
 265                                  uint64_t imm);
 266
 267    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 268    void (*store_derived_program_state)(const struct gen_device_info *devinfo,
 269                                        enum iris_program_cache_id cache_id,
 270                                        struct iris_compiled_shader *shader);
 271    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 272                                     const struct brw_vue_map *vue_map);
 273    void (*populate_vs_key)(const struct iris_context *ice,
 274                            struct brw_vs_prog_key *key);
 275    void (*populate_tcs_key)(const struct iris_context *ice,
 276                             struct brw_tcs_prog_key *key);
 277    void (*populate_tes_key)(const struct iris_context *ice,
 278                             struct brw_tes_prog_key *key);
 279    void (*populate_gs_key)(const struct iris_context *ice,
 280                            struct brw_gs_prog_key *key);
 281    void (*populate_fs_key)(const struct iris_context *ice,
 282                            struct brw_wm_prog_key *key);
 283 };
 284
 285 /**
 286  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 287  *
 288  * See iris_border_color.c for more information.
 289  */
 290 struct iris_border_color_pool {
 291    struct iris_bo *bo;
 292    void *map;
 293    unsigned insert_point;
 294
 295    /** Map from border colors to offsets in the buffer. */
 296    struct hash_table *ht;
 297 };
 298
 299 /**
 300  * The API context (derived from pipe_context).
 301  *
 302  * Most driver state is tracked here.
 303  */
 304 struct iris_context {
 305    struct pipe_context ctx;
 306
 307    /** A debug callback for KHR_debug output. */
 308    struct pipe_debug_callback dbg;
 309
 310    /** Slab allocator for iris_transfer_map objects. */
 311    struct slab_child_pool transfer_pool;
 312
 313    struct iris_vtable vtbl;
 314
 315    struct blorp_context blorp;
 316
 317    /** The main batch for rendering. */
 318    struct iris_batch render_batch;
 319
 320    struct {
 321       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 322       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 323       struct brw_vue_map *last_vue_map;
 324
 325       struct u_upload_mgr *uploader;
 326       struct hash_table *cache;
 327
 328       unsigned urb_size;
 329    } shaders;
 330
 331    struct {
 332       uint64_t dirty;
 333       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 334
 335       unsigned num_viewports;
 336       unsigned sample_mask;
 337       struct iris_blend_state *cso_blend;
 338       struct iris_rasterizer_state *cso_rast;
 339       struct iris_depth_stencil_alpha_state *cso_zsa;
 340       struct iris_vertex_element_state *cso_vertex_elements;
 341       struct pipe_blend_color blend_color;
 342       struct pipe_poly_stipple poly_stipple;
 343       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 344       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 345       struct pipe_stencil_ref stencil_ref;
 346       struct pipe_framebuffer_state framebuffer;
 347
 348       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 349       bool depth_writes_enabled;
 350
 351       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 352       bool stencil_writes_enabled;
 353
 354       /** GenX-specific current state */
 355       struct iris_genx_state *genx;
 356
 357       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 358
 359       /** Do any samplers (for any stage) need border color? */
 360       bool need_border_colors;
 361
 362       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 363       bool streamout_active;
 364       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 365       uint32_t *streamout;
 366
 367       /** The SURFACE_STATE for a 1x1x1 null surface. */
 368       struct iris_state_ref unbound_tex;
 369
 370       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 371       struct iris_state_ref null_fb;
 372
 373       struct u_upload_mgr *surface_uploader;
 374       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 375       // "I'm streaming this out at draw time and never want it again!"
 376       struct u_upload_mgr *dynamic_uploader;
 377
 378       struct iris_border_color_pool border_color_pool;
 379
 380       /**
 381        * Resources containing streamed state which our render context
 382        * currently points to.  Used to re-add these to the validation
 383        * list when we start a new batch and haven't resubmitted commands.
 384        */
 385       struct {
 386          struct pipe_resource *cc_vp;
 387          struct pipe_resource *sf_cl_vp;
 388          struct pipe_resource *color_calc;
 389          struct pipe_resource *scissor;
 390          struct pipe_resource *blend;
 391       } last_res;
 392    } state;
 393 };
 394
 395 #define perf_debug(dbg, ...) do {                      \
 396    if (INTEL_DEBUG & DEBUG_PERF)                       \
 397       dbg_printf(__VA_ARGS__);                         \
 398    if (unlikely(dbg))                                  \
 399       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 400 } while(0)
 401
 402 double get_time(void);
 403
 404 struct pipe_context *
 405 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 406
 407 void iris_init_blit_functions(struct pipe_context *ctx);
 408 void iris_init_clear_functions(struct pipe_context *ctx);
 409 void iris_init_program_functions(struct pipe_context *ctx);
 410 void iris_init_resource_functions(struct pipe_context *ctx);
 411 void iris_init_query_functions(struct pipe_context *ctx);
 412 void iris_update_compiled_shaders(struct iris_context *ice);
 413
 414 /* iris_blit.c */
 415 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 416                                   struct pipe_resource *p_res,
 417                                   enum isl_aux_usage aux_usage,
 418                                   bool is_render_target);
 419
 420 /* iris_draw.c */
 421
 422 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 423
 424 /* iris_pipe_control.c */
 425
 426 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 427                                   uint32_t flags);
 428 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 429                                   struct iris_bo *bo, uint32_t offset,
 430                                   uint64_t imm);
 431 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 432                                 uint32_t flags);
 433
 434 void iris_init_flush_functions(struct pipe_context *ctx);
 435
 436 /* iris_blorp.c */
 437
 438 void gen9_init_blorp(struct iris_context *ice);
 439 void gen10_init_blorp(struct iris_context *ice);
 440
 441 /* iris_border_color.c */
 442
 443 void iris_init_border_color_pool(struct iris_context *ice);
 444 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 445 uint32_t iris_upload_border_color(struct iris_context *ice,
 446                                   union pipe_color_union *color);
 447
 448 /* iris_state.c */
 449
 450 void gen9_init_state(struct iris_context *ice);
 451 void gen10_init_state(struct iris_context *ice);
 452
 453 /* iris_program.c */
 454 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 455                                                gl_shader_stage stage);
 456
 457 /* iris_program_cache.c */
 458
 459 void iris_init_program_cache(struct iris_context *ice);
 460 void iris_destroy_program_cache(struct iris_context *ice);
 461 void iris_print_program_cache(struct iris_context *ice);
 462 bool iris_bind_cached_shader(struct iris_context *ice,
 463                              enum iris_program_cache_id cache_id,
 464                              const void *key);
 465 void iris_unbind_shader(struct iris_context *ice,
 466                         enum iris_program_cache_id cache_id);
 467 void iris_upload_and_bind_shader(struct iris_context *ice,
 468                                  enum iris_program_cache_id cache_id,
 469                                  const void *key,
 470                                  const void *assembly,
 471                                  struct brw_stage_prog_data *prog_data,
 472                                  uint32_t *streamout);
 473 const void *iris_find_previous_compile(const struct iris_context *ice,
 474                                        enum iris_program_cache_id cache_id,
 475                                        unsigned program_string_id);
 476 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 477                               const void *key,
 478                               uint32_t key_size,
 479                               uint32_t *kernel_out,
 480                               void *prog_data_out);
 481 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 482                               const void *key, uint32_t key_size,
 483                               const void *kernel, uint32_t kernel_size,
 484                               const struct brw_stage_prog_data *prog_data,
 485                               uint32_t prog_data_size,
 486                               uint32_t *kernel_out,
 487                               void *prog_data_out);
 488
 489 /* iris_resolve.c */
 490
 491 void iris_cache_sets_clear(struct iris_batch *batch);
 492 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 493 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 494 void iris_cache_flush_for_render(struct iris_batch *batch,
 495                                  struct iris_bo *bo,
 496                                  enum isl_format format,
 497                                  enum isl_aux_usage aux_usage);
 498 void iris_render_cache_add_bo(struct iris_batch *batch,
 499                               struct iris_bo *bo,
 500                               enum isl_format format,
 501                               enum isl_aux_usage aux_usage);
 502 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 503 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 504
 505 #endif