src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_resource.h"
  35 #include "iris_screen.h"
  36
  37 struct iris_bo;
  38 struct iris_context;
  39 struct blorp_batch;
  40 struct blorp_params;
  41
  42 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  43 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  44 #define IRIS_MAX_ABOS 16
  45 #define IRIS_MAX_SSBOS 16
  46 #define IRIS_MAX_VIEWPORTS 16
  47
  48 /**
  49  * Dirty flags.  When state changes, we flag some combination of these
  50  * to indicate that particular GPU commands need to be re-emitted.
  51  *
  52  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  53  * in rare cases they map to a group of related packets that need to be
  54  * emitted together.
  55  *
  56  * See iris_upload_render_state().
  57  */
  58 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  59 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  60 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  61 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  62 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  63 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  64 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  65 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  66 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  67 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  68 #define IRIS_DIRTY_SBE                      (1ull << 10)
  69 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  70 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  71 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  72 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  73 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  74 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  75 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  76 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  77 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  78 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  79 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  80 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  81 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  82 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  83 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  84 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  85 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  86 #define IRIS_DIRTY_VS                       (1ull << 28)
  87 #define IRIS_DIRTY_TCS                      (1ull << 29)
  88 #define IRIS_DIRTY_TES                      (1ull << 30)
  89 #define IRIS_DIRTY_GS                       (1ull << 31)
  90 #define IRIS_DIRTY_FS                       (1ull << 32)
  91 #define IRIS_DIRTY_CS                       (1ull << 33)
  92 #define IRIS_DIRTY_URB                      (1ull << 34)
  93 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  94 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  95 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  96 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  97 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  98 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
  99 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 100 #define IRIS_DIRTY_WM                       (1ull << 42)
 101 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 102 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 103 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 104 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 105 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 106 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 107 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 108 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 109 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 110 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 111 #define IRIS_DIRTY_VF                       (1ull << 53)
 112 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 113
 114 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 115                                  IRIS_DIRTY_BINDINGS_TCS | \
 116                                  IRIS_DIRTY_BINDINGS_TES | \
 117                                  IRIS_DIRTY_BINDINGS_GS  | \
 118                                  IRIS_DIRTY_BINDINGS_FS  | \
 119                                  IRIS_DIRTY_BINDINGS_CS)
 120
 121 /**
 122  * Non-orthogonal state (NOS) dependency flags.
 123  *
 124  * Shader programs may depend on non-orthogonal state.  These flags are
 125  * used to indicate that a shader's key depends on the state provided by
 126  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 127  * cause the driver to re-compute the shader key, possibly triggering a
 128  * shader recompile.
 129  */
 130 enum iris_nos_dep {
 131    IRIS_NOS_FRAMEBUFFER,
 132    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 133    IRIS_NOS_RASTERIZER,
 134    IRIS_NOS_BLEND,
 135    IRIS_NOS_LAST_VUE_MAP,
 136
 137    IRIS_NOS_COUNT,
 138 };
 139
 140 struct iris_depth_stencil_alpha_state;
 141
 142 /**
 143  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 144  */
 145 enum iris_program_cache_id {
 146    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 147    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 148    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 149    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 150    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 151    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 152    IRIS_CACHE_BLORP,
 153 };
 154
 155 /** @{
 156  *
 157  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 158  * synchronization, pipelined memory writes, and so on.
 159  *
 160  * The bits here are not the actual hardware values.  The actual fields
 161  * move between various generations, so we just have flags for each
 162  * potential operation, and use genxml to encode the actual packet.
 163  */
 164 enum pipe_control_flags
 165 {
 166    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 167    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 168    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 169    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 170    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 171    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 172    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 173    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 174    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 175    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 176    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 177    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 178    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 179    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 180    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 181    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 182    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 183    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 184    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 185    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 186    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 187    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 188    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 189    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 190 };
 191
 192 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 193    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 194     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 195     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 196
 197 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 198    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 199     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 200     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 201     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 202     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 203
 204 /** @} */
 205
 206 /**
 207  * A compiled shader variant, containing a pointer to the GPU assembly,
 208  * as well as program data and other packets needed by state upload.
 209  *
 210  * There can be several iris_compiled_shader variants per API-level shader
 211  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 212  */
 213 struct iris_compiled_shader {
 214    /** Reference to the uploaded assembly. */
 215    struct iris_state_ref assembly;
 216
 217    /** Pointer to the assembly in the BO's map. */
 218    void *map;
 219
 220    /** The program data (owned by the program cache hash table) */
 221    struct brw_stage_prog_data *prog_data;
 222
 223    /**
 224     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 225     * (the VUE-based information for transform feedback outputs).
 226     */
 227    uint32_t *streamout;
 228
 229    /**
 230     * Shader packets and other data derived from prog_data.  These must be
 231     * completely determined from prog_data.
 232     */
 233    uint8_t derived_data[0];
 234 };
 235
 236 /**
 237  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 238  */
 239 struct iris_const_buffer {
 240    /** The resource and offset for the actual constant data */
 241    struct iris_state_ref data;
 242
 243    /** The resource and offset for the SURFACE_STATE for pull access. */
 244    struct iris_state_ref surface_state;
 245 };
 246
 247 /**
 248  * API context state that is replicated per shader stage.
 249  */
 250 struct iris_shader_state {
 251    /** Uniform Buffers */
 252    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 253
 254    /** Shader Storage Buffers */
 255    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 256    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 257
 258    /** Shader Storage Images (image load store) */
 259    struct {
 260       struct pipe_resource *res;
 261       struct iris_state_ref surface_state;
 262       unsigned access;
 263    } image[PIPE_MAX_SHADER_IMAGES];
 264
 265    struct iris_state_ref sampler_table;
 266    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 267    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 268    unsigned num_samplers;
 269    unsigned num_textures;
 270 };
 271
 272 /**
 273  * Virtual table for generation-specific (genxml) function calls.
 274  */
 275 struct iris_vtable {
 276    void (*destroy_state)(struct iris_context *ice);
 277    void (*init_render_context)(struct iris_screen *screen,
 278                                struct iris_batch *batch,
 279                                struct iris_vtable *vtbl,
 280                                struct pipe_debug_callback *dbg);
 281    void (*init_compute_context)(struct iris_screen *screen,
 282                                 struct iris_batch *batch,
 283                                 struct iris_vtable *vtbl,
 284                                 struct pipe_debug_callback *dbg);
 285    void (*upload_render_state)(struct iris_context *ice,
 286                                struct iris_batch *batch,
 287                                const struct pipe_draw_info *draw);
 288    void (*update_surface_base_address)(struct iris_batch *batch,
 289                                        struct iris_binder *binder);
 290    void (*upload_compute_state)(struct iris_context *ice,
 291                                 struct iris_batch *batch,
 292                                 const struct pipe_grid_info *grid);
 293    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 294                                uint32_t val);
 295    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 296                                uint64_t val);
 297    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 298                                struct iris_bo *bo, uint32_t offset);
 299    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 300                                struct iris_bo *bo, uint32_t offset);
 301    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 302                                 struct iris_bo *bo, uint32_t offset,
 303                                 bool predicated);
 304    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 305                                 struct iris_bo *bo, uint32_t offset,
 306                                 bool predicated);
 307    void (*store_data_imm32)(struct iris_batch *batch,
 308                             struct iris_bo *bo, uint32_t offset,
 309                             uint32_t value);
 310    void (*store_data_imm64)(struct iris_batch *batch,
 311                             struct iris_bo *bo, uint32_t offset,
 312                             uint64_t value);
 313    void (*copy_mem_mem)(struct iris_batch *batch,
 314                         struct iris_bo *dst_bo, uint32_t dst_offset,
 315                         struct iris_bo *src_bo, uint32_t src_offset,
 316                         unsigned bytes);
 317    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 318                                  struct iris_bo *bo, uint32_t offset,
 319                                  uint64_t imm);
 320
 321    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 322    void (*store_derived_program_state)(const struct gen_device_info *devinfo,
 323                                        enum iris_program_cache_id cache_id,
 324                                        struct iris_compiled_shader *shader);
 325    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 326                                     const struct brw_vue_map *vue_map);
 327    void (*populate_vs_key)(const struct iris_context *ice,
 328                            struct brw_vs_prog_key *key);
 329    void (*populate_tcs_key)(const struct iris_context *ice,
 330                             struct brw_tcs_prog_key *key);
 331    void (*populate_tes_key)(const struct iris_context *ice,
 332                             struct brw_tes_prog_key *key);
 333    void (*populate_gs_key)(const struct iris_context *ice,
 334                            struct brw_gs_prog_key *key);
 335    void (*populate_fs_key)(const struct iris_context *ice,
 336                            struct brw_wm_prog_key *key);
 337    void (*populate_cs_key)(const struct iris_context *ice,
 338                            struct brw_cs_prog_key *key);
 339 };
 340
 341 /**
 342  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 343  *
 344  * See iris_border_color.c for more information.
 345  */
 346 struct iris_border_color_pool {
 347    struct iris_bo *bo;
 348    void *map;
 349    unsigned insert_point;
 350
 351    /** Map from border colors to offsets in the buffer. */
 352    struct hash_table *ht;
 353 };
 354
 355 /**
 356  * The API context (derived from pipe_context).
 357  *
 358  * Most driver state is tracked here.
 359  */
 360 struct iris_context {
 361    struct pipe_context ctx;
 362
 363    /** A debug callback for KHR_debug output. */
 364    struct pipe_debug_callback dbg;
 365
 366    /** Slab allocator for iris_transfer_map objects. */
 367    struct slab_child_pool transfer_pool;
 368
 369    struct iris_vtable vtbl;
 370
 371    struct blorp_context blorp;
 372
 373    /** The main batch for rendering. */
 374    struct iris_batch render_batch;
 375
 376    /** The batch for compute shader dispatch */
 377    struct iris_batch compute_batch;
 378
 379    struct {
 380       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 381       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 382       struct brw_vue_map *last_vue_map;
 383
 384       struct u_upload_mgr *uploader;
 385       struct hash_table *cache;
 386
 387       unsigned urb_size;
 388    } shaders;
 389
 390    struct {
 391       uint64_t dirty;
 392       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 393
 394       unsigned num_viewports;
 395       unsigned sample_mask;
 396       struct iris_blend_state *cso_blend;
 397       struct iris_rasterizer_state *cso_rast;
 398       struct iris_depth_stencil_alpha_state *cso_zsa;
 399       struct iris_vertex_element_state *cso_vertex_elements;
 400       struct pipe_blend_color blend_color;
 401       struct pipe_poly_stipple poly_stipple;
 402       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 403       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 404       struct pipe_stencil_ref stencil_ref;
 405       struct pipe_framebuffer_state framebuffer;
 406
 407       float default_outer_level[4];
 408       float default_inner_level[2];
 409
 410       bool primitive_restart;
 411       unsigned cut_index;
 412       enum pipe_prim_type prim_mode:8;
 413       uint8_t vertices_per_patch;
 414
 415       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 416       bool depth_writes_enabled;
 417
 418       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 419       bool stencil_writes_enabled;
 420
 421       /** GenX-specific current state */
 422       struct iris_genx_state *genx;
 423
 424       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 425
 426       /** Do any samplers (for any stage) need border color? */
 427       bool need_border_colors;
 428
 429       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 430       bool streamout_active;
 431
 432       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 433       bool prims_generated_query_active;
 434
 435       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 436       uint32_t *streamout;
 437
 438       /** The SURFACE_STATE for a 1x1x1 null surface. */
 439       struct iris_state_ref unbound_tex;
 440
 441       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 442       struct iris_state_ref null_fb;
 443
 444       struct u_upload_mgr *surface_uploader;
 445       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 446       // "I'm streaming this out at draw time and never want it again!"
 447       struct u_upload_mgr *dynamic_uploader;
 448
 449       struct iris_binder binder;
 450
 451       struct iris_border_color_pool border_color_pool;
 452
 453       /**
 454        * Resources containing streamed state which our render context
 455        * currently points to.  Used to re-add these to the validation
 456        * list when we start a new batch and haven't resubmitted commands.
 457        */
 458       struct {
 459          struct pipe_resource *cc_vp;
 460          struct pipe_resource *sf_cl_vp;
 461          struct pipe_resource *color_calc;
 462          struct pipe_resource *scissor;
 463          struct pipe_resource *blend;
 464          struct pipe_resource *index_buffer;
 465       } last_res;
 466    } state;
 467 };
 468
 469 #define perf_debug(dbg, ...) do {                      \
 470    if (INTEL_DEBUG & DEBUG_PERF)                       \
 471       dbg_printf(__VA_ARGS__);                         \
 472    if (unlikely(dbg))                                  \
 473       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 474 } while(0)
 475
 476 double get_time(void);
 477
 478 struct pipe_context *
 479 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 480
 481 void iris_init_blit_functions(struct pipe_context *ctx);
 482 void iris_init_clear_functions(struct pipe_context *ctx);
 483 void iris_init_program_functions(struct pipe_context *ctx);
 484 void iris_init_resource_functions(struct pipe_context *ctx);
 485 void iris_init_query_functions(struct pipe_context *ctx);
 486 void iris_update_compiled_shaders(struct iris_context *ice);
 487 void iris_update_compiled_compute_shader(struct iris_context *ice);
 488
 489
 490 /* iris_blit.c */
 491 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 492                                   struct pipe_resource *p_res,
 493                                   enum isl_aux_usage aux_usage,
 494                                   bool is_render_target);
 495
 496 /* iris_draw.c */
 497
 498 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 499 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 500
 501 /* iris_pipe_control.c */
 502
 503 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 504                                   uint32_t flags);
 505 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 506                                   struct iris_bo *bo, uint32_t offset,
 507                                   uint64_t imm);
 508 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 509                                 uint32_t flags);
 510
 511 void iris_init_flush_functions(struct pipe_context *ctx);
 512
 513 /* iris_blorp.c */
 514
 515 void gen9_init_blorp(struct iris_context *ice);
 516 void gen10_init_blorp(struct iris_context *ice);
 517 void gen11_init_blorp(struct iris_context *ice);
 518
 519 /* iris_border_color.c */
 520
 521 void iris_init_border_color_pool(struct iris_context *ice);
 522 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 523 uint32_t iris_upload_border_color(struct iris_context *ice,
 524                                   union pipe_color_union *color);
 525
 526 /* iris_state.c */
 527
 528 void gen9_init_state(struct iris_context *ice);
 529 void gen10_init_state(struct iris_context *ice);
 530 void gen11_init_state(struct iris_context *ice);
 531
 532 /* iris_program.c */
 533 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 534                                                gl_shader_stage stage);
 535 unsigned iris_get_shader_num_ubos(const struct iris_context *ice,
 536                                   gl_shader_stage stage);
 537
 538
 539 /* iris_program_cache.c */
 540
 541 void iris_init_program_cache(struct iris_context *ice);
 542 void iris_destroy_program_cache(struct iris_context *ice);
 543 void iris_print_program_cache(struct iris_context *ice);
 544 bool iris_bind_cached_shader(struct iris_context *ice,
 545                              enum iris_program_cache_id cache_id,
 546                              const void *key);
 547 void iris_unbind_shader(struct iris_context *ice,
 548                         enum iris_program_cache_id cache_id);
 549 void iris_upload_and_bind_shader(struct iris_context *ice,
 550                                  enum iris_program_cache_id cache_id,
 551                                  const void *key,
 552                                  const void *assembly,
 553                                  struct brw_stage_prog_data *prog_data,
 554                                  uint32_t *streamout);
 555 const void *iris_find_previous_compile(const struct iris_context *ice,
 556                                        enum iris_program_cache_id cache_id,
 557                                        unsigned program_string_id);
 558 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 559                               const void *key,
 560                               uint32_t key_size,
 561                               uint32_t *kernel_out,
 562                               void *prog_data_out);
 563 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 564                               const void *key, uint32_t key_size,
 565                               const void *kernel, uint32_t kernel_size,
 566                               const struct brw_stage_prog_data *prog_data,
 567                               uint32_t prog_data_size,
 568                               uint32_t *kernel_out,
 569                               void *prog_data_out);
 570
 571 /* iris_query.c */
 572
 573 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 574                              uint64_t gpu_timestamp);
 575
 576 /* iris_resolve.c */
 577
 578 void iris_predraw_resolve_inputs(struct iris_context *ice,
 579                                  struct iris_batch *batch);
 580 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 581                                       struct iris_batch *batch);
 582 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 583                                            struct iris_batch *batch);
 584 void iris_cache_sets_clear(struct iris_batch *batch);
 585 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 586 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 587 void iris_cache_flush_for_render(struct iris_batch *batch,
 588                                  struct iris_bo *bo,
 589                                  enum isl_format format,
 590                                  enum isl_aux_usage aux_usage);
 591 void iris_render_cache_add_bo(struct iris_batch *batch,
 592                               struct iris_bo *bo,
 593                               enum isl_format format,
 594                               enum isl_aux_usage aux_usage);
 595 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 596 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 597
 598 #endif