src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49 #define IRIS_MAX_CLIP_PLANES 8
  50
  51 enum iris_param_domain {
  52    BRW_PARAM_DOMAIN_BUILTIN = 0,
  53    BRW_PARAM_DOMAIN_IMAGE,
  54 };
  55
  56 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  57 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  58 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  59 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  60 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  61 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  62
  63 /**
  64  * Dirty flags.  When state changes, we flag some combination of these
  65  * to indicate that particular GPU commands need to be re-emitted.
  66  *
  67  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  68  * in rare cases they map to a group of related packets that need to be
  69  * emitted together.
  70  *
  71  * See iris_upload_render_state().
  72  */
  73 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  74 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  75 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  76 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  77 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  78 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  79 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  80 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  81 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  82 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  83 #define IRIS_DIRTY_SBE                      (1ull << 10)
  84 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  85 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  86 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  87 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  88 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  89 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  90 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  91 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  92 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  93 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  94 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  95 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  96 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  97 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  98 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  99 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 100 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 101 #define IRIS_DIRTY_VS                       (1ull << 28)
 102 #define IRIS_DIRTY_TCS                      (1ull << 29)
 103 #define IRIS_DIRTY_TES                      (1ull << 30)
 104 #define IRIS_DIRTY_GS                       (1ull << 31)
 105 #define IRIS_DIRTY_FS                       (1ull << 32)
 106 #define IRIS_DIRTY_CS                       (1ull << 33)
 107 #define IRIS_DIRTY_URB                      (1ull << 34)
 108 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 109 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 110 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 111 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 112 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 113 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 114 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 115 #define IRIS_DIRTY_WM                       (1ull << 42)
 116 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 117 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 118 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 119 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 120 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 121 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 122 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 123 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 124 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 125 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 126 #define IRIS_DIRTY_VF                       (1ull << 53)
 127 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 128 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 129 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 130
 131 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 132                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 133                                     IRIS_DIRTY_UNCOMPILED_CS | \
 134                                     IRIS_DIRTY_CONSTANTS_CS | \
 135                                     IRIS_DIRTY_BINDINGS_CS | \
 136                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 137
 138 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 139
 140 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 141                                  IRIS_DIRTY_BINDINGS_TCS | \
 142                                  IRIS_DIRTY_BINDINGS_TES | \
 143                                  IRIS_DIRTY_BINDINGS_GS  | \
 144                                  IRIS_DIRTY_BINDINGS_FS  | \
 145                                  IRIS_DIRTY_BINDINGS_CS)
 146
 147 /**
 148  * Non-orthogonal state (NOS) dependency flags.
 149  *
 150  * Shader programs may depend on non-orthogonal state.  These flags are
 151  * used to indicate that a shader's key depends on the state provided by
 152  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 153  * cause the driver to re-compute the shader key, possibly triggering a
 154  * shader recompile.
 155  */
 156 enum iris_nos_dep {
 157    IRIS_NOS_FRAMEBUFFER,
 158    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 159    IRIS_NOS_RASTERIZER,
 160    IRIS_NOS_BLEND,
 161    IRIS_NOS_LAST_VUE_MAP,
 162
 163    IRIS_NOS_COUNT,
 164 };
 165
 166 struct iris_depth_stencil_alpha_state;
 167
 168 /**
 169  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 170  */
 171 enum iris_program_cache_id {
 172    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 173    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 174    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 175    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 176    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 177    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 178    IRIS_CACHE_BLORP,
 179 };
 180
 181 /** @{
 182  *
 183  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 184  * synchronization, pipelined memory writes, and so on.
 185  *
 186  * The bits here are not the actual hardware values.  The actual fields
 187  * move between various generations, so we just have flags for each
 188  * potential operation, and use genxml to encode the actual packet.
 189  */
 190 enum pipe_control_flags
 191 {
 192    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 193    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 194    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 195    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 196    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 197    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 198    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 199    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 200    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 201    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 202    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 203    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 204    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 205    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 206    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 207    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 208    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 209    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 210    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 211    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 212    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 213    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 214    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 215    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 216 };
 217
 218 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 219    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 220     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 221     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 222
 223 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 224    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 225     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 226     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 227     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 228     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 229
 230 enum iris_predicate_state {
 231    /* The first two states are used if we can determine whether to draw
 232     * without having to look at the values in the query object buffer. This
 233     * will happen if there is no conditional render in progress, if the query
 234     * object is already completed or if something else has already added
 235     * samples to the preliminary result.
 236     */
 237    IRIS_PREDICATE_STATE_RENDER,
 238    IRIS_PREDICATE_STATE_DONT_RENDER,
 239
 240    /* In this case whether to draw or not depends on the result of an
 241     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 242     */
 243    IRIS_PREDICATE_STATE_USE_BIT,
 244 };
 245
 246 /** @} */
 247
 248 /**
 249  * A compiled shader variant, containing a pointer to the GPU assembly,
 250  * as well as program data and other packets needed by state upload.
 251  *
 252  * There can be several iris_compiled_shader variants per API-level shader
 253  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 254  */
 255 struct iris_compiled_shader {
 256    /** Reference to the uploaded assembly. */
 257    struct iris_state_ref assembly;
 258
 259    /** Pointer to the assembly in the BO's map. */
 260    void *map;
 261
 262    /** The program data (owned by the program cache hash table) */
 263    struct brw_stage_prog_data *prog_data;
 264
 265    /** A list of system values to be uploaded as uniforms. */
 266    enum brw_param_builtin *system_values;
 267    unsigned num_system_values;
 268
 269    /** Number of constbufs expected by the shader. */
 270    unsigned num_cbufs;
 271
 272    /**
 273     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 274     * (the VUE-based information for transform feedback outputs).
 275     */
 276    uint32_t *streamout;
 277
 278    /**
 279     * Shader packets and other data derived from prog_data.  These must be
 280     * completely determined from prog_data.
 281     */
 282    uint8_t derived_data[0];
 283 };
 284
 285 /**
 286  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 287  */
 288 struct iris_const_buffer {
 289    /** The resource and offset for the actual constant data */
 290    struct iris_state_ref data;
 291
 292    /** The resource and offset for the SURFACE_STATE for pull access. */
 293    struct iris_state_ref surface_state;
 294 };
 295
 296 /**
 297  * API context state that is replicated per shader stage.
 298  */
 299 struct iris_shader_state {
 300    /** Uniform Buffers */
 301    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 302
 303    struct pipe_constant_buffer cbuf0;
 304    bool cbuf0_needs_upload;
 305
 306    /** Shader Storage Buffers */
 307    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 308    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 309
 310    /** Shader Storage Images (image load store) */
 311    struct {
 312       struct pipe_resource *res;
 313       struct iris_state_ref surface_state;
 314       unsigned access;
 315
 316       /** Gen8-only uniform data for image lowering */
 317       struct brw_image_param param;
 318    } image[PIPE_MAX_SHADER_IMAGES];
 319
 320    struct iris_state_ref sampler_table;
 321    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 322    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 323
 324    /** Bitfield of which image views are bound (non-null). */
 325    uint32_t bound_image_views;
 326
 327    /** Bitfield of which sampler views are bound (non-null). */
 328    uint32_t bound_sampler_views;
 329 };
 330
 331 /**
 332  * Gallium CSO for stream output (transform feedback) targets.
 333  */
 334 struct iris_stream_output_target {
 335    struct pipe_stream_output_target base;
 336
 337    /** Storage holding the offset where we're writing in the buffer */
 338    struct iris_state_ref offset;
 339
 340    /** Stride (dwords-per-vertex) during this transform feedback operation */
 341    uint16_t stride;
 342 };
 343
 344 /**
 345  * Virtual table for generation-specific (genxml) function calls.
 346  */
 347 struct iris_vtable {
 348    void (*destroy_state)(struct iris_context *ice);
 349    void (*init_render_context)(struct iris_screen *screen,
 350                                struct iris_batch *batch,
 351                                struct iris_vtable *vtbl,
 352                                struct pipe_debug_callback *dbg);
 353    void (*init_compute_context)(struct iris_screen *screen,
 354                                 struct iris_batch *batch,
 355                                 struct iris_vtable *vtbl,
 356                                 struct pipe_debug_callback *dbg);
 357    void (*upload_render_state)(struct iris_context *ice,
 358                                struct iris_batch *batch,
 359                                const struct pipe_draw_info *draw);
 360    void (*update_surface_base_address)(struct iris_batch *batch,
 361                                        struct iris_binder *binder);
 362    void (*upload_compute_state)(struct iris_context *ice,
 363                                 struct iris_batch *batch,
 364                                 const struct pipe_grid_info *grid);
 365    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 366                                uint32_t src);
 367    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 368                                uint32_t src);
 369    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 370                                uint32_t val);
 371    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 372                                uint64_t val);
 373    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 374                                struct iris_bo *bo, uint32_t offset);
 375    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 376                                struct iris_bo *bo, uint32_t offset);
 377    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 378                                 struct iris_bo *bo, uint32_t offset,
 379                                 bool predicated);
 380    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 381                                 struct iris_bo *bo, uint32_t offset,
 382                                 bool predicated);
 383    void (*store_data_imm32)(struct iris_batch *batch,
 384                             struct iris_bo *bo, uint32_t offset,
 385                             uint32_t value);
 386    void (*store_data_imm64)(struct iris_batch *batch,
 387                             struct iris_bo *bo, uint32_t offset,
 388                             uint64_t value);
 389    void (*copy_mem_mem)(struct iris_batch *batch,
 390                         struct iris_bo *dst_bo, uint32_t dst_offset,
 391                         struct iris_bo *src_bo, uint32_t src_offset,
 392                         unsigned bytes);
 393    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 394                                  struct iris_bo *bo, uint32_t offset,
 395                                  uint64_t imm);
 396
 397    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 398    void (*store_derived_program_state)(struct iris_context *ice,
 399                                        enum iris_program_cache_id cache_id,
 400                                        struct iris_compiled_shader *shader);
 401    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 402                                     const struct brw_vue_map *vue_map);
 403    void (*populate_vs_key)(const struct iris_context *ice,
 404                            const struct shader_info *info,
 405                            struct brw_vs_prog_key *key);
 406    void (*populate_tcs_key)(const struct iris_context *ice,
 407                             struct brw_tcs_prog_key *key);
 408    void (*populate_tes_key)(const struct iris_context *ice,
 409                             struct brw_tes_prog_key *key);
 410    void (*populate_gs_key)(const struct iris_context *ice,
 411                            struct brw_gs_prog_key *key);
 412    void (*populate_fs_key)(const struct iris_context *ice,
 413                            struct brw_wm_prog_key *key);
 414    void (*populate_cs_key)(const struct iris_context *ice,
 415                            struct brw_cs_prog_key *key);
 416    uint32_t (*mocs)(const struct iris_bo *bo);
 417 };
 418
 419 /**
 420  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 421  *
 422  * See iris_border_color.c for more information.
 423  */
 424 struct iris_border_color_pool {
 425    struct iris_bo *bo;
 426    void *map;
 427    unsigned insert_point;
 428
 429    /** Map from border colors to offsets in the buffer. */
 430    struct hash_table *ht;
 431 };
 432
 433 /**
 434  * The API context (derived from pipe_context).
 435  *
 436  * Most driver state is tracked here.
 437  */
 438 struct iris_context {
 439    struct pipe_context ctx;
 440
 441    /** A debug callback for KHR_debug output. */
 442    struct pipe_debug_callback dbg;
 443
 444    /** Slab allocator for iris_transfer_map objects. */
 445    struct slab_child_pool transfer_pool;
 446
 447    struct iris_vtable vtbl;
 448
 449    struct blorp_context blorp;
 450
 451    struct iris_batch batches[IRIS_BATCH_COUNT];
 452
 453    struct u_upload_mgr *query_buffer_uploader;
 454
 455    struct {
 456       struct {
 457          /**
 458           * Either the value of BaseVertex for indexed draw calls or the value
 459           * of the argument <first> for non-indexed draw calls.
 460           */
 461          int firstvertex;
 462          int baseinstance;
 463       } params;
 464
 465       /**
 466        * Resource and offset that stores draw_parameters from the indirect
 467        * buffer or to the buffer that stures the previous values for non
 468        * indirect draws.
 469        */
 470       struct pipe_resource *draw_params_res;
 471       uint32_t draw_params_offset;
 472
 473       struct {
 474          /**
 475           * The value of DrawID. This always comes in from it's own vertex
 476           * buffer since it's not part of the indirect draw parameters.
 477           */
 478          int drawid;
 479
 480          /**
 481           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 482           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 483           */
 484          int is_indexed_draw;
 485       } derived_params;
 486
 487       /**
 488        * Resource and offset used for GL_ARB_shader_draw_parameters which
 489        * contains parameters that are not present in the indirect buffer as
 490        * drawid and is_indexed_draw. They will go in their own vertex element.
 491        */
 492       struct pipe_resource *derived_draw_params_res;
 493       uint32_t derived_draw_params_offset;
 494
 495       bool is_indirect;
 496    } draw;
 497
 498    struct {
 499       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 500       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 501       struct brw_vue_map *last_vue_map;
 502
 503       struct u_upload_mgr *uploader;
 504       struct hash_table *cache;
 505
 506       unsigned urb_size;
 507
 508       /* Track last VS URB entry size */
 509       unsigned last_vs_entry_size;
 510
 511       /**
 512        * Scratch buffers for various sizes and stages.
 513        *
 514        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 515        * and shader stage.
 516        */
 517       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 518    } shaders;
 519
 520    struct {
 521       struct iris_query *query;
 522       bool condition;
 523    } condition;
 524
 525    struct {
 526       uint64_t dirty;
 527       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 528
 529       unsigned num_viewports;
 530       unsigned sample_mask;
 531       struct iris_blend_state *cso_blend;
 532       struct iris_rasterizer_state *cso_rast;
 533       struct iris_depth_stencil_alpha_state *cso_zsa;
 534       struct iris_vertex_element_state *cso_vertex_elements;
 535       struct pipe_blend_color blend_color;
 536       struct pipe_poly_stipple poly_stipple;
 537       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 538       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 539       struct pipe_stencil_ref stencil_ref;
 540       struct pipe_framebuffer_state framebuffer;
 541       struct pipe_clip_state clip_planes;
 542
 543       float default_outer_level[4];
 544       float default_inner_level[2];
 545
 546       /** Bitfield of which vertex buffers are bound (non-null). */
 547       uint64_t bound_vertex_buffers;
 548
 549       bool primitive_restart;
 550       unsigned cut_index;
 551       enum pipe_prim_type prim_mode:8;
 552       uint8_t vertices_per_patch;
 553
 554       /** The last compute grid size */
 555       uint32_t last_grid[3];
 556       /** Reference to the BO containing the compute grid size */
 557       struct iris_state_ref grid_size;
 558       /** Reference to the SURFACE_STATE for the compute grid resource */
 559       struct iris_state_ref grid_surf_state;
 560
 561       /**
 562        * Array of aux usages for drawing, altered to account for any
 563        * self-dependencies from resources bound for sampling and rendering.
 564        */
 565       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 566
 567       /** Bitfield of whether color blending is enabled for RT[i] */
 568       uint8_t blend_enables;
 569
 570       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 571       bool depth_writes_enabled;
 572
 573       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 574       bool stencil_writes_enabled;
 575
 576       /** GenX-specific current state */
 577       struct iris_genx_state *genx;
 578
 579       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 580
 581       /** Do vertex shader uses shader draw parameters ? */
 582       bool vs_uses_draw_params;
 583       bool vs_uses_derived_draw_params;
 584       bool vs_needs_sgvs_element;
 585
 586       /** Do vertex shader uses edge flag ? */
 587       bool vs_needs_edge_flag;
 588
 589       /** Do any samplers need border color?  One bit per shader stage. */
 590       uint8_t need_border_colors;
 591
 592       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 593       bool streamout_active;
 594
 595       bool statistics_counters_enabled;
 596
 597       /** Current conditional rendering mode */
 598       enum iris_predicate_state predicate;
 599
 600       /**
 601        * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
 602        * render context that needs to be uploaded to the compute context.
 603        */
 604       struct iris_bo *compute_predicate;
 605
 606       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 607       bool prims_generated_query_active;
 608
 609       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 610       uint32_t *streamout;
 611
 612       /** Current strides for each streamout buffer */
 613       uint16_t *streamout_strides;
 614
 615       /** The SURFACE_STATE for a 1x1x1 null surface. */
 616       struct iris_state_ref unbound_tex;
 617
 618       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 619       struct iris_state_ref null_fb;
 620
 621       struct u_upload_mgr *surface_uploader;
 622       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 623       // "I'm streaming this out at draw time and never want it again!"
 624       struct u_upload_mgr *dynamic_uploader;
 625
 626       struct iris_binder binder;
 627
 628       struct iris_border_color_pool border_color_pool;
 629
 630       /** The high 16-bits of the last VBO/index buffer addresses */
 631       uint16_t last_vbo_high_bits[33];
 632       uint16_t last_index_bo_high_bits;
 633
 634       /**
 635        * Resources containing streamed state which our render context
 636        * currently points to.  Used to re-add these to the validation
 637        * list when we start a new batch and haven't resubmitted commands.
 638        */
 639       struct {
 640          struct pipe_resource *cc_vp;
 641          struct pipe_resource *sf_cl_vp;
 642          struct pipe_resource *color_calc;
 643          struct pipe_resource *scissor;
 644          struct pipe_resource *blend;
 645          struct pipe_resource *index_buffer;
 646       } last_res;
 647    } state;
 648 };
 649
 650 #define perf_debug(dbg, ...) do {                      \
 651    if (INTEL_DEBUG & DEBUG_PERF)                       \
 652       dbg_printf(__VA_ARGS__);                         \
 653    if (unlikely(dbg))                                  \
 654       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 655 } while(0)
 656
 657 double get_time(void);
 658
 659 struct pipe_context *
 660 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 661
 662 void iris_init_blit_functions(struct pipe_context *ctx);
 663 void iris_init_clear_functions(struct pipe_context *ctx);
 664 void iris_init_program_functions(struct pipe_context *ctx);
 665 void iris_init_resource_functions(struct pipe_context *ctx);
 666 void iris_init_query_functions(struct pipe_context *ctx);
 667 void iris_update_compiled_shaders(struct iris_context *ice);
 668 void iris_update_compiled_compute_shader(struct iris_context *ice);
 669 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 670                                     uint32_t *dst);
 671
 672
 673 /* iris_blit.c */
 674 void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
 675                                   struct blorp_surf *surf,
 676                                   struct pipe_resource *p_res,
 677                                   enum isl_aux_usage aux_usage,
 678                                   unsigned level,
 679                                   bool is_render_target);
 680 void iris_copy_region(struct blorp_context *blorp,
 681                       struct iris_batch *batch,
 682                       struct pipe_resource *dst,
 683                       unsigned dst_level,
 684                       unsigned dstx, unsigned dsty, unsigned dstz,
 685                       struct pipe_resource *src,
 686                       unsigned src_level,
 687                       const struct pipe_box *src_box);
 688
 689 /* iris_draw.c */
 690
 691 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 692 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 693
 694 /* iris_pipe_control.c */
 695
 696 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 697                                   uint32_t flags);
 698 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 699                                   struct iris_bo *bo, uint32_t offset,
 700                                   uint64_t imm);
 701 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 702                                 uint32_t flags);
 703
 704 void iris_init_flush_functions(struct pipe_context *ctx);
 705
 706 /* iris_blorp.c */
 707 void gen8_init_blorp(struct iris_context *ice);
 708 void gen9_init_blorp(struct iris_context *ice);
 709 void gen10_init_blorp(struct iris_context *ice);
 710 void gen11_init_blorp(struct iris_context *ice);
 711
 712 /* iris_border_color.c */
 713
 714 void iris_init_border_color_pool(struct iris_context *ice);
 715 void iris_destroy_border_color_pool(struct iris_context *ice);
 716 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 717 uint32_t iris_upload_border_color(struct iris_context *ice,
 718                                   union pipe_color_union *color);
 719
 720 /* iris_state.c */
 721 void gen8_init_state(struct iris_context *ice);
 722 void gen9_init_state(struct iris_context *ice);
 723 void gen10_init_state(struct iris_context *ice);
 724 void gen11_init_state(struct iris_context *ice);
 725 void gen8_emit_urb_setup(struct iris_context *ice,
 726                           struct iris_batch *batch,
 727                           const unsigned size[4],
 728                           bool tess_present, bool gs_present);
 729 void gen9_emit_urb_setup(struct iris_context *ice,
 730                           struct iris_batch *batch,
 731                           const unsigned size[4],
 732                           bool tess_present, bool gs_present);
 733 void gen10_emit_urb_setup(struct iris_context *ice,
 734                           struct iris_batch *batch,
 735                           const unsigned size[4],
 736                           bool tess_present, bool gs_present);
 737 void gen11_emit_urb_setup(struct iris_context *ice,
 738                           struct iris_batch *batch,
 739                           const unsigned size[4],
 740                           bool tess_present, bool gs_present);
 741
 742 /* iris_program.c */
 743 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 744                                                gl_shader_stage stage);
 745 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 746                                        unsigned per_thread_scratch,
 747                                        gl_shader_stage stage);
 748
 749 /* iris_program_cache.c */
 750
 751 void iris_init_program_cache(struct iris_context *ice);
 752 void iris_destroy_program_cache(struct iris_context *ice);
 753 void iris_print_program_cache(struct iris_context *ice);
 754 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 755                                                      enum iris_program_cache_id,
 756                                                      uint32_t key_size,
 757                                                      const void *key);
 758 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 759                                                 enum iris_program_cache_id,
 760                                                 uint32_t key_size,
 761                                                 const void *key,
 762                                                 const void *assembly,
 763                                                 struct brw_stage_prog_data *,
 764                                                 uint32_t *streamout,
 765                                                 enum brw_param_builtin *sysv,
 766                                                 unsigned num_system_values,
 767                                                 unsigned num_cbufs);
 768 const void *iris_find_previous_compile(const struct iris_context *ice,
 769                                        enum iris_program_cache_id cache_id,
 770                                        unsigned program_string_id);
 771 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 772                               const void *key,
 773                               uint32_t key_size,
 774                               uint32_t *kernel_out,
 775                               void *prog_data_out);
 776 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 777                               const void *key, uint32_t key_size,
 778                               const void *kernel, uint32_t kernel_size,
 779                               const struct brw_stage_prog_data *prog_data,
 780                               uint32_t prog_data_size,
 781                               uint32_t *kernel_out,
 782                               void *prog_data_out);
 783
 784 /* iris_query.c */
 785
 786 void iris_math_div32_gpr0(struct iris_context *ice,
 787                           struct iris_batch *batch,
 788                           uint32_t D);
 789
 790 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 791                              uint64_t gpu_timestamp);
 792 void iris_resolve_conditional_render(struct iris_context *ice);
 793
 794 /* iris_resolve.c */
 795
 796 void iris_predraw_resolve_inputs(struct iris_context *ice,
 797                                  struct iris_batch *batch,
 798                                  bool *draw_aux_buffer_disabled,
 799                                  gl_shader_stage stage,
 800                                  bool consider_framebuffer);
 801 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 802                                       struct iris_batch *batch,
 803                                       bool *draw_aux_buffer_disabled);
 804 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 805                                            struct iris_batch *batch);
 806 void iris_cache_sets_clear(struct iris_batch *batch);
 807 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 808 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 809 void iris_cache_flush_for_render(struct iris_batch *batch,
 810                                  struct iris_bo *bo,
 811                                  enum isl_format format,
 812                                  enum isl_aux_usage aux_usage);
 813 void iris_render_cache_add_bo(struct iris_batch *batch,
 814                               struct iris_bo *bo,
 815                               enum isl_format format,
 816                               enum isl_aux_usage aux_usage);
 817 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 818 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 819
 820 #endif