src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_screen.h"
  34
  35 struct iris_bo;
  36 struct iris_context;
  37 struct blorp_batch;
  38 struct blorp_params;
  39
  40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  43
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 #define IRIS_MAX_VIEWPORTS 16
  46
  47 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  48 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  49 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  50 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  51 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  52 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  53 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  54 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  55 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  56 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  57 // XXX: define IRIS_DIRTY_                        (1ull << 10)
  58 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  59 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  60 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  61 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  62 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  63 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  64 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  65 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  66 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  67 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  68 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  69 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  70 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  71 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  72 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  73 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  74 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  75 #define IRIS_DIRTY_VS                       (1ull << 28)
  76 #define IRIS_DIRTY_TCS                      (1ull << 29)
  77 #define IRIS_DIRTY_TES                      (1ull << 30)
  78 #define IRIS_DIRTY_GS                       (1ull << 31)
  79 #define IRIS_DIRTY_FS                       (1ull << 32)
  80 #define IRIS_DIRTY_CS                       (1ull << 33)
  81 #define IRIS_DIRTY_URB                      (1ull << 34)
  82 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  83 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  84 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  85 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  86 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  87 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 40)
  88 #define IRIS_DIRTY_WM                       (1ull << 41)
  89 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 42)
  90 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 43)
  91 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 44)
  92 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 45)
  93 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 46)
  94 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 47)
  95
  96 struct iris_depth_stencil_alpha_state;
  97
  98 enum iris_program_cache_id {
  99    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 100    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 101    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 102    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 103    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 104    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 105    IRIS_CACHE_BLORP,
 106 };
 107
 108 /** @{
 109  *
 110  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
 111  * additional flushing control.
 112  *
 113  * The bits here are not the actual hardware values.  The actual values
 114  * shift around a bit per-generation, so we just have flags for each
 115  * potential operation, and use genxml to encode the actual packet.
 116  */
 117 enum pipe_control_flags
 118 {
 119    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 120    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 121    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 122    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 123    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 124    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 125    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 126    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 127    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 128    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 129    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 130    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 131    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 132    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 133    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 134    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 135    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 136    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 137    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 138    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 139    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 140    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 141    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 142    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 143 };
 144
 145 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 146    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 147     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 148     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 149
 150 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 151    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 152     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 153     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 154     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 155     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 156
 157 /** @} */
 158
 159 struct iris_compiled_shader {
 160    /** Buffer containing the uploaded assembly. */
 161    struct pipe_resource *buffer;
 162
 163    /** Pointer to the assembly in the BO's map. */
 164    void *map;
 165
 166    /** The program data (owned by the program cache hash table) */
 167    struct brw_stage_prog_data *prog_data;
 168
 169    /** Offset where the assembly lives in the BO. */
 170    unsigned offset;
 171
 172    /**
 173     * Shader packets and other data derived from prog_data.  These must be
 174     * completely determined from prog_data.
 175     */
 176    uint8_t derived_data[0];
 177 };
 178
 179 struct iris_const_buffer {
 180    /** The resource and offset for the actual constant data */
 181    struct pipe_resource *resource;
 182    unsigned offset;
 183
 184    /** The resource and offset for the SURFACE_STATE for pull access. */
 185    struct pipe_resource *surface_state_resource;
 186    unsigned surface_state_offset;
 187 };
 188
 189 struct iris_shader_state {
 190    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 191 };
 192
 193 struct iris_vtable {
 194    void (*destroy_state)(struct iris_context *ice);
 195    void (*init_render_context)(struct iris_screen *screen,
 196                                struct iris_batch *batch,
 197                                struct iris_vtable *vtbl,
 198                                struct pipe_debug_callback *dbg);
 199    void (*upload_render_state)(struct iris_context *ice,
 200                                struct iris_batch *batch,
 201                                const struct pipe_draw_info *draw);
 202    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 203                                  struct iris_bo *bo, uint32_t offset,
 204                                  uint64_t imm);
 205
 206    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 207    void (*store_derived_program_state)(const struct gen_device_info *devinfo,
 208                                        enum iris_program_cache_id cache_id,
 209                                        struct iris_compiled_shader *shader);
 210    void (*populate_vs_key)(const struct iris_context *ice,
 211                            struct brw_vs_prog_key *key);
 212    void (*populate_tcs_key)(const struct iris_context *ice,
 213                             struct brw_tcs_prog_key *key);
 214    void (*populate_tes_key)(const struct iris_context *ice,
 215                             struct brw_tes_prog_key *key);
 216    void (*populate_gs_key)(const struct iris_context *ice,
 217                            struct brw_gs_prog_key *key);
 218    void (*populate_fs_key)(const struct iris_context *ice,
 219                            struct brw_wm_prog_key *key);
 220 };
 221
 222 struct iris_context {
 223    struct pipe_context ctx;
 224
 225    struct pipe_debug_callback dbg;
 226
 227    struct iris_vtable vtbl;
 228
 229    struct {
 230       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 231       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 232       struct brw_vue_map *last_vue_map;
 233
 234       struct iris_shader_state state[MESA_SHADER_STAGES];
 235
 236       struct u_upload_mgr *uploader;
 237       struct hash_table *cache;
 238
 239       unsigned urb_size;
 240    } shaders;
 241
 242    struct blorp_context blorp;
 243
 244    /** The main batch for rendering */
 245    struct iris_batch render_batch;
 246
 247    struct {
 248       uint64_t dirty;
 249       unsigned num_viewports;
 250       unsigned sample_mask;
 251       struct iris_blend_state *cso_blend;
 252       struct iris_rasterizer_state *cso_rast;
 253       struct iris_depth_stencil_alpha_state *cso_zsa;
 254       struct iris_vertex_element_state *cso_vertex_elements;
 255       struct iris_vertex_buffer_state *cso_vertex_buffers;
 256       struct iris_viewport_state *cso_vp;
 257       struct iris_depth_state *cso_depth;
 258       struct pipe_blend_color blend_color;
 259       struct pipe_poly_stipple poly_stipple;
 260       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 261       struct pipe_stencil_ref stencil_ref;
 262       struct pipe_framebuffer_state framebuffer;
 263       struct iris_depth_buffer_state *cso_depthbuffer;
 264
 265       struct pipe_resource *sampler_table_resource[MESA_SHADER_STAGES];
 266       uint32_t sampler_table_offset[MESA_SHADER_STAGES];
 267       struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 268       struct iris_sampler_view *textures[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 269       unsigned num_samplers[MESA_SHADER_STAGES];
 270       unsigned num_textures[MESA_SHADER_STAGES];
 271
 272       struct u_upload_mgr *surface_uploader;
 273       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 274       // "I'm streaming this out at draw time and never want it again!"
 275       struct u_upload_mgr *dynamic_uploader;
 276
 277       /**
 278        * Resources containing streamed state which our render context
 279        * currently points to.  Used to re-add these to the validation
 280        * list when we start a new batch and haven't resubmitted commands.
 281        */
 282       struct {
 283          struct pipe_resource *cc_vp;
 284          struct pipe_resource *sf_cl_vp;
 285          struct pipe_resource *color_calc;
 286          struct pipe_resource *scissor;
 287          struct pipe_resource *blend;
 288       } last_res;
 289    } state;
 290 };
 291
 292 #define perf_debug(dbg, ...) do {                      \
 293    if (INTEL_DEBUG & DEBUG_PERF)                       \
 294       dbg_printf(__VA_ARGS__);                         \
 295    if (unlikely(dbg))                                  \
 296       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 297 } while(0)
 298
 299 double get_time(void);
 300
 301 struct pipe_context *
 302 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 303
 304 void iris_init_blit_functions(struct pipe_context *ctx);
 305 void iris_init_clear_functions(struct pipe_context *ctx);
 306 void iris_init_program_functions(struct pipe_context *ctx);
 307 void iris_init_resource_functions(struct pipe_context *ctx);
 308 void iris_init_query_functions(struct pipe_context *ctx);
 309 void iris_update_compiled_shaders(struct iris_context *ice);
 310
 311 /* iris_blit.c */
 312 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 313                                   struct pipe_resource *p_res,
 314                                   enum isl_aux_usage aux_usage,
 315                                   bool is_render_target);
 316
 317 /* iris_draw.c */
 318
 319 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 320
 321 /* iris_pipe_control.c */
 322
 323 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 324                                   uint32_t flags);
 325 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 326                                   struct iris_bo *bo, uint32_t offset,
 327                                   uint64_t imm);
 328 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 329                                 uint32_t flags);
 330
 331 void iris_cache_sets_clear(struct iris_batch *batch);
 332 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 333 void iris_cache_flush_for_render(struct iris_batch *batch,
 334                                  struct iris_bo *bo,
 335                                  enum isl_format format,
 336                                  enum isl_aux_usage aux_usage);
 337 void iris_render_cache_add_bo(struct iris_batch *batch,
 338                               struct iris_bo *bo,
 339                               enum isl_format format,
 340                               enum isl_aux_usage aux_usage);
 341 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 342 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 343
 344 /* iris_blorp.c */
 345
 346 void gen9_init_blorp(struct iris_context *ice);
 347 void gen10_init_blorp(struct iris_context *ice);
 348
 349 /* iris_state.c */
 350
 351 void gen9_init_state(struct iris_context *ice);
 352 void gen10_init_state(struct iris_context *ice);
 353
 354 /* iris_program_cache.c */
 355
 356 void iris_init_program_cache(struct iris_context *ice);
 357 void iris_destroy_program_cache(struct iris_context *ice);
 358 void iris_print_program_cache(struct iris_context *ice);
 359 bool iris_bind_cached_shader(struct iris_context *ice,
 360                              enum iris_program_cache_id cache_id,
 361                              const void *key);
 362 void iris_upload_and_bind_shader(struct iris_context *ice,
 363                                  enum iris_program_cache_id cache_id,
 364                                  const void *key,
 365                                  const void *assembly,
 366                                  struct brw_stage_prog_data *prog_data);
 367 const void *iris_find_previous_compile(const struct iris_context *ice,
 368                                        enum iris_program_cache_id cache_id,
 369                                        unsigned program_string_id);
 370 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 371                               const void *key,
 372                               uint32_t key_size,
 373                               uint32_t *kernel_out,
 374                               void *prog_data_out);
 375 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 376                               const void *key, uint32_t key_size,
 377                               const void *kernel, uint32_t kernel_size,
 378                               const struct brw_stage_prog_data *prog_data,
 379                               uint32_t prog_data_size,
 380                               uint32_t *kernel_out,
 381                               void *prog_data_out);
 382
 383 #endif