2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_CONTEXT_H
24 #define IRIS_CONTEXT_H
26 #include "pipe/p_context.h"
27 #include "pipe/p_state.h"
28 #include "util/slab.h"
29 #include "util/u_debug.h"
30 #include "intel/blorp/blorp.h"
31 #include "intel/dev/gen_debug.h"
32 #include "intel/common/gen_l3_config.h"
33 #include "intel/compiler/brw_compiler.h"
34 #include "iris_batch.h"
35 #include "iris_binder.h"
36 #include "iris_fence.h"
37 #include "iris_resource.h"
38 #include "iris_screen.h"
45 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
46 #define IRIS_MAX_TEXTURE_SAMPLERS 32
47 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
48 #define IRIS_MAX_ABOS 16
49 #define IRIS_MAX_SSBOS 16
50 #define IRIS_MAX_VIEWPORTS 16
51 #define IRIS_MAX_CLIP_PLANES 8
53 enum iris_param_domain
{
54 BRW_PARAM_DOMAIN_BUILTIN
= 0,
55 BRW_PARAM_DOMAIN_IMAGE
,
59 DRI_CONF_BO_REUSE_DISABLED
,
63 #define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
64 #define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
65 #define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
66 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
67 #define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
68 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
71 * Dirty flags. When state changes, we flag some combination of these
72 * to indicate that particular GPU commands need to be re-emitted.
74 * Each bit typically corresponds to a single 3DSTATE_* command packet, but
75 * in rare cases they map to a group of related packets that need to be
78 * See iris_upload_render_state().
80 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
81 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
82 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
83 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
84 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
85 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
86 #define IRIS_DIRTY_PS_BLEND (1ull << 6)
87 #define IRIS_DIRTY_BLEND_STATE (1ull << 7)
88 #define IRIS_DIRTY_RASTER (1ull << 8)
89 #define IRIS_DIRTY_CLIP (1ull << 9)
90 #define IRIS_DIRTY_SBE (1ull << 10)
91 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
92 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
93 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
94 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
95 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
96 #define IRIS_DIRTY_URB (1ull << 16)
97 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 17)
98 #define IRIS_DIRTY_WM (1ull << 18)
99 #define IRIS_DIRTY_SO_BUFFERS (1ull << 19)
100 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 20)
101 #define IRIS_DIRTY_STREAMOUT (1ull << 21)
102 #define IRIS_DIRTY_VF_SGVS (1ull << 22)
103 #define IRIS_DIRTY_VF (1ull << 23)
104 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 24)
105 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 25)
106 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 26)
107 #define IRIS_DIRTY_VF_STATISTICS (1ull << 27)
108 #define IRIS_DIRTY_PMA_FIX (1ull << 28)
109 #define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 29)
110 #define IRIS_DIRTY_RENDER_BUFFER (1ull << 30)
111 #define IRIS_DIRTY_STENCIL_REF (1ull << 31)
113 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
115 #define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE)
118 * Per-stage dirty flags. When state changes, we flag some combination of
119 * these to indicate that particular GPU commands need to be re-emitted.
120 * Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be
121 * indexed by shifting the mask by the shader stage index.
123 * See iris_upload_render_state().
125 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS (1ull << 0)
126 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS (1ull << 1)
127 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES (1ull << 2)
128 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS (1ull << 3)
129 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS (1ull << 4)
130 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS (1ull << 5)
131 #define IRIS_STAGE_DIRTY_UNCOMPILED_VS (1ull << 6)
132 #define IRIS_STAGE_DIRTY_UNCOMPILED_TCS (1ull << 7)
133 #define IRIS_STAGE_DIRTY_UNCOMPILED_TES (1ull << 8)
134 #define IRIS_STAGE_DIRTY_UNCOMPILED_GS (1ull << 9)
135 #define IRIS_STAGE_DIRTY_UNCOMPILED_FS (1ull << 10)
136 #define IRIS_STAGE_DIRTY_UNCOMPILED_CS (1ull << 11)
137 #define IRIS_STAGE_DIRTY_VS (1ull << 12)
138 #define IRIS_STAGE_DIRTY_TCS (1ull << 13)
139 #define IRIS_STAGE_DIRTY_TES (1ull << 14)
140 #define IRIS_STAGE_DIRTY_GS (1ull << 15)
141 #define IRIS_STAGE_DIRTY_FS (1ull << 16)
142 #define IRIS_STAGE_DIRTY_CS (1ull << 17)
143 #define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS 18
144 #define IRIS_STAGE_DIRTY_CONSTANTS_VS (1ull << 18)
145 #define IRIS_STAGE_DIRTY_CONSTANTS_TCS (1ull << 19)
146 #define IRIS_STAGE_DIRTY_CONSTANTS_TES (1ull << 20)
147 #define IRIS_STAGE_DIRTY_CONSTANTS_GS (1ull << 21)
148 #define IRIS_STAGE_DIRTY_CONSTANTS_FS (1ull << 22)
149 #define IRIS_STAGE_DIRTY_CONSTANTS_CS (1ull << 23)
150 #define IRIS_STAGE_DIRTY_BINDINGS_VS (1ull << 24)
151 #define IRIS_STAGE_DIRTY_BINDINGS_TCS (1ull << 25)
152 #define IRIS_STAGE_DIRTY_BINDINGS_TES (1ull << 26)
153 #define IRIS_STAGE_DIRTY_BINDINGS_GS (1ull << 27)
154 #define IRIS_STAGE_DIRTY_BINDINGS_FS (1ull << 28)
155 #define IRIS_STAGE_DIRTY_BINDINGS_CS (1ull << 29)
157 #define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \
158 IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \
159 IRIS_STAGE_DIRTY_UNCOMPILED_CS | \
160 IRIS_STAGE_DIRTY_CONSTANTS_CS | \
161 IRIS_STAGE_DIRTY_BINDINGS_CS)
163 #define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE)
165 #define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_STAGE_DIRTY_BINDINGS_VS | \
166 IRIS_STAGE_DIRTY_BINDINGS_TCS | \
167 IRIS_STAGE_DIRTY_BINDINGS_TES | \
168 IRIS_STAGE_DIRTY_BINDINGS_GS | \
169 IRIS_STAGE_DIRTY_BINDINGS_FS | \
170 IRIS_STAGE_DIRTY_BINDINGS_CS)
173 * Non-orthogonal state (NOS) dependency flags.
175 * Shader programs may depend on non-orthogonal state. These flags are
176 * used to indicate that a shader's key depends on the state provided by
177 * a certain Gallium CSO. Changing any CSOs marked as a dependency will
178 * cause the driver to re-compute the shader key, possibly triggering a
182 IRIS_NOS_FRAMEBUFFER
,
183 IRIS_NOS_DEPTH_STENCIL_ALPHA
,
186 IRIS_NOS_LAST_VUE_MAP
,
193 * Program cache keys for state based recompiles.
196 struct iris_base_prog_key
{
197 unsigned program_string_id
;
200 struct iris_vue_prog_key
{
201 struct iris_base_prog_key base
;
203 unsigned nr_userclip_plane_consts
:4;
206 struct iris_vs_prog_key
{
207 struct iris_vue_prog_key vue
;
210 struct iris_tcs_prog_key
{
211 struct iris_vue_prog_key vue
;
213 uint16_t tes_primitive_mode
;
215 uint8_t input_vertices
;
217 bool quads_workaround
;
219 /** A bitfield of per-patch outputs written. */
220 uint32_t patch_outputs_written
;
222 /** A bitfield of per-vertex outputs written. */
223 uint64_t outputs_written
;
226 struct iris_tes_prog_key
{
227 struct iris_vue_prog_key vue
;
229 /** A bitfield of per-patch inputs read. */
230 uint32_t patch_inputs_read
;
232 /** A bitfield of per-vertex inputs read. */
233 uint64_t inputs_read
;
236 struct iris_gs_prog_key
{
237 struct iris_vue_prog_key vue
;
240 struct iris_fs_prog_key
{
241 struct iris_base_prog_key base
;
243 unsigned nr_color_regions
:5;
245 bool alpha_test_replicate_alpha
:1;
246 bool alpha_to_coverage
:1;
247 bool clamp_fragment_color
:1;
248 bool persample_interp
:1;
249 bool multisample_fbo
:1;
250 bool force_dual_color_blend
:1;
251 bool coherent_fb_fetch
:1;
253 uint8_t color_outputs_valid
;
254 uint64_t input_slots_valid
;
257 struct iris_cs_prog_key
{
258 struct iris_base_prog_key base
;
263 struct iris_depth_stencil_alpha_state
;
266 * Cache IDs for the in-memory program cache (ice->shaders.cache).
268 enum iris_program_cache_id
{
269 IRIS_CACHE_VS
= MESA_SHADER_VERTEX
,
270 IRIS_CACHE_TCS
= MESA_SHADER_TESS_CTRL
,
271 IRIS_CACHE_TES
= MESA_SHADER_TESS_EVAL
,
272 IRIS_CACHE_GS
= MESA_SHADER_GEOMETRY
,
273 IRIS_CACHE_FS
= MESA_SHADER_FRAGMENT
,
274 IRIS_CACHE_CS
= MESA_SHADER_COMPUTE
,
280 * Defines for PIPE_CONTROL operations, which trigger cache flushes,
281 * synchronization, pipelined memory writes, and so on.
283 * The bits here are not the actual hardware values. The actual fields
284 * move between various generations, so we just have flags for each
285 * potential operation, and use genxml to encode the actual packet.
287 enum pipe_control_flags
289 PIPE_CONTROL_FLUSH_LLC
= (1 << 1),
290 PIPE_CONTROL_LRI_POST_SYNC_OP
= (1 << 2),
291 PIPE_CONTROL_STORE_DATA_INDEX
= (1 << 3),
292 PIPE_CONTROL_CS_STALL
= (1 << 4),
293 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
= (1 << 5),
294 PIPE_CONTROL_SYNC_GFDT
= (1 << 6),
295 PIPE_CONTROL_TLB_INVALIDATE
= (1 << 7),
296 PIPE_CONTROL_MEDIA_STATE_CLEAR
= (1 << 8),
297 PIPE_CONTROL_WRITE_IMMEDIATE
= (1 << 9),
298 PIPE_CONTROL_WRITE_DEPTH_COUNT
= (1 << 10),
299 PIPE_CONTROL_WRITE_TIMESTAMP
= (1 << 11),
300 PIPE_CONTROL_DEPTH_STALL
= (1 << 12),
301 PIPE_CONTROL_RENDER_TARGET_FLUSH
= (1 << 13),
302 PIPE_CONTROL_INSTRUCTION_INVALIDATE
= (1 << 14),
303 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
= (1 << 15),
304 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
= (1 << 16),
305 PIPE_CONTROL_NOTIFY_ENABLE
= (1 << 17),
306 PIPE_CONTROL_FLUSH_ENABLE
= (1 << 18),
307 PIPE_CONTROL_DATA_CACHE_FLUSH
= (1 << 19),
308 PIPE_CONTROL_VF_CACHE_INVALIDATE
= (1 << 20),
309 PIPE_CONTROL_CONST_CACHE_INVALIDATE
= (1 << 21),
310 PIPE_CONTROL_STATE_CACHE_INVALIDATE
= (1 << 22),
311 PIPE_CONTROL_STALL_AT_SCOREBOARD
= (1 << 23),
312 PIPE_CONTROL_DEPTH_CACHE_FLUSH
= (1 << 24),
313 PIPE_CONTROL_TILE_CACHE_FLUSH
= (1 << 25),
314 PIPE_CONTROL_FLUSH_HDC
= (1 << 26),
317 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
318 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
319 PIPE_CONTROL_DATA_CACHE_FLUSH | \
320 PIPE_CONTROL_RENDER_TARGET_FLUSH)
322 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
323 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
324 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
325 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
326 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
327 PIPE_CONTROL_INSTRUCTION_INVALIDATE)
329 enum iris_predicate_state
{
330 /* The first two states are used if we can determine whether to draw
331 * without having to look at the values in the query object buffer. This
332 * will happen if there is no conditional render in progress, if the query
333 * object is already completed or if something else has already added
334 * samples to the preliminary result.
336 IRIS_PREDICATE_STATE_RENDER
,
337 IRIS_PREDICATE_STATE_DONT_RENDER
,
339 /* In this case whether to draw or not depends on the result of an
340 * MI_PREDICATE command so the predicate enable bit needs to be checked.
342 IRIS_PREDICATE_STATE_USE_BIT
,
348 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
349 * It primarily contains the NIR for the shader.
351 * Each API-facing shader can be compiled into multiple shader variants,
352 * based on non-orthogonal state dependencies, recorded in the shader key.
354 * See iris_compiled_shader, which represents a compiled shader variant.
356 struct iris_uncompiled_shader
{
357 struct nir_shader
*nir
;
359 struct pipe_stream_output_info stream_output
;
361 /* A SHA1 of the serialized NIR for the disk cache. */
362 unsigned char nir_sha1
[20];
366 /** Bitfield of (1 << IRIS_NOS_*) flags. */
369 /** Have any shader variants been compiled yet? */
372 /** Should we use ALT mode for math? Useful for ARB programs. */
375 bool needs_edge_flag
;
377 /* Whether shader uses atomic operations. */
378 bool uses_atomic_load_store
;
380 /** Constant data scraped from the shader by nir_opt_large_constants */
381 struct pipe_resource
*const_data
;
383 /** Surface state for const_data */
384 struct iris_state_ref const_data_state
;
387 enum iris_surface_group
{
388 IRIS_SURFACE_GROUP_RENDER_TARGET
,
389 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
,
390 IRIS_SURFACE_GROUP_CS_WORK_GROUPS
,
391 IRIS_SURFACE_GROUP_TEXTURE
,
392 IRIS_SURFACE_GROUP_IMAGE
,
393 IRIS_SURFACE_GROUP_UBO
,
394 IRIS_SURFACE_GROUP_SSBO
,
396 IRIS_SURFACE_GROUP_COUNT
,
400 /* Invalid value for a binding table index. */
401 IRIS_SURFACE_NOT_USED
= 0xa0a0a0a0,
404 struct iris_binding_table
{
407 /** Number of surfaces in each group, before compacting. */
408 uint32_t sizes
[IRIS_SURFACE_GROUP_COUNT
];
410 /** Initial offset of each group. */
411 uint32_t offsets
[IRIS_SURFACE_GROUP_COUNT
];
413 /** Mask of surfaces used in each group. */
414 uint64_t used_mask
[IRIS_SURFACE_GROUP_COUNT
];
418 * A compiled shader variant, containing a pointer to the GPU assembly,
419 * as well as program data and other packets needed by state upload.
421 * There can be several iris_compiled_shader variants per API-level shader
422 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
424 struct iris_compiled_shader
{
425 /** Reference to the uploaded assembly. */
426 struct iris_state_ref assembly
;
428 /** Pointer to the assembly in the BO's map. */
431 /** The program data (owned by the program cache hash table) */
432 struct brw_stage_prog_data
*prog_data
;
434 /** A list of system values to be uploaded as uniforms. */
435 enum brw_param_builtin
*system_values
;
436 unsigned num_system_values
;
438 /** Number of constbufs expected by the shader. */
442 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
443 * (the VUE-based information for transform feedback outputs).
447 struct iris_binding_table bt
;
450 * Shader packets and other data derived from prog_data. These must be
451 * completely determined from prog_data.
453 uint8_t derived_data
[0];
457 * API context state that is replicated per shader stage.
459 struct iris_shader_state
{
460 /** Uniform Buffers */
461 struct pipe_shader_buffer constbuf
[PIPE_MAX_CONSTANT_BUFFERS
];
462 struct iris_state_ref constbuf_surf_state
[PIPE_MAX_CONSTANT_BUFFERS
];
464 bool sysvals_need_upload
;
466 /** Shader Storage Buffers */
467 struct pipe_shader_buffer ssbo
[PIPE_MAX_SHADER_BUFFERS
];
468 struct iris_state_ref ssbo_surf_state
[PIPE_MAX_SHADER_BUFFERS
];
470 /** Shader Storage Images (image load store) */
471 struct iris_image_view image
[PIPE_MAX_SHADER_IMAGES
];
473 struct iris_state_ref sampler_table
;
474 struct iris_sampler_state
*samplers
[IRIS_MAX_TEXTURE_SAMPLERS
];
475 struct iris_sampler_view
*textures
[IRIS_MAX_TEXTURE_SAMPLERS
];
477 /** Bitfield of which constant buffers are bound (non-null). */
478 uint32_t bound_cbufs
;
480 /** Bitfield of which image views are bound (non-null). */
481 uint32_t bound_image_views
;
483 /** Bitfield of which sampler views are bound (non-null). */
484 uint32_t bound_sampler_views
;
486 /** Bitfield of which shader storage buffers are bound (non-null). */
487 uint32_t bound_ssbos
;
489 /** Bitfield of which shader storage buffers are writable. */
490 uint32_t writable_ssbos
;
494 * Gallium CSO for stream output (transform feedback) targets.
496 struct iris_stream_output_target
{
497 struct pipe_stream_output_target base
;
499 /** Storage holding the offset where we're writing in the buffer */
500 struct iris_state_ref offset
;
502 /** Stride (bytes-per-vertex) during this transform feedback operation */
505 /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
510 * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
512 * See iris_border_color.c for more information.
514 struct iris_border_color_pool
{
517 unsigned insert_point
;
519 /** Map from border colors to offsets in the buffer. */
520 struct hash_table
*ht
;
524 * The API context (derived from pipe_context).
526 * Most driver state is tracked here.
528 struct iris_context
{
529 struct pipe_context ctx
;
531 /** A debug callback for KHR_debug output. */
532 struct pipe_debug_callback dbg
;
534 /** A device reset status callback for notifying that the GPU is hosed. */
535 struct pipe_device_reset_callback reset
;
537 /** Slab allocator for iris_transfer_map objects. */
538 struct slab_child_pool transfer_pool
;
540 struct blorp_context blorp
;
542 struct iris_batch batches
[IRIS_BATCH_COUNT
];
544 struct u_upload_mgr
*query_buffer_uploader
;
549 * Either the value of BaseVertex for indexed draw calls or the value
550 * of the argument <first> for non-indexed draw calls.
557 * Are the above values the ones stored in the draw_params buffer?
558 * If so, we can compare them against new values to see if anything
559 * changed. If not, we need to assume they changed.
564 * Resource and offset that stores draw_parameters from the indirect
565 * buffer or to the buffer that stures the previous values for non
568 struct iris_state_ref draw_params
;
572 * The value of DrawID. This always comes in from it's own vertex
573 * buffer since it's not part of the indirect draw parameters.
578 * Stores if an indexed or non-indexed draw (~0/0). Useful to
579 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
585 * Resource and offset used for GL_ARB_shader_draw_parameters which
586 * contains parameters that are not present in the indirect buffer as
587 * drawid and is_indexed_draw. They will go in their own vertex element.
589 struct iris_state_ref derived_draw_params
;
593 struct iris_uncompiled_shader
*uncompiled
[MESA_SHADER_STAGES
];
594 struct iris_compiled_shader
*prog
[MESA_SHADER_STAGES
];
595 struct brw_vue_map
*last_vue_map
;
597 struct u_upload_mgr
*uploader
;
598 struct hash_table
*cache
;
600 /** Is a GS or TES outputting points or lines? */
601 bool output_topology_is_points_or_lines
;
604 * Scratch buffers for various sizes and stages.
606 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
609 struct iris_bo
*scratch_bos
[1 << 4][MESA_SHADER_STAGES
];
613 struct iris_query
*query
;
617 struct gen_perf_context
*perf_ctx
;
619 /** Frame number for debug prints */
624 uint64_t stage_dirty
;
625 uint64_t stage_dirty_for_nos
[IRIS_NOS_COUNT
];
627 unsigned num_viewports
;
628 unsigned sample_mask
;
629 struct iris_blend_state
*cso_blend
;
630 struct iris_rasterizer_state
*cso_rast
;
631 struct iris_depth_stencil_alpha_state
*cso_zsa
;
632 struct iris_vertex_element_state
*cso_vertex_elements
;
633 struct pipe_blend_color blend_color
;
634 struct pipe_poly_stipple poly_stipple
;
635 struct pipe_viewport_state viewports
[IRIS_MAX_VIEWPORTS
];
636 struct pipe_scissor_state scissors
[IRIS_MAX_VIEWPORTS
];
637 struct pipe_stencil_ref stencil_ref
;
638 struct pipe_framebuffer_state framebuffer
;
639 struct pipe_clip_state clip_planes
;
641 float default_outer_level
[4];
642 float default_inner_level
[2];
644 /** Bitfield of which vertex buffers are bound (non-null). */
645 uint64_t bound_vertex_buffers
;
647 bool primitive_restart
;
649 enum pipe_prim_type prim_mode
:8;
650 bool prim_is_points_or_lines
;
651 uint8_t vertices_per_patch
;
653 bool window_space_position
;
655 /** The last compute group size */
656 uint32_t last_block
[3];
658 /** The last compute grid size */
659 uint32_t last_grid
[3];
660 /** Reference to the BO containing the compute grid size */
661 struct iris_state_ref grid_size
;
662 /** Reference to the SURFACE_STATE for the compute grid resource */
663 struct iris_state_ref grid_surf_state
;
666 * Array of aux usages for drawing, altered to account for any
667 * self-dependencies from resources bound for sampling and rendering.
669 enum isl_aux_usage draw_aux_usage
[BRW_MAX_DRAW_BUFFERS
];
671 enum gen_urb_deref_block_size urb_deref_block_size
;
673 /** Bitfield of whether color blending is enabled for RT[i] */
674 uint8_t blend_enables
;
676 /** Are depth writes enabled? (Depth buffer may or may not exist.) */
677 bool depth_writes_enabled
;
679 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */
680 bool stencil_writes_enabled
;
682 /** GenX-specific current state */
683 struct iris_genx_state
*genx
;
685 struct iris_shader_state shaders
[MESA_SHADER_STAGES
];
687 /** Do vertex shader uses shader draw parameters ? */
688 bool vs_uses_draw_params
;
689 bool vs_uses_derived_draw_params
;
690 bool vs_needs_sgvs_element
;
692 /** Do vertex shader uses edge flag ? */
693 bool vs_needs_edge_flag
;
695 /** Do any samplers need border color? One bit per shader stage. */
696 uint8_t need_border_colors
;
698 struct pipe_stream_output_target
*so_target
[PIPE_MAX_SO_BUFFERS
];
699 bool streamout_active
;
701 bool statistics_counters_enabled
;
703 /** Current conditional rendering mode */
704 enum iris_predicate_state predicate
;
707 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
708 * render context that needs to be uploaded to the compute context.
710 struct iris_bo
*compute_predicate
;
712 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
713 bool prims_generated_query_active
;
715 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
718 /** The SURFACE_STATE for a 1x1x1 null surface. */
719 struct iris_state_ref unbound_tex
;
721 /** The SURFACE_STATE for a framebuffer-sized null surface. */
722 struct iris_state_ref null_fb
;
724 struct u_upload_mgr
*surface_uploader
;
725 struct u_upload_mgr
*dynamic_uploader
;
727 struct iris_binder binder
;
729 struct iris_border_color_pool border_color_pool
;
731 /** The high 16-bits of the last VBO/index buffer addresses */
732 uint16_t last_vbo_high_bits
[33];
733 uint16_t last_index_bo_high_bits
;
736 * Resources containing streamed state which our render context
737 * currently points to. Used to re-add these to the validation
738 * list when we start a new batch and haven't resubmitted commands.
741 struct pipe_resource
*cc_vp
;
742 struct pipe_resource
*sf_cl_vp
;
743 struct pipe_resource
*color_calc
;
744 struct pipe_resource
*scissor
;
745 struct pipe_resource
*blend
;
746 struct pipe_resource
*index_buffer
;
747 struct pipe_resource
*cs_thread_ids
;
748 struct pipe_resource
*cs_desc
;
751 /** Records the size of variable-length state for INTEL_DEBUG=bat */
752 struct hash_table_u64
*sizes
;
754 /** Last rendering scale argument provided to genX(emit_hashing_mode). */
755 unsigned current_hash_scale
;
759 #define perf_debug(dbg, ...) do { \
760 if (INTEL_DEBUG & DEBUG_PERF) \
761 dbg_printf(__VA_ARGS__); \
763 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
766 double get_time(void);
768 struct pipe_context
*
769 iris_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
);
771 void iris_lost_context_state(struct iris_batch
*batch
);
773 void iris_init_blit_functions(struct pipe_context
*ctx
);
774 void iris_init_clear_functions(struct pipe_context
*ctx
);
775 void iris_init_program_functions(struct pipe_context
*ctx
);
776 void iris_init_resource_functions(struct pipe_context
*ctx
);
777 void iris_init_perfquery_functions(struct pipe_context
*ctx
);
778 void iris_update_compiled_shaders(struct iris_context
*ice
);
779 void iris_update_compiled_compute_shader(struct iris_context
*ice
);
780 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
786 void iris_blorp_surf_for_resource(struct isl_device
*isl_dev
,
787 struct blorp_surf
*surf
,
788 struct pipe_resource
*p_res
,
789 enum isl_aux_usage aux_usage
,
791 bool is_render_target
);
792 void iris_copy_region(struct blorp_context
*blorp
,
793 struct iris_batch
*batch
,
794 struct pipe_resource
*dst
,
796 unsigned dstx
, unsigned dsty
, unsigned dstz
,
797 struct pipe_resource
*src
,
799 const struct pipe_box
*src_box
);
803 void iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
804 void iris_launch_grid(struct pipe_context
*, const struct pipe_grid_info
*);
806 /* iris_pipe_control.c */
808 void iris_emit_pipe_control_flush(struct iris_batch
*batch
,
809 const char *reason
, uint32_t flags
);
810 void iris_emit_pipe_control_write(struct iris_batch
*batch
,
811 const char *reason
, uint32_t flags
,
812 struct iris_bo
*bo
, uint32_t offset
,
814 void iris_emit_end_of_pipe_sync(struct iris_batch
*batch
,
815 const char *reason
, uint32_t flags
);
816 void iris_emit_buffer_barrier_for(struct iris_batch
*batch
,
818 enum iris_domain access
);
819 void iris_flush_all_caches(struct iris_batch
*batch
);
821 #define iris_handle_always_flush_cache(batch) \
822 if (unlikely(batch->screen->driconf.always_flush_cache)) \
823 iris_flush_all_caches(batch);
825 void iris_init_flush_functions(struct pipe_context
*ctx
);
827 /* iris_border_color.c */
829 void iris_init_border_color_pool(struct iris_context
*ice
);
830 void iris_destroy_border_color_pool(struct iris_context
*ice
);
831 void iris_border_color_pool_reserve(struct iris_context
*ice
, unsigned count
);
832 uint32_t iris_upload_border_color(struct iris_context
*ice
,
833 union pipe_color_union
*color
);
836 void iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
837 struct pipe_shader_buffer
*buf
,
838 struct iris_state_ref
*surf_state
,
840 const struct shader_info
*iris_get_shader_info(const struct iris_context
*ice
,
841 gl_shader_stage stage
);
842 struct iris_bo
*iris_get_scratch_space(struct iris_context
*ice
,
843 unsigned per_thread_scratch
,
844 gl_shader_stage stage
);
845 uint32_t iris_group_index_to_bti(const struct iris_binding_table
*bt
,
846 enum iris_surface_group group
,
848 uint32_t iris_bti_to_group_index(const struct iris_binding_table
*bt
,
849 enum iris_surface_group group
,
852 /* iris_disk_cache.c */
854 void iris_disk_cache_store(struct disk_cache
*cache
,
855 const struct iris_uncompiled_shader
*ish
,
856 const struct iris_compiled_shader
*shader
,
857 const void *prog_key
,
858 uint32_t prog_key_size
);
859 struct iris_compiled_shader
*
860 iris_disk_cache_retrieve(struct iris_context
*ice
,
861 const struct iris_uncompiled_shader
*ish
,
862 const void *prog_key
,
863 uint32_t prog_key_size
);
865 /* iris_program_cache.c */
867 void iris_init_program_cache(struct iris_context
*ice
);
868 void iris_destroy_program_cache(struct iris_context
*ice
);
869 void iris_print_program_cache(struct iris_context
*ice
);
870 struct iris_compiled_shader
*iris_find_cached_shader(struct iris_context
*ice
,
871 enum iris_program_cache_id
,
874 struct iris_compiled_shader
*iris_upload_shader(struct iris_context
*ice
,
875 enum iris_program_cache_id
,
878 const void *assembly
,
879 struct brw_stage_prog_data
*,
881 enum brw_param_builtin
*sysv
,
882 unsigned num_system_values
,
884 const struct iris_binding_table
*bt
);
885 const void *iris_find_previous_compile(const struct iris_context
*ice
,
886 enum iris_program_cache_id cache_id
,
887 unsigned program_string_id
);
888 bool iris_blorp_lookup_shader(struct blorp_batch
*blorp_batch
,
891 uint32_t *kernel_out
,
892 void *prog_data_out
);
893 bool iris_blorp_upload_shader(struct blorp_batch
*blorp_batch
, uint32_t stage
,
894 const void *key
, uint32_t key_size
,
895 const void *kernel
, uint32_t kernel_size
,
896 const struct brw_stage_prog_data
*prog_data
,
897 uint32_t prog_data_size
,
898 uint32_t *kernel_out
,
899 void *prog_data_out
);
903 void iris_predraw_resolve_inputs(struct iris_context
*ice
,
904 struct iris_batch
*batch
,
905 bool *draw_aux_buffer_disabled
,
906 gl_shader_stage stage
,
907 bool consider_framebuffer
);
908 void iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
909 struct iris_batch
*batch
,
910 bool *draw_aux_buffer_disabled
);
911 void iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
912 struct iris_batch
*batch
);
913 void iris_flush_depth_and_render_caches(struct iris_batch
*batch
);
914 void iris_cache_flush_for_render(struct iris_batch
*batch
,
916 enum isl_format format
,
917 enum isl_aux_usage aux_usage
);
918 int iris_get_driver_query_info(struct pipe_screen
*pscreen
, unsigned index
,
919 struct pipe_driver_query_info
*info
);
920 int iris_get_driver_query_group_info(struct pipe_screen
*pscreen
,
922 struct pipe_driver_query_group_info
*info
);
925 void gen9_toggle_preemption(struct iris_context
*ice
,
926 struct iris_batch
*batch
,
927 const struct pipe_draw_info
*draw
);
932 # include "iris_genx_protos.h"
934 # define genX(x) gen4_##x
935 # include "iris_genx_protos.h"
937 # define genX(x) gen5_##x
938 # include "iris_genx_protos.h"
940 # define genX(x) gen6_##x
941 # include "iris_genx_protos.h"
943 # define genX(x) gen7_##x
944 # include "iris_genx_protos.h"
946 # define genX(x) gen75_##x
947 # include "iris_genx_protos.h"
949 # define genX(x) gen8_##x
950 # include "iris_genx_protos.h"
952 # define genX(x) gen9_##x
953 # include "iris_genx_protos.h"
955 # define genX(x) gen10_##x
956 # include "iris_genx_protos.h"
958 # define genX(x) gen11_##x
959 # include "iris_genx_protos.h"
961 # define genX(x) gen12_##x
962 # include "iris_genx_protos.h"