src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/common/gen_debug.h"
  30 #include "intel/compiler/brw_compiler.h"
  31 #include "iris_batch.h"
  32 #include "iris_binder.h"
  33 #include "iris_screen.h"
  34
  35 struct iris_bo;
  36 struct iris_context;
  37 struct blorp_batch;
  38 struct blorp_params;
  39
  40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  43
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 #define IRIS_MAX_VIEWPORTS 16
  46
  47 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  48 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  49 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  50 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  51 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  52 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  53 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  54 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  55 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  56 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  57 #define IRIS_DIRTY_SCISSOR                  (1ull << 10)
  58 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  59 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  60 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  61 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  62 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  63 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  64 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  65 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  66 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  67 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  68 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  69 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  70 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  71 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  72 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  73 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  74 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  75 #define IRIS_DIRTY_VS                       (1ull << 28)
  76 #define IRIS_DIRTY_TCS                      (1ull << 29)
  77 #define IRIS_DIRTY_TES                      (1ull << 30)
  78 #define IRIS_DIRTY_GS                       (1ull << 31)
  79 #define IRIS_DIRTY_FS                       (1ull << 32)
  80 #define IRIS_DIRTY_CS                       (1ull << 33)
  81 #define IRIS_DIRTY_URB                      (1ull << 34)
  82 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  83 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  84 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  85 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  86 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  87
  88 enum brw_param_domain {
  89    BRW_PARAM_DOMAIN_BUILTIN = 0,
  90    BRW_PARAM_DOMAIN_PARAMETER,
  91    BRW_PARAM_DOMAIN_UNIFORM,
  92    BRW_PARAM_DOMAIN_IMAGE,
  93 };
  94
  95 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  96 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  97 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  98
  99 #define BRW_PARAM_PARAMETER(idx, comp) \
 100    BRW_PARAM(PARAMETER, ((idx) << 2) | (comp))
 101 #define BRW_PARAM_PARAMETER_IDX(param)    (BRW_PARAM_VALUE(param) >> 2)
 102 #define BRW_PARAM_PARAMETER_COMP(param)   (BRW_PARAM_VALUE(param) & 0x3)
 103
 104 #define BRW_PARAM_UNIFORM(idx)            BRW_PARAM(UNIFORM, (idx))
 105 #define BRW_PARAM_UNIFORM_IDX(param)      BRW_PARAM_VALUE(param)
 106
 107 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
 108 #define BRW_PARAM_IMAGE_IDX(value)        (BRW_PARAM_VALUE(value) >> 8)
 109 #define BRW_PARAM_IMAGE_OFFSET(value)     (BRW_PARAM_VALUE(value) & 0xf)
 110
 111 struct iris_depth_stencil_alpha_state;
 112
 113 enum iris_program_cache_id {
 114    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 115    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 116    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 117    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 118    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 119    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 120    IRIS_CACHE_BLORP_BLIT,
 121 };
 122
 123 /** @{
 124  *
 125  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
 126  * additional flushing control.
 127  *
 128  * The bits here are not the actual hardware values.  The actual values
 129  * shift around a bit per-generation, so we just have flags for each
 130  * potential operation, and use genxml to encode the actual packet.
 131  */
 132 enum pipe_control_flags
 133 {
 134    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 135    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 136    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 137    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 138    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 139    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 140    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 141    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 142    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 143    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 144    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 145    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 146    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 147    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 148    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 149    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 150    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 151    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 152    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 153    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 154    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 155    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 156    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 157    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 158 };
 159
 160 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 161    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 162     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 163     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 164
 165 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 166    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 167     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 168     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 169     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 170     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 171
 172 /** @} */
 173
 174 struct iris_compiled_shader {
 175    /** Buffer containing the uploaded assembly. */
 176    struct pipe_resource *buffer;
 177
 178    /** Offset where the assembly lives in the BO. */
 179    unsigned offset;
 180
 181    /** Pointer to the assembly in the BO's map. */
 182    void *map;
 183
 184    /** The program data (owned by the program cache hash table) */
 185    struct brw_stage_prog_data *prog_data;
 186
 187    /**
 188     * Shader packets and other data derived from prog_data.  These must be
 189     * completely determined from prog_data.
 190     */
 191    uint8_t derived_data[0];
 192 };
 193
 194 struct iris_shader_state {
 195    struct pipe_constant_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 196    struct pipe_resource *push_resource;
 197    unsigned const_offset;
 198    unsigned const_size;
 199 };
 200
 201 struct iris_vtable {
 202    void (*destroy_state)(struct iris_context *ice);
 203    void (*init_render_context)(struct iris_screen *screen,
 204                                struct iris_batch *batch,
 205                                struct iris_vtable *vtbl,
 206                                struct pipe_debug_callback *dbg);
 207    void (*upload_render_state)(struct iris_context *ice,
 208                                struct iris_batch *batch,
 209                                const struct pipe_draw_info *draw);
 210    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 211                                  struct iris_bo *bo, uint32_t offset,
 212                                  uint64_t imm);
 213    void (*blorp_exec)(struct blorp_batch *blorp_batch,
 214                       const struct blorp_params *params);
 215
 216    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 217    void (*set_derived_program_state)(const struct gen_device_info *devinfo,
 218                                      enum iris_program_cache_id cache_id,
 219                                      struct iris_compiled_shader *shader);
 220    void (*populate_vs_key)(const struct iris_context *ice,
 221                            struct brw_vs_prog_key *key);
 222    void (*populate_tcs_key)(const struct iris_context *ice,
 223                             struct brw_tcs_prog_key *key);
 224    void (*populate_tes_key)(const struct iris_context *ice,
 225                             struct brw_tes_prog_key *key);
 226    void (*populate_gs_key)(const struct iris_context *ice,
 227                            struct brw_gs_prog_key *key);
 228    void (*populate_fs_key)(const struct iris_context *ice,
 229                            struct brw_wm_prog_key *key);
 230 };
 231
 232 struct iris_context {
 233    struct pipe_context ctx;
 234
 235    struct pipe_debug_callback dbg;
 236
 237    struct iris_vtable vtbl;
 238
 239    struct {
 240       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 241       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 242       struct brw_vue_map *last_vue_map;
 243
 244       struct iris_shader_state state[MESA_SHADER_STAGES];
 245
 246       struct u_upload_mgr *uploader;
 247       struct hash_table *cache;
 248
 249       unsigned urb_size;
 250    } shaders;
 251
 252    /** The main batch for rendering */
 253    struct iris_batch render_batch;
 254
 255    struct {
 256       uint64_t dirty;
 257       unsigned num_viewports; // XXX: can viewports + scissors be different?
 258       unsigned num_scissors;
 259       unsigned sample_mask;
 260       struct iris_blend_state *cso_blend;
 261       struct iris_rasterizer_state *cso_rast;
 262       struct iris_depth_stencil_alpha_state *cso_zsa;
 263       struct iris_vertex_element_state *cso_vertex_elements;
 264       struct iris_vertex_buffer_state *cso_vertex_buffers;
 265       struct iris_viewport_state *cso_vp;
 266       struct iris_depth_state *cso_depth;
 267       struct pipe_blend_color blend_color;
 268       struct pipe_poly_stipple poly_stipple;
 269       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 270       struct pipe_stencil_ref stencil_ref;
 271       struct pipe_framebuffer_state framebuffer;
 272
 273       struct pipe_resource *sampler_table_resource[MESA_SHADER_STAGES];
 274       uint32_t sampler_table_offset[MESA_SHADER_STAGES];
 275       struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 276       struct iris_sampler_view *textures[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
 277       unsigned num_samplers[MESA_SHADER_STAGES];
 278       unsigned num_textures[MESA_SHADER_STAGES];
 279
 280       struct iris_binder binder;
 281       struct u_upload_mgr *surface_uploader;
 282       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 283       // "I'm streaming this out at draw time and never want it again!"
 284       struct u_upload_mgr *dynamic_uploader;
 285
 286    } state;
 287 };
 288
 289 #define perf_debug(dbg, ...) do {                      \
 290    if (INTEL_DEBUG & DEBUG_PERF)                       \
 291       dbg_printf(__VA_ARGS__);                         \
 292    if (unlikely(dbg))                                  \
 293       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 294 } while(0)
 295
 296 double get_time(void);
 297
 298 struct pipe_context *
 299 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 300
 301 void iris_init_blit_functions(struct pipe_context *ctx);
 302 void iris_init_clear_functions(struct pipe_context *ctx);
 303 void iris_init_program_functions(struct pipe_context *ctx);
 304 void iris_init_resource_functions(struct pipe_context *ctx);
 305 void iris_init_query_functions(struct pipe_context *ctx);
 306 void iris_update_compiled_shaders(struct iris_context *ice);
 307
 308 /* iris_draw.c */
 309
 310 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 311
 312 /* iris_pipe_control.c */
 313
 314 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 315                                   uint32_t flags);
 316 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 317                                   struct iris_bo *bo, uint32_t offset,
 318                                   uint64_t imm);
 319 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 320                                 uint32_t flags);
 321
 322 void iris_cache_sets_clear(struct iris_batch *batch);
 323 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 324 void iris_cache_flush_for_render(struct iris_batch *batch,
 325                                  struct iris_bo *bo,
 326                                  enum isl_format format,
 327                                  enum isl_aux_usage aux_usage);
 328 void iris_render_cache_add_bo(struct iris_batch *batch,
 329                               struct iris_bo *bo,
 330                               enum isl_format format,
 331                               enum isl_aux_usage aux_usage);
 332 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 333 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 334
 335 /* iris_blorp.c */
 336
 337 void gen9_init_blorp(struct iris_context *ice);
 338 void gen10_init_blorp(struct iris_context *ice);
 339
 340 /* iris_state.c */
 341
 342 void gen9_init_state(struct iris_context *ice);
 343 void gen10_init_state(struct iris_context *ice);
 344
 345 /* iris_program_cache.c */
 346
 347 void iris_init_program_cache(struct iris_context *ice);
 348 void iris_destroy_program_cache(struct iris_context *ice);
 349 void iris_print_program_cache(struct iris_context *ice);
 350 bool iris_bind_cached_shader(struct iris_context *ice,
 351                              enum iris_program_cache_id cache_id,
 352                              const void *key);
 353 void iris_upload_and_bind_shader(struct iris_context *ice,
 354                                  enum iris_program_cache_id cache_id,
 355                                  const void *key,
 356                                  const void *assembly,
 357                                  struct brw_stage_prog_data *prog_data);
 358 const void *iris_find_previous_compile(const struct iris_context *ice,
 359                                        enum iris_program_cache_id cache_id,
 360                                        unsigned program_string_id);
 361 #endif