src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49
  50 /**
  51  * Dirty flags.  When state changes, we flag some combination of these
  52  * to indicate that particular GPU commands need to be re-emitted.
  53  *
  54  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  55  * in rare cases they map to a group of related packets that need to be
  56  * emitted together.
  57  *
  58  * See iris_upload_render_state().
  59  */
  60 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  61 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  62 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  63 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  64 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  65 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  66 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  67 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  68 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  69 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  70 #define IRIS_DIRTY_SBE                      (1ull << 10)
  71 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  72 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  73 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  74 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  75 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  76 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  77 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  78 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  79 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  80 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  81 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  82 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  83 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  84 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  85 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  86 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  87 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  88 #define IRIS_DIRTY_VS                       (1ull << 28)
  89 #define IRIS_DIRTY_TCS                      (1ull << 29)
  90 #define IRIS_DIRTY_TES                      (1ull << 30)
  91 #define IRIS_DIRTY_GS                       (1ull << 31)
  92 #define IRIS_DIRTY_FS                       (1ull << 32)
  93 #define IRIS_DIRTY_CS                       (1ull << 33)
  94 #define IRIS_DIRTY_URB                      (1ull << 34)
  95 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  96 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  97 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  98 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  99 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 100 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 101 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 102 #define IRIS_DIRTY_WM                       (1ull << 42)
 103 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 104 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 105 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 106 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 107 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 108 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 109 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 110 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 111 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 112 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 113 #define IRIS_DIRTY_VF                       (1ull << 53)
 114 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 115
 116 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 117                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 118                                     IRIS_DIRTY_UNCOMPILED_CS | \
 119                                     IRIS_DIRTY_CONSTANTS_CS | \
 120                                     IRIS_DIRTY_BINDINGS_CS)
 121
 122 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 123
 124 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 125                                  IRIS_DIRTY_BINDINGS_TCS | \
 126                                  IRIS_DIRTY_BINDINGS_TES | \
 127                                  IRIS_DIRTY_BINDINGS_GS  | \
 128                                  IRIS_DIRTY_BINDINGS_FS  | \
 129                                  IRIS_DIRTY_BINDINGS_CS)
 130
 131 /**
 132  * Non-orthogonal state (NOS) dependency flags.
 133  *
 134  * Shader programs may depend on non-orthogonal state.  These flags are
 135  * used to indicate that a shader's key depends on the state provided by
 136  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 137  * cause the driver to re-compute the shader key, possibly triggering a
 138  * shader recompile.
 139  */
 140 enum iris_nos_dep {
 141    IRIS_NOS_FRAMEBUFFER,
 142    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 143    IRIS_NOS_RASTERIZER,
 144    IRIS_NOS_BLEND,
 145    IRIS_NOS_LAST_VUE_MAP,
 146
 147    IRIS_NOS_COUNT,
 148 };
 149
 150 struct iris_depth_stencil_alpha_state;
 151
 152 /**
 153  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 154  */
 155 enum iris_program_cache_id {
 156    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 157    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 158    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 159    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 160    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 161    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 162    IRIS_CACHE_BLORP,
 163 };
 164
 165 /** @{
 166  *
 167  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 168  * synchronization, pipelined memory writes, and so on.
 169  *
 170  * The bits here are not the actual hardware values.  The actual fields
 171  * move between various generations, so we just have flags for each
 172  * potential operation, and use genxml to encode the actual packet.
 173  */
 174 enum pipe_control_flags
 175 {
 176    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 177    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 178    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 179    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 180    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 181    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 182    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 183    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 184    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 185    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 186    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 187    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 188    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 189    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 190    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 191    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 192    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 193    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 194    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 195    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 196    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 197    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 198    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 199    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 200 };
 201
 202 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 203    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 204     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 205     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 206
 207 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 208    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 209     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 210     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 211     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 212     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 213
 214 /** @} */
 215
 216 /**
 217  * A compiled shader variant, containing a pointer to the GPU assembly,
 218  * as well as program data and other packets needed by state upload.
 219  *
 220  * There can be several iris_compiled_shader variants per API-level shader
 221  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 222  */
 223 struct iris_compiled_shader {
 224    /** Reference to the uploaded assembly. */
 225    struct iris_state_ref assembly;
 226
 227    /** Pointer to the assembly in the BO's map. */
 228    void *map;
 229
 230    /** The program data (owned by the program cache hash table) */
 231    struct brw_stage_prog_data *prog_data;
 232
 233    /** A list of system values to be uploaded as uniforms. */
 234    enum brw_param_builtin *system_values;
 235    unsigned num_system_values;
 236
 237    /**
 238     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 239     * (the VUE-based information for transform feedback outputs).
 240     */
 241    uint32_t *streamout;
 242
 243    /**
 244     * Shader packets and other data derived from prog_data.  These must be
 245     * completely determined from prog_data.
 246     */
 247    uint8_t derived_data[0];
 248 };
 249
 250 /**
 251  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 252  */
 253 struct iris_const_buffer {
 254    /** The resource and offset for the actual constant data */
 255    struct iris_state_ref data;
 256
 257    /** The resource and offset for the SURFACE_STATE for pull access. */
 258    struct iris_state_ref surface_state;
 259 };
 260
 261 /**
 262  * API context state that is replicated per shader stage.
 263  */
 264 struct iris_shader_state {
 265    /** Uniform Buffers */
 266    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 267
 268    struct pipe_constant_buffer cbuf0;
 269    bool cbuf0_needs_upload;
 270
 271    /** Shader Storage Buffers */
 272    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 273    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 274
 275    /** Shader Storage Images (image load store) */
 276    struct {
 277       struct pipe_resource *res;
 278       struct iris_state_ref surface_state;
 279       unsigned access;
 280    } image[PIPE_MAX_SHADER_IMAGES];
 281
 282    struct iris_state_ref sampler_table;
 283    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 284    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 285    unsigned num_samplers;
 286    unsigned num_textures;
 287 };
 288
 289 /**
 290  * Virtual table for generation-specific (genxml) function calls.
 291  */
 292 struct iris_vtable {
 293    void (*destroy_state)(struct iris_context *ice);
 294    void (*init_render_context)(struct iris_screen *screen,
 295                                struct iris_batch *batch,
 296                                struct iris_vtable *vtbl,
 297                                struct pipe_debug_callback *dbg);
 298    void (*init_compute_context)(struct iris_screen *screen,
 299                                 struct iris_batch *batch,
 300                                 struct iris_vtable *vtbl,
 301                                 struct pipe_debug_callback *dbg);
 302    void (*upload_render_state)(struct iris_context *ice,
 303                                struct iris_batch *batch,
 304                                const struct pipe_draw_info *draw);
 305    void (*update_surface_base_address)(struct iris_batch *batch,
 306                                        struct iris_binder *binder);
 307    void (*upload_compute_state)(struct iris_context *ice,
 308                                 struct iris_batch *batch,
 309                                 const struct pipe_grid_info *grid);
 310    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 311                                uint32_t val);
 312    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 313                                uint64_t val);
 314    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 315                                struct iris_bo *bo, uint32_t offset);
 316    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 317                                struct iris_bo *bo, uint32_t offset);
 318    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 319                                 struct iris_bo *bo, uint32_t offset,
 320                                 bool predicated);
 321    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 322                                 struct iris_bo *bo, uint32_t offset,
 323                                 bool predicated);
 324    void (*store_data_imm32)(struct iris_batch *batch,
 325                             struct iris_bo *bo, uint32_t offset,
 326                             uint32_t value);
 327    void (*store_data_imm64)(struct iris_batch *batch,
 328                             struct iris_bo *bo, uint32_t offset,
 329                             uint64_t value);
 330    void (*copy_mem_mem)(struct iris_batch *batch,
 331                         struct iris_bo *dst_bo, uint32_t dst_offset,
 332                         struct iris_bo *src_bo, uint32_t src_offset,
 333                         unsigned bytes);
 334    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 335                                  struct iris_bo *bo, uint32_t offset,
 336                                  uint64_t imm);
 337
 338    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 339    void (*store_derived_program_state)(struct iris_context *ice,
 340                                        enum iris_program_cache_id cache_id,
 341                                        struct iris_compiled_shader *shader);
 342    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 343                                     const struct brw_vue_map *vue_map);
 344    void (*populate_vs_key)(const struct iris_context *ice,
 345                            const struct shader_info *info,
 346                            struct brw_vs_prog_key *key);
 347    void (*populate_tcs_key)(const struct iris_context *ice,
 348                             struct brw_tcs_prog_key *key);
 349    void (*populate_tes_key)(const struct iris_context *ice,
 350                             struct brw_tes_prog_key *key);
 351    void (*populate_gs_key)(const struct iris_context *ice,
 352                            struct brw_gs_prog_key *key);
 353    void (*populate_fs_key)(const struct iris_context *ice,
 354                            struct brw_wm_prog_key *key);
 355    void (*populate_cs_key)(const struct iris_context *ice,
 356                            struct brw_cs_prog_key *key);
 357 };
 358
 359 /**
 360  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 361  *
 362  * See iris_border_color.c for more information.
 363  */
 364 struct iris_border_color_pool {
 365    struct iris_bo *bo;
 366    void *map;
 367    unsigned insert_point;
 368
 369    /** Map from border colors to offsets in the buffer. */
 370    struct hash_table *ht;
 371 };
 372
 373 /**
 374  * The API context (derived from pipe_context).
 375  *
 376  * Most driver state is tracked here.
 377  */
 378 struct iris_context {
 379    struct pipe_context ctx;
 380
 381    /** A debug callback for KHR_debug output. */
 382    struct pipe_debug_callback dbg;
 383
 384    /** Slab allocator for iris_transfer_map objects. */
 385    struct slab_child_pool transfer_pool;
 386
 387    struct iris_vtable vtbl;
 388
 389    struct blorp_context blorp;
 390
 391    struct iris_batch batches[IRIS_BATCH_COUNT];
 392
 393    struct {
 394       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 395       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 396       struct brw_vue_map *last_vue_map;
 397
 398       struct u_upload_mgr *uploader;
 399       struct hash_table *cache;
 400
 401       unsigned urb_size;
 402
 403       /**
 404        * Scratch buffers for various sizes and stages.
 405        *
 406        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 407        * and shader stage.
 408        */
 409       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 410    } shaders;
 411
 412    struct {
 413       uint64_t dirty;
 414       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 415
 416       unsigned num_viewports;
 417       unsigned sample_mask;
 418       struct iris_blend_state *cso_blend;
 419       struct iris_rasterizer_state *cso_rast;
 420       struct iris_depth_stencil_alpha_state *cso_zsa;
 421       struct iris_vertex_element_state *cso_vertex_elements;
 422       struct pipe_blend_color blend_color;
 423       struct pipe_poly_stipple poly_stipple;
 424       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 425       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 426       struct pipe_stencil_ref stencil_ref;
 427       struct pipe_framebuffer_state framebuffer;
 428       struct pipe_clip_state clip_planes;
 429
 430       float default_outer_level[4];
 431       float default_inner_level[2];
 432
 433       bool primitive_restart;
 434       unsigned cut_index;
 435       enum pipe_prim_type prim_mode:8;
 436       uint8_t vertices_per_patch;
 437
 438       /** The last compute grid size */
 439       uint32_t last_grid[3];
 440       /** Reference to the BO containing the compute grid size */
 441       struct iris_state_ref grid_size;
 442       /** Reference to the SURFACE_STATE for the compute grid resource */
 443       struct iris_state_ref grid_surf_state;
 444
 445       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 446       bool depth_writes_enabled;
 447
 448       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 449       bool stencil_writes_enabled;
 450
 451       /** GenX-specific current state */
 452       struct iris_genx_state *genx;
 453
 454       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 455
 456       /** Do any samplers (for any stage) need border color? */
 457       bool need_border_colors;
 458
 459       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 460       bool streamout_active;
 461
 462       bool statistics_counters_enabled;
 463
 464       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 465       bool prims_generated_query_active;
 466
 467       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 468       uint32_t *streamout;
 469
 470       /** The SURFACE_STATE for a 1x1x1 null surface. */
 471       struct iris_state_ref unbound_tex;
 472
 473       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 474       struct iris_state_ref null_fb;
 475
 476       struct u_upload_mgr *surface_uploader;
 477       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 478       // "I'm streaming this out at draw time and never want it again!"
 479       struct u_upload_mgr *dynamic_uploader;
 480
 481       struct iris_binder binder;
 482
 483       struct iris_border_color_pool border_color_pool;
 484
 485       /** The high 16-bits of the last VBO/index buffer addresses */
 486       uint16_t last_vbo_high_bits[33];
 487       uint16_t last_index_bo_high_bits;
 488
 489       /**
 490        * Resources containing streamed state which our render context
 491        * currently points to.  Used to re-add these to the validation
 492        * list when we start a new batch and haven't resubmitted commands.
 493        */
 494       struct {
 495          struct pipe_resource *cc_vp;
 496          struct pipe_resource *sf_cl_vp;
 497          struct pipe_resource *color_calc;
 498          struct pipe_resource *scissor;
 499          struct pipe_resource *blend;
 500          struct pipe_resource *index_buffer;
 501       } last_res;
 502    } state;
 503 };
 504
 505 #define perf_debug(dbg, ...) do {                      \
 506    if (INTEL_DEBUG & DEBUG_PERF)                       \
 507       dbg_printf(__VA_ARGS__);                         \
 508    if (unlikely(dbg))                                  \
 509       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 510 } while(0)
 511
 512 double get_time(void);
 513
 514 struct pipe_context *
 515 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 516
 517 void iris_init_blit_functions(struct pipe_context *ctx);
 518 void iris_init_clear_functions(struct pipe_context *ctx);
 519 void iris_init_program_functions(struct pipe_context *ctx);
 520 void iris_init_resource_functions(struct pipe_context *ctx);
 521 void iris_init_query_functions(struct pipe_context *ctx);
 522 void iris_update_compiled_shaders(struct iris_context *ice);
 523 void iris_update_compiled_compute_shader(struct iris_context *ice);
 524 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 525                                     uint32_t *dst);
 526
 527
 528 /* iris_blit.c */
 529 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 530                                   struct pipe_resource *p_res,
 531                                   enum isl_aux_usage aux_usage,
 532                                   bool is_render_target);
 533
 534 /* iris_draw.c */
 535
 536 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 537 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 538
 539 /* iris_pipe_control.c */
 540
 541 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 542                                   uint32_t flags);
 543 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 544                                   struct iris_bo *bo, uint32_t offset,
 545                                   uint64_t imm);
 546 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 547                                 uint32_t flags);
 548
 549 void iris_init_flush_functions(struct pipe_context *ctx);
 550
 551 /* iris_blorp.c */
 552
 553 void gen9_init_blorp(struct iris_context *ice);
 554 void gen10_init_blorp(struct iris_context *ice);
 555 void gen11_init_blorp(struct iris_context *ice);
 556
 557 /* iris_border_color.c */
 558
 559 void iris_init_border_color_pool(struct iris_context *ice);
 560 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 561 uint32_t iris_upload_border_color(struct iris_context *ice,
 562                                   union pipe_color_union *color);
 563
 564 /* iris_state.c */
 565
 566 void gen9_init_state(struct iris_context *ice);
 567 void gen10_init_state(struct iris_context *ice);
 568 void gen11_init_state(struct iris_context *ice);
 569
 570 /* iris_program.c */
 571 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 572                                                gl_shader_stage stage);
 573 unsigned iris_get_shader_num_ubos(const struct iris_context *ice,
 574                                   gl_shader_stage stage);
 575 uint32_t iris_get_scratch_space(struct iris_context *ice,
 576                                 unsigned per_thread_scratch,
 577                                 gl_shader_stage stage);
 578
 579 /* iris_program_cache.c */
 580
 581 void iris_init_program_cache(struct iris_context *ice);
 582 void iris_destroy_program_cache(struct iris_context *ice);
 583 void iris_print_program_cache(struct iris_context *ice);
 584 bool iris_bind_cached_shader(struct iris_context *ice,
 585                              enum iris_program_cache_id cache_id,
 586                              const void *key);
 587 void iris_unbind_shader(struct iris_context *ice,
 588                         enum iris_program_cache_id cache_id);
 589 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 590                                                 enum iris_program_cache_id,
 591                                                 uint32_t key_size,
 592                                                 const void *key,
 593                                                 const void *assembly,
 594                                                 struct brw_stage_prog_data *,
 595                                                 uint32_t *streamout,
 596                                                 enum brw_param_builtin *sysv,
 597                                                 unsigned num_system_values);
 598 void iris_upload_and_bind_shader(struct iris_context *ice,
 599                                  enum iris_program_cache_id cache_id,
 600                                  const void *key,
 601                                  const void *assembly,
 602                                  struct brw_stage_prog_data *prog_data,
 603                                  uint32_t *streamout,
 604                                  enum brw_param_builtin *system_values,
 605                                  unsigned num_system_values);
 606 const void *iris_find_previous_compile(const struct iris_context *ice,
 607                                        enum iris_program_cache_id cache_id,
 608                                        unsigned program_string_id);
 609 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 610                               const void *key,
 611                               uint32_t key_size,
 612                               uint32_t *kernel_out,
 613                               void *prog_data_out);
 614 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 615                               const void *key, uint32_t key_size,
 616                               const void *kernel, uint32_t kernel_size,
 617                               const struct brw_stage_prog_data *prog_data,
 618                               uint32_t prog_data_size,
 619                               uint32_t *kernel_out,
 620                               void *prog_data_out);
 621
 622 /* iris_query.c */
 623
 624 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 625                              uint64_t gpu_timestamp);
 626
 627 /* iris_resolve.c */
 628
 629 void iris_predraw_resolve_inputs(struct iris_context *ice,
 630                                  struct iris_batch *batch);
 631 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 632                                       struct iris_batch *batch);
 633 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 634                                            struct iris_batch *batch);
 635 void iris_cache_sets_clear(struct iris_batch *batch);
 636 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 637 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 638 void iris_cache_flush_for_render(struct iris_batch *batch,
 639                                  struct iris_bo *bo,
 640                                  enum isl_format format,
 641                                  enum isl_aux_usage aux_usage);
 642 void iris_render_cache_add_bo(struct iris_batch *batch,
 643                               struct iris_bo *bo,
 644                               enum isl_format format,
 645                               enum isl_aux_usage aux_usage);
 646 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 647 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 648
 649 #endif