src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/common/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_resource.h"
  35 #include "iris_screen.h"
  36
  37 struct iris_bo;
  38 struct iris_context;
  39 struct blorp_batch;
  40 struct blorp_params;
  41
  42 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  43 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  44 #define IRIS_MAX_ABOS 16
  45 #define IRIS_MAX_SSBOS 16
  46 #define IRIS_MAX_VIEWPORTS 16
  47
  48 /**
  49  * Dirty flags.  When state changes, we flag some combination of these
  50  * to indicate that particular GPU commands need to be re-emitted.
  51  *
  52  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  53  * in rare cases they map to a group of related packets that need to be
  54  * emitted together.
  55  *
  56  * See iris_upload_render_state().
  57  */
  58 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  59 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  60 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  61 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  62 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  63 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  64 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  65 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  66 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  67 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  68 #define IRIS_DIRTY_SBE                      (1ull << 10)
  69 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  70 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  71 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  72 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  73 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  74 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  75 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  76 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  77 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  78 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  79 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  80 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  81 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  82 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  83 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  84 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
  85 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
  86 #define IRIS_DIRTY_VS                       (1ull << 28)
  87 #define IRIS_DIRTY_TCS                      (1ull << 29)
  88 #define IRIS_DIRTY_TES                      (1ull << 30)
  89 #define IRIS_DIRTY_GS                       (1ull << 31)
  90 #define IRIS_DIRTY_FS                       (1ull << 32)
  91 #define IRIS_DIRTY_CS                       (1ull << 33)
  92 #define IRIS_DIRTY_URB                      (1ull << 34)
  93 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
  94 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
  95 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
  96 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
  97 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
  98 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 40)
  99 #define IRIS_DIRTY_WM                       (1ull << 41)
 100 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 42)
 101 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 43)
 102 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 44)
 103 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 45)
 104 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 46)
 105 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 47)
 106 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 48)
 107 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 49)
 108 #define IRIS_DIRTY_STREAMOUT                (1ull << 50)
 109 #define IRIS_DIRTY_VF_SGVS                  (1ull << 51)
 110 #define IRIS_DIRTY_VF                       (1ull << 52)
 111 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 53)
 112
 113 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 114                                  IRIS_DIRTY_BINDINGS_TCS | \
 115                                  IRIS_DIRTY_BINDINGS_TES | \
 116                                  IRIS_DIRTY_BINDINGS_GS  | \
 117                                  IRIS_DIRTY_BINDINGS_FS  | \
 118                                  IRIS_DIRTY_BINDINGS_CS)
 119
 120 /**
 121  * Non-orthogonal state (NOS) dependency flags.
 122  *
 123  * Shader programs may depend on non-orthogonal state.  These flags are
 124  * used to indicate that a shader's key depends on the state provided by
 125  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 126  * cause the driver to re-compute the shader key, possibly triggering a
 127  * shader recompile.
 128  */
 129 enum iris_nos_dep {
 130    IRIS_NOS_FRAMEBUFFER,
 131    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 132    IRIS_NOS_RASTERIZER,
 133    IRIS_NOS_BLEND,
 134    IRIS_NOS_LAST_VUE_MAP,
 135
 136    IRIS_NOS_COUNT,
 137 };
 138
 139 struct iris_depth_stencil_alpha_state;
 140
 141 /**
 142  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 143  */
 144 enum iris_program_cache_id {
 145    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 146    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 147    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 148    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 149    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 150    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 151    IRIS_CACHE_BLORP,
 152 };
 153
 154 /** @{
 155  *
 156  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 157  * synchronization, pipelined memory writes, and so on.
 158  *
 159  * The bits here are not the actual hardware values.  The actual fields
 160  * move between various generations, so we just have flags for each
 161  * potential operation, and use genxml to encode the actual packet.
 162  */
 163 enum pipe_control_flags
 164 {
 165    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 166    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 167    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 168    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 169    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 170    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 171    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 172    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 173    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 174    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 175    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 176    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 177    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 178    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 179    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 180    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 181    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 182    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 183    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 184    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 185    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 186    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 187    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 188    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 189 };
 190
 191 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 192    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 193     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 194     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 195
 196 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 197    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 198     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 199     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 200     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 201     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 202
 203 /** @} */
 204
 205 /**
 206  * A compiled shader variant, containing a pointer to the GPU assembly,
 207  * as well as program data and other packets needed by state upload.
 208  *
 209  * There can be several iris_compiled_shader variants per API-level shader
 210  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 211  */
 212 struct iris_compiled_shader {
 213    /** Reference to the uploaded assembly. */
 214    struct iris_state_ref assembly;
 215
 216    /** Pointer to the assembly in the BO's map. */
 217    void *map;
 218
 219    /** The program data (owned by the program cache hash table) */
 220    struct brw_stage_prog_data *prog_data;
 221
 222    /**
 223     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 224     * (the VUE-based information for transform feedback outputs).
 225     */
 226    uint32_t *streamout;
 227
 228    /**
 229     * Shader packets and other data derived from prog_data.  These must be
 230     * completely determined from prog_data.
 231     */
 232    uint8_t derived_data[0];
 233 };
 234
 235 /**
 236  * Constant buffer (UBO) information.  See iris_set_const_buffer().
 237  */
 238 struct iris_const_buffer {
 239    /** The resource and offset for the actual constant data */
 240    struct iris_state_ref data;
 241
 242    /** The resource and offset for the SURFACE_STATE for pull access. */
 243    struct iris_state_ref surface_state;
 244 };
 245
 246 /**
 247  * API context state that is replicated per shader stage.
 248  */
 249 struct iris_shader_state {
 250    /** Uniform Buffers */
 251    struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 252
 253    /** Shader Storage Buffers */
 254    struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
 255    struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
 256
 257    /** Shader Storage Images (image load store) */
 258    struct pipe_resource *image[PIPE_MAX_SHADER_IMAGES];
 259    struct iris_state_ref image_surface_state[PIPE_MAX_SHADER_IMAGES];
 260
 261    struct iris_state_ref sampler_table;
 262    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 263    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 264    unsigned num_samplers;
 265    unsigned num_textures;
 266 };
 267
 268 /**
 269  * Virtual table for generation-specific (genxml) function calls.
 270  */
 271 struct iris_vtable {
 272    void (*destroy_state)(struct iris_context *ice);
 273    void (*init_render_context)(struct iris_screen *screen,
 274                                struct iris_batch *batch,
 275                                struct iris_vtable *vtbl,
 276                                struct pipe_debug_callback *dbg);
 277    void (*upload_render_state)(struct iris_context *ice,
 278                                struct iris_batch *batch,
 279                                const struct pipe_draw_info *draw);
 280    void (*update_surface_base_address)(struct iris_batch *batch,
 281                                        struct iris_binder *binder);
 282    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 283                                uint32_t val);
 284    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 285                                uint64_t val);
 286    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 287                                struct iris_bo *bo, uint32_t offset);
 288    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 289                                struct iris_bo *bo, uint32_t offset);
 290    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 291                                 struct iris_bo *bo, uint32_t offset,
 292                                 bool predicated);
 293    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 294                                 struct iris_bo *bo, uint32_t offset,
 295                                 bool predicated);
 296    void (*store_data_imm32)(struct iris_batch *batch,
 297                             struct iris_bo *bo, uint32_t offset,
 298                             uint32_t value);
 299    void (*store_data_imm64)(struct iris_batch *batch,
 300                             struct iris_bo *bo, uint32_t offset,
 301                             uint64_t value);
 302    void (*copy_mem_mem)(struct iris_batch *batch,
 303                         struct iris_bo *dst_bo, uint32_t dst_offset,
 304                         struct iris_bo *src_bo, uint32_t src_offset,
 305                         unsigned bytes);
 306    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 307                                  struct iris_bo *bo, uint32_t offset,
 308                                  uint64_t imm);
 309
 310    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 311    void (*store_derived_program_state)(const struct gen_device_info *devinfo,
 312                                        enum iris_program_cache_id cache_id,
 313                                        struct iris_compiled_shader *shader);
 314    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 315                                     const struct brw_vue_map *vue_map);
 316    void (*populate_vs_key)(const struct iris_context *ice,
 317                            struct brw_vs_prog_key *key);
 318    void (*populate_tcs_key)(const struct iris_context *ice,
 319                             struct brw_tcs_prog_key *key);
 320    void (*populate_tes_key)(const struct iris_context *ice,
 321                             struct brw_tes_prog_key *key);
 322    void (*populate_gs_key)(const struct iris_context *ice,
 323                            struct brw_gs_prog_key *key);
 324    void (*populate_fs_key)(const struct iris_context *ice,
 325                            struct brw_wm_prog_key *key);
 326 };
 327
 328 /**
 329  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 330  *
 331  * See iris_border_color.c for more information.
 332  */
 333 struct iris_border_color_pool {
 334    struct iris_bo *bo;
 335    void *map;
 336    unsigned insert_point;
 337
 338    /** Map from border colors to offsets in the buffer. */
 339    struct hash_table *ht;
 340 };
 341
 342 /**
 343  * The API context (derived from pipe_context).
 344  *
 345  * Most driver state is tracked here.
 346  */
 347 struct iris_context {
 348    struct pipe_context ctx;
 349
 350    /** A debug callback for KHR_debug output. */
 351    struct pipe_debug_callback dbg;
 352
 353    /** Slab allocator for iris_transfer_map objects. */
 354    struct slab_child_pool transfer_pool;
 355
 356    struct iris_vtable vtbl;
 357
 358    struct blorp_context blorp;
 359
 360    /** The main batch for rendering. */
 361    struct iris_batch render_batch;
 362
 363    struct {
 364       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 365       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 366       struct brw_vue_map *last_vue_map;
 367
 368       struct u_upload_mgr *uploader;
 369       struct hash_table *cache;
 370
 371       unsigned urb_size;
 372    } shaders;
 373
 374    struct {
 375       uint64_t dirty;
 376       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 377
 378       unsigned num_viewports;
 379       unsigned sample_mask;
 380       struct iris_blend_state *cso_blend;
 381       struct iris_rasterizer_state *cso_rast;
 382       struct iris_depth_stencil_alpha_state *cso_zsa;
 383       struct iris_vertex_element_state *cso_vertex_elements;
 384       struct pipe_blend_color blend_color;
 385       struct pipe_poly_stipple poly_stipple;
 386       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 387       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 388       struct pipe_stencil_ref stencil_ref;
 389       struct pipe_framebuffer_state framebuffer;
 390
 391       float default_outer_level[4];
 392       float default_inner_level[2];
 393
 394       bool primitive_restart;
 395       unsigned cut_index;
 396       enum pipe_prim_type prim_mode:8;
 397       uint8_t vertices_per_patch;
 398
 399       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 400       bool depth_writes_enabled;
 401
 402       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 403       bool stencil_writes_enabled;
 404
 405       /** GenX-specific current state */
 406       struct iris_genx_state *genx;
 407
 408       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 409
 410       /** Do any samplers (for any stage) need border color? */
 411       bool need_border_colors;
 412
 413       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 414       bool streamout_active;
 415
 416       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 417       bool prims_generated_query_active;
 418
 419       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 420       uint32_t *streamout;
 421
 422       /** The SURFACE_STATE for a 1x1x1 null surface. */
 423       struct iris_state_ref unbound_tex;
 424
 425       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 426       struct iris_state_ref null_fb;
 427
 428       struct u_upload_mgr *surface_uploader;
 429       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 430       // "I'm streaming this out at draw time and never want it again!"
 431       struct u_upload_mgr *dynamic_uploader;
 432
 433       struct iris_binder binder;
 434
 435       struct iris_border_color_pool border_color_pool;
 436
 437       /**
 438        * Resources containing streamed state which our render context
 439        * currently points to.  Used to re-add these to the validation
 440        * list when we start a new batch and haven't resubmitted commands.
 441        */
 442       struct {
 443          struct pipe_resource *cc_vp;
 444          struct pipe_resource *sf_cl_vp;
 445          struct pipe_resource *color_calc;
 446          struct pipe_resource *scissor;
 447          struct pipe_resource *blend;
 448          struct pipe_resource *index_buffer;
 449       } last_res;
 450    } state;
 451 };
 452
 453 #define perf_debug(dbg, ...) do {                      \
 454    if (INTEL_DEBUG & DEBUG_PERF)                       \
 455       dbg_printf(__VA_ARGS__);                         \
 456    if (unlikely(dbg))                                  \
 457       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 458 } while(0)
 459
 460 double get_time(void);
 461
 462 struct pipe_context *
 463 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 464
 465 void iris_init_blit_functions(struct pipe_context *ctx);
 466 void iris_init_clear_functions(struct pipe_context *ctx);
 467 void iris_init_program_functions(struct pipe_context *ctx);
 468 void iris_init_resource_functions(struct pipe_context *ctx);
 469 void iris_init_query_functions(struct pipe_context *ctx);
 470 void iris_update_compiled_shaders(struct iris_context *ice);
 471
 472 /* iris_blit.c */
 473 void iris_blorp_surf_for_resource(struct blorp_surf *surf,
 474                                   struct pipe_resource *p_res,
 475                                   enum isl_aux_usage aux_usage,
 476                                   bool is_render_target);
 477
 478 /* iris_draw.c */
 479
 480 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 481
 482 /* iris_pipe_control.c */
 483
 484 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 485                                   uint32_t flags);
 486 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 487                                   struct iris_bo *bo, uint32_t offset,
 488                                   uint64_t imm);
 489 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 490                                 uint32_t flags);
 491
 492 void iris_init_flush_functions(struct pipe_context *ctx);
 493
 494 /* iris_blorp.c */
 495
 496 void gen9_init_blorp(struct iris_context *ice);
 497 void gen10_init_blorp(struct iris_context *ice);
 498 void gen11_init_blorp(struct iris_context *ice);
 499
 500 /* iris_border_color.c */
 501
 502 void iris_init_border_color_pool(struct iris_context *ice);
 503 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 504 uint32_t iris_upload_border_color(struct iris_context *ice,
 505                                   union pipe_color_union *color);
 506
 507 /* iris_state.c */
 508
 509 void gen9_init_state(struct iris_context *ice);
 510 void gen10_init_state(struct iris_context *ice);
 511 void gen11_init_state(struct iris_context *ice);
 512
 513 /* iris_program.c */
 514 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 515                                                gl_shader_stage stage);
 516
 517 /* iris_program_cache.c */
 518
 519 void iris_init_program_cache(struct iris_context *ice);
 520 void iris_destroy_program_cache(struct iris_context *ice);
 521 void iris_print_program_cache(struct iris_context *ice);
 522 bool iris_bind_cached_shader(struct iris_context *ice,
 523                              enum iris_program_cache_id cache_id,
 524                              const void *key);
 525 void iris_unbind_shader(struct iris_context *ice,
 526                         enum iris_program_cache_id cache_id);
 527 void iris_upload_and_bind_shader(struct iris_context *ice,
 528                                  enum iris_program_cache_id cache_id,
 529                                  const void *key,
 530                                  const void *assembly,
 531                                  struct brw_stage_prog_data *prog_data,
 532                                  uint32_t *streamout);
 533 const void *iris_find_previous_compile(const struct iris_context *ice,
 534                                        enum iris_program_cache_id cache_id,
 535                                        unsigned program_string_id);
 536 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 537                               const void *key,
 538                               uint32_t key_size,
 539                               uint32_t *kernel_out,
 540                               void *prog_data_out);
 541 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 542                               const void *key, uint32_t key_size,
 543                               const void *kernel, uint32_t kernel_size,
 544                               const struct brw_stage_prog_data *prog_data,
 545                               uint32_t prog_data_size,
 546                               uint32_t *kernel_out,
 547                               void *prog_data_out);
 548
 549 /* iris_query.c */
 550
 551 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 552                              uint64_t gpu_timestamp);
 553
 554 /* iris_resolve.c */
 555
 556 void iris_predraw_resolve_inputs(struct iris_context *ice,
 557                                  struct iris_batch *batch);
 558 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 559                                       struct iris_batch *batch);
 560 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 561                                            struct iris_batch *batch);
 562 void iris_cache_sets_clear(struct iris_batch *batch);
 563 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 564 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 565 void iris_cache_flush_for_render(struct iris_batch *batch,
 566                                  struct iris_bo *bo,
 567                                  enum isl_format format,
 568                                  enum isl_aux_usage aux_usage);
 569 void iris_render_cache_add_bo(struct iris_batch *batch,
 570                               struct iris_bo *bo,
 571                               enum isl_format format,
 572                               enum isl_aux_usage aux_usage);
 573 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 574 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 575
 576 #endif