iris: Implement INTEL_DEBUG=pc for pipe control logging.
[mesa.git] / src / gallium / drivers / iris / iris_defines.h
1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef IRIS_DEFINES_H
24 #define IRIS_DEFINES_H
25
26 /**
27 * @file iris_defines.h
28 *
29 * Random hardware #defines that we're not using GENXML for.
30 */
31
32 #define MI_PREDICATE (0xC << 23)
33 # define MI_PREDICATE_LOADOP_KEEP (0 << 6)
34 # define MI_PREDICATE_LOADOP_LOAD (2 << 6)
35 # define MI_PREDICATE_LOADOP_LOADINV (3 << 6)
36 # define MI_PREDICATE_COMBINEOP_SET (0 << 3)
37 # define MI_PREDICATE_COMBINEOP_AND (1 << 3)
38 # define MI_PREDICATE_COMBINEOP_OR (2 << 3)
39 # define MI_PREDICATE_COMBINEOP_XOR (3 << 3)
40 # define MI_PREDICATE_COMPAREOP_TRUE (0 << 0)
41 # define MI_PREDICATE_COMPAREOP_FALSE (1 << 0)
42 # define MI_PREDICATE_COMPAREOP_SRCS_EQUAL (2 << 0)
43 # define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL (3 << 0)
44
45 /* Predicate registers */
46 #define MI_PREDICATE_SRC0 0x2400
47 #define MI_PREDICATE_SRC1 0x2408
48 #define MI_PREDICATE_DATA 0x2410
49 #define MI_PREDICATE_RESULT 0x2418
50 #define MI_PREDICATE_RESULT_1 0x241C
51 #define MI_PREDICATE_RESULT_2 0x2214
52
53 #define CS_GPR(n) (0x2600 + (n) * 8)
54
55 /* MI_MATH registers */
56 #define MI_ALU_R0 0x00
57 #define MI_ALU_R1 0x01
58 #define MI_ALU_R2 0x02
59 #define MI_ALU_R3 0x03
60 #define MI_ALU_R4 0x04
61
62 /* MI_MATH operations */
63 #define MI_MATH (0x1a << 23)
64
65 #define _MI_ALU(op, x, y) (((op) << 20) | ((x) << 10) | (y))
66
67 #define _MI_ALU0(op) _MI_ALU(MI_ALU_##op, 0, 0)
68 #define _MI_ALU1(op, x) _MI_ALU(MI_ALU_##op, x, 0)
69 #define _MI_ALU2(op, x, y) _MI_ALU(MI_ALU_##op, x, y)
70
71 #define MI_ALU0(op) _MI_ALU0(op)
72 #define MI_ALU1(op, x) _MI_ALU1(op, MI_ALU_##x)
73 #define MI_ALU2(op, x, y) _MI_ALU2(op, MI_ALU_##x, MI_ALU_##y)
74
75 /* The number of bits in our TIMESTAMP queries. */
76 #define TIMESTAMP_BITS 36
77
78 #endif