src/gallium/drivers/iris/iris_perf.c

   1 /*
   2  * Copyright © 2019 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "iris_perf.h"
  24 #include "iris_context.h"
  25 #include "perf/gen_perf_regs.h"
  26
  27 static void *
  28 iris_oa_bo_alloc(void *bufmgr, const char *name, uint64_t size)
  29 {
  30    return iris_bo_alloc(bufmgr, name, size, IRIS_MEMZONE_OTHER);
  31 }
  32
  33 static void
  34 iris_perf_emit_stall_at_pixel_scoreboard(struct iris_context *ice)
  35 {
  36    iris_emit_end_of_pipe_sync(&ice->batches[IRIS_BATCH_RENDER],
  37                               "OA metrics",
  38                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
  39 }
  40
  41 static void
  42 iris_perf_emit_mi_report_perf_count(void *c,
  43                                        void *bo,
  44                                        uint32_t offset_in_bytes,
  45                                        uint32_t report_id)
  46 {
  47    struct iris_context *ice = c;
  48    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
  49    ice->vtbl.emit_mi_report_perf_count(batch, bo, offset_in_bytes, report_id);
  50 }
  51
  52 static void
  53 iris_perf_batchbuffer_flush(void *c, const char *file, int line)
  54 {
  55    struct iris_context *ice = c;
  56    _iris_batch_flush(&ice->batches[IRIS_BATCH_RENDER], __FILE__, __LINE__);
  57 }
  58
  59 static void
  60 iris_perf_capture_frequency_stat_register(void *ctx,
  61                                                 void *bo,
  62                                                 uint32_t bo_offset)
  63 {
  64    struct iris_context *ice = ctx;
  65    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
  66    struct gen_device_info *devinfo = &batch->screen->devinfo;
  67
  68    if (devinfo->gen == 8 && !devinfo->is_cherryview)
  69       ice->vtbl.store_register_mem32(batch, GEN7_RPSTAT1, bo, bo_offset, false);
  70    else if (devinfo->gen >= 9)
  71       ice->vtbl.store_register_mem32(batch, GEN9_RPSTAT0, bo, bo_offset, false);
  72 }
  73
  74 static void
  75 iris_perf_store_register_mem64(void *ctx, void *bo,
  76                                      uint32_t reg, uint32_t offset)
  77 {
  78    struct iris_context *ice = ctx;
  79    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
  80    ice->vtbl.store_register_mem64(batch, reg, bo, offset, false);
  81 }
  82
  83 typedef void (*bo_unreference_t)(void *);
  84 typedef void *(*bo_map_t)(void *, void *, unsigned flags);
  85 typedef void (*bo_unmap_t)(void *);
  86 typedef void (*emit_mi_report_t)(void *, void *, uint32_t, uint32_t);
  87 typedef void (*emit_mi_flush_t)(void *);
  88 typedef void (*capture_frequency_stat_register_t)(void *, void *, uint32_t );
  89 typedef void (*store_register_mem64_t)(void *ctx, void *bo,
  90                                        uint32_t reg, uint32_t offset);
  91 typedef bool (*batch_references_t)(void *batch, void *bo);
  92 typedef void (*bo_wait_rendering_t)(void *bo);
  93 typedef int (*bo_busy_t)(void *bo);
  94
  95 void
  96 iris_perf_init_vtbl(struct gen_perf_config *perf_cfg)
  97 {
  98    perf_cfg->vtbl.bo_alloc = iris_oa_bo_alloc;
  99    perf_cfg->vtbl.bo_unreference = (bo_unreference_t)iris_bo_unreference;
 100    perf_cfg->vtbl.bo_map = (bo_map_t)iris_bo_map;
 101    perf_cfg->vtbl.bo_unmap = (bo_unmap_t)iris_bo_unmap;
 102    perf_cfg->vtbl.emit_stall_at_pixel_scoreboard =
 103       (emit_mi_flush_t)iris_perf_emit_stall_at_pixel_scoreboard;
 104
 105    perf_cfg->vtbl.emit_mi_report_perf_count =
 106       (emit_mi_report_t)iris_perf_emit_mi_report_perf_count;
 107    perf_cfg->vtbl.batchbuffer_flush = iris_perf_batchbuffer_flush;
 108    perf_cfg->vtbl.capture_frequency_stat_register =
 109       (capture_frequency_stat_register_t) iris_perf_capture_frequency_stat_register;
 110    perf_cfg->vtbl.store_register_mem64 =
 111       (store_register_mem64_t) iris_perf_store_register_mem64;
 112    perf_cfg->vtbl.batch_references = (batch_references_t)iris_batch_references;
 113    perf_cfg->vtbl.bo_wait_rendering =
 114       (bo_wait_rendering_t)iris_bo_wait_rendering;
 115    perf_cfg->vtbl.bo_busy = (bo_busy_t)iris_bo_busy;
 116 }