src/gallium/drivers/iris/iris_pipe_control.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "iris_context.h"
  25
  26 /**
  27  * Emit a PIPE_CONTROL with various flushing flags.
  28  *
  29  * The caller is responsible for deciding what flags are appropriate for the
  30  * given generation.
  31  */
  32 void
  33 iris_emit_pipe_control_flush(struct iris_context *ice,
  34                              struct iris_batch *batch,
  35                              uint32_t flags)
  36 {
  37    if ((flags & PIPE_CONTROL_CACHE_FLUSH_BITS) &&
  38        (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) {
  39       /* A pipe control command with flush and invalidate bits set
  40        * simultaneously is an inherently racy operation on Gen6+ if the
  41        * contents of the flushed caches were intended to become visible from
  42        * any of the invalidated caches.  Split it in two PIPE_CONTROLs, the
  43        * first one should stall the pipeline to make sure that the flushed R/W
  44        * caches are coherent with memory once the specified R/O caches are
  45        * invalidated.  On pre-Gen6 hardware the (implicit) R/O cache
  46        * invalidation seems to happen at the bottom of the pipeline together
  47        * with any write cache flush, so this shouldn't be a concern.  In order
  48        * to ensure a full stall, we do an end-of-pipe sync.
  49        */
  50       iris_emit_end_of_pipe_sync(ice, batch,
  51                                  flags & PIPE_CONTROL_CACHE_FLUSH_BITS);
  52       flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
  53    }
  54
  55    ice->state.emit_raw_pipe_control(batch, flags, NULL, 0, 0);
  56 }
  57
  58 /**
  59  * Emit a PIPE_CONTROL that writes to a buffer object.
  60  *
  61  * \p flags should contain one of the following items:
  62  *  - PIPE_CONTROL_WRITE_IMMEDIATE
  63  *  - PIPE_CONTROL_WRITE_TIMESTAMP
  64  *  - PIPE_CONTROL_WRITE_DEPTH_COUNT
  65  */
  66 void
  67 iris_emit_pipe_control_write(struct iris_context *ice,
  68                              struct iris_batch *batch, uint32_t flags,
  69                              struct iris_bo *bo, uint32_t offset,
  70                              uint64_t imm)
  71 {
  72    ice->state.emit_raw_pipe_control(batch, flags, bo, offset, imm);
  73 }
  74
  75 /*
  76  * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
  77  *
  78  *  Write synchronization is a special case of end-of-pipe
  79  *  synchronization that requires that the render cache and/or depth
  80  *  related caches are flushed to memory, where the data will become
  81  *  globally visible. This type of synchronization is required prior to
  82  *  SW (CPU) actually reading the result data from memory, or initiating
  83  *  an operation that will use as a read surface (such as a texture
  84  *  surface) a previous render target and/or depth/stencil buffer
  85  *
  86  * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
  87  *
  88  *  Exercising the write cache flush bits (Render Target Cache Flush
  89  *  Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
  90  *  ensures the write caches are flushed and doesn't guarantee the data
  91  *  is globally visible.
  92  *
  93  *  SW can track the completion of the end-of-pipe-synchronization by
  94  *  using "Notify Enable" and "PostSync Operation - Write Immediate
  95  *  Data" in the PIPE_CONTROL command.
  96  */
  97 void
  98 iris_emit_end_of_pipe_sync(struct iris_context *ice,
  99                            struct iris_batch *batch,
 100                            uint32_t flags)
 101 {
 102    /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
 103     *
 104     *    "The most common action to perform upon reaching a synchronization
 105     *    point is to write a value out to memory. An immediate value
 106     *    (included with the synchronization command) may be written."
 107     *
 108     * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
 109     *
 110     *    "In case the data flushed out by the render engine is to be read
 111     *    back in to the render engine in coherent manner, then the render
 112     *    engine has to wait for the fence completion before accessing the
 113     *    flushed data. This can be achieved by following means on various
 114     *    products: PIPE_CONTROL command with CS Stall and the required
 115     *    write caches flushed with Post-Sync-Operation as Write Immediate
 116     *    Data.
 117     *
 118     *    Example:
 119     *       - Workload-1 (3D/GPGPU/MEDIA)
 120     *       - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write Immediate
 121     *         Data, Required Write Cache Flush bits set)
 122     *       - Workload-2 (Can use the data produce or output by Workload-1)
 123     */
 124    iris_emit_pipe_control_write(ice, batch, flags | PIPE_CONTROL_CS_STALL |
 125                                 PIPE_CONTROL_WRITE_IMMEDIATE,
 126                                 batch->screen->workaround_bo, 0, 0);
 127 }