2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
45 #define ALL_SAMPLERS_XYZW .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688
46 #define KEY_INIT .program_string_id = ish->program_id, ALL_SAMPLERS_XYZW
48 static struct iris_compiled_shader
*
49 iris_compile_vs(struct iris_context
*, struct iris_uncompiled_shader
*,
50 const struct brw_vs_prog_key
*);
51 static struct iris_compiled_shader
*
52 iris_compile_tcs(struct iris_context
*, struct iris_uncompiled_shader
*,
53 const struct brw_tcs_prog_key
*);
54 static struct iris_compiled_shader
*
55 iris_compile_tes(struct iris_context
*, struct iris_uncompiled_shader
*,
56 const struct brw_tes_prog_key
*);
57 static struct iris_compiled_shader
*
58 iris_compile_gs(struct iris_context
*, struct iris_uncompiled_shader
*,
59 const struct brw_gs_prog_key
*);
60 static struct iris_compiled_shader
*
61 iris_compile_fs(struct iris_context
*, struct iris_uncompiled_shader
*,
62 const struct brw_wm_prog_key
*, struct brw_vue_map
*);
63 static struct iris_compiled_shader
*
64 iris_compile_cs(struct iris_context
*, struct iris_uncompiled_shader
*,
65 const struct brw_cs_prog_key
*);
69 get_new_program_id(struct iris_screen
*screen
)
71 return p_atomic_inc_return(&screen
->program_id
);
75 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
76 * It primarily contains the NIR for the shader.
78 * Each API-facing shader can be compiled into multiple shader variants,
79 * based on non-orthogonal state dependencies, recorded in the shader key.
81 * See iris_compiled_shader, which represents a compiled shader variant.
83 struct iris_uncompiled_shader
{
86 struct pipe_stream_output_info stream_output
;
90 /** Bitfield of (1 << IRIS_NOS_*) flags. */
93 /** Have any shader variants been compiled yet? */
98 get_aoa_deref_offset(nir_builder
*b
,
99 nir_deref_instr
*deref
,
102 unsigned array_size
= elem_size
;
103 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
105 while (deref
->deref_type
!= nir_deref_type_var
) {
106 assert(deref
->deref_type
== nir_deref_type_array
);
108 /* This level's element size is the previous level's array size */
109 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
110 assert(deref
->arr
.index
.ssa
);
111 offset
= nir_iadd(b
, offset
,
112 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
114 deref
= nir_deref_instr_parent(deref
);
115 assert(glsl_type_is_array(deref
->type
));
116 array_size
*= glsl_get_length(deref
->type
);
119 /* Accessing an invalid surface index with the dataport can result in a
120 * hang. According to the spec "if the index used to select an individual
121 * element is negative or greater than or equal to the size of the array,
122 * the results of the operation are undefined but may not lead to
123 * termination" -- which is one of the possible outcomes of the hang.
124 * Clamp the index to prevent access outside of the array bounds.
126 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
130 iris_lower_storage_image_derefs(nir_shader
*nir
)
132 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
135 nir_builder_init(&b
, impl
);
137 nir_foreach_block(block
, impl
) {
138 nir_foreach_instr_safe(instr
, block
) {
139 if (instr
->type
!= nir_instr_type_intrinsic
)
142 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
143 switch (intrin
->intrinsic
) {
144 case nir_intrinsic_image_deref_load
:
145 case nir_intrinsic_image_deref_store
:
146 case nir_intrinsic_image_deref_atomic_add
:
147 case nir_intrinsic_image_deref_atomic_min
:
148 case nir_intrinsic_image_deref_atomic_max
:
149 case nir_intrinsic_image_deref_atomic_and
:
150 case nir_intrinsic_image_deref_atomic_or
:
151 case nir_intrinsic_image_deref_atomic_xor
:
152 case nir_intrinsic_image_deref_atomic_exchange
:
153 case nir_intrinsic_image_deref_atomic_comp_swap
:
154 case nir_intrinsic_image_deref_size
:
155 case nir_intrinsic_image_deref_samples
: {
156 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
157 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
159 b
.cursor
= nir_before_instr(&intrin
->instr
);
161 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
162 get_aoa_deref_offset(&b
, deref
, 1));
163 brw_nir_rewrite_image_intrinsic(intrin
, index
);
174 // XXX: need unify_interfaces() at link time...
177 update_so_info(struct pipe_stream_output_info
*so_info
)
179 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
180 struct pipe_stream_output
*output
= &so_info
->output
[i
];
182 /* The VUE header contains three scalar fields packed together:
183 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
184 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
185 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
187 switch (output
->register_index
) {
188 case VARYING_SLOT_LAYER
:
189 assert(output
->num_components
== 1);
190 output
->register_index
= VARYING_SLOT_PSIZ
;
191 output
->start_component
= 1;
193 case VARYING_SLOT_VIEWPORT
:
194 assert(output
->num_components
== 1);
195 output
->register_index
= VARYING_SLOT_PSIZ
;
196 output
->start_component
= 2;
198 case VARYING_SLOT_PSIZ
:
199 assert(output
->num_components
== 1);
200 output
->start_component
= 3;
204 //info->outputs_written |= 1ull << output->register_index;
209 * The pipe->create_[stage]_state() driver hooks.
211 * Performs basic NIR preprocessing, records any state dependencies, and
212 * returns an iris_uncompiled_shader as the Gallium CSO.
214 * Actual shader compilation to assembly happens later, at first use.
217 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
219 const struct pipe_stream_output_info
*so_info
)
221 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
222 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
224 struct iris_uncompiled_shader
*ish
=
225 calloc(1, sizeof(struct iris_uncompiled_shader
));
229 nir
= brw_preprocess_nir(screen
->compiler
, nir
);
231 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
232 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
234 ish
->program_id
= get_new_program_id(screen
);
237 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
238 update_so_info(&ish
->stream_output
);
244 static struct iris_uncompiled_shader
*
245 iris_create_shader_state(struct pipe_context
*ctx
,
246 const struct pipe_shader_state
*state
)
248 assert(state
->type
== PIPE_SHADER_IR_NIR
);
250 return iris_create_uncompiled_shader(ctx
, state
->ir
.nir
,
251 &state
->stream_output
);
255 iris_create_vs_state(struct pipe_context
*ctx
,
256 const struct pipe_shader_state
*state
)
258 struct iris_context
*ice
= (void *) ctx
;
259 struct iris_screen
*screen
= (void *) ctx
->screen
;
260 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
262 /* User clip planes */
263 if (ish
->nir
->info
.clip_distance_array_size
== 0)
264 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
266 if (screen
->precompile
) {
267 struct brw_vs_prog_key key
= { KEY_INIT
};
269 iris_compile_vs(ice
, ish
, &key
);
276 iris_create_tcs_state(struct pipe_context
*ctx
,
277 const struct pipe_shader_state
*state
)
279 struct iris_context
*ice
= (void *) ctx
;
280 struct iris_screen
*screen
= (void *) ctx
->screen
;
281 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
282 struct shader_info
*info
= &ish
->nir
->info
;
286 if (screen
->precompile
) {
287 const unsigned _GL_TRIANGLES
= 0x0004;
288 struct brw_tcs_prog_key key
= {
290 // XXX: make sure the linker fills this out from the TES...
291 .tes_primitive_mode
=
292 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
294 .outputs_written
= info
->outputs_written
,
295 .patch_outputs_written
= info
->patch_outputs_written
,
298 iris_compile_tcs(ice
, ish
, &key
);
305 iris_create_tes_state(struct pipe_context
*ctx
,
306 const struct pipe_shader_state
*state
)
308 struct iris_context
*ice
= (void *) ctx
;
309 struct iris_screen
*screen
= (void *) ctx
->screen
;
310 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
311 struct shader_info
*info
= &ish
->nir
->info
;
315 if (screen
->precompile
) {
316 struct brw_tes_prog_key key
= {
318 // XXX: not ideal, need TCS output/TES input unification
319 .inputs_read
= info
->inputs_read
,
320 .patch_inputs_read
= info
->patch_inputs_read
,
323 iris_compile_tes(ice
, ish
, &key
);
330 iris_create_gs_state(struct pipe_context
*ctx
,
331 const struct pipe_shader_state
*state
)
333 struct iris_context
*ice
= (void *) ctx
;
334 struct iris_screen
*screen
= (void *) ctx
->screen
;
335 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
339 if (screen
->precompile
) {
340 struct brw_gs_prog_key key
= { KEY_INIT
};
342 iris_compile_gs(ice
, ish
, &key
);
349 iris_create_fs_state(struct pipe_context
*ctx
,
350 const struct pipe_shader_state
*state
)
352 struct iris_context
*ice
= (void *) ctx
;
353 struct iris_screen
*screen
= (void *) ctx
->screen
;
354 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
355 struct shader_info
*info
= &ish
->nir
->info
;
357 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
358 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
359 (1ull << IRIS_NOS_RASTERIZER
) |
360 (1ull << IRIS_NOS_BLEND
);
362 /* The program key needs the VUE map if there are > 16 inputs */
363 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
364 BRW_FS_VARYING_INPUT_MASK
) > 16) {
365 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
368 if (screen
->precompile
) {
369 const uint64_t color_outputs
= info
->outputs_written
&
370 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
371 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
372 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
374 bool can_rearrange_varyings
=
375 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
377 struct brw_wm_prog_key key
= {
379 .nr_color_regions
= util_bitcount(color_outputs
),
380 .coherent_fb_fetch
= true,
382 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
385 iris_compile_fs(ice
, ish
, &key
, NULL
);
392 iris_create_compute_state(struct pipe_context
*ctx
,
393 const struct pipe_compute_state
*state
)
395 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
397 struct iris_context
*ice
= (void *) ctx
;
398 struct iris_screen
*screen
= (void *) ctx
->screen
;
399 struct iris_uncompiled_shader
*ish
=
400 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
402 // XXX: disallow more than 64KB of shared variables
404 if (screen
->precompile
) {
405 struct brw_cs_prog_key key
= { KEY_INIT
};
407 iris_compile_cs(ice
, ish
, &key
);
414 * The pipe->delete_[stage]_state() driver hooks.
416 * Frees the iris_uncompiled_shader.
419 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
421 struct iris_uncompiled_shader
*ish
= state
;
423 ralloc_free(ish
->nir
);
428 * The pipe->bind_[stage]_state() driver hook.
430 * Binds an uncompiled shader as the current one for a particular stage.
431 * Updates dirty tracking to account for the shader's NOS.
434 bind_state(struct iris_context
*ice
,
435 struct iris_uncompiled_shader
*ish
,
436 gl_shader_stage stage
)
438 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
439 const uint64_t nos
= ish
? ish
->nos
: 0;
441 ice
->shaders
.uncompiled
[stage
] = ish
;
442 ice
->state
.dirty
|= dirty_bit
;
444 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
445 * (or that they no longer need to do so).
447 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
449 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
451 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
456 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
458 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
462 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
464 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
468 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
470 struct iris_context
*ice
= (struct iris_context
*)ctx
;
472 /* Enabling/disabling optional stages requires a URB reconfiguration. */
473 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
474 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
476 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
480 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
482 struct iris_context
*ice
= (struct iris_context
*)ctx
;
484 /* Enabling/disabling optional stages requires a URB reconfiguration. */
485 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
486 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
488 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
492 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
494 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
498 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
500 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
504 * Sets up the starting offsets for the groups of binding table entries
505 * common to all pipeline stages.
507 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
508 * unused but also make sure that addition of small offsets to them will
509 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
512 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
513 const struct nir_shader
*nir
,
514 struct brw_stage_prog_data
*prog_data
,
515 uint32_t next_binding_table_offset
,
516 unsigned num_system_values
)
518 const struct shader_info
*info
= &nir
->info
;
520 if (info
->num_textures
) {
521 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
522 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
523 next_binding_table_offset
+= info
->num_textures
;
525 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
526 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
529 if (info
->num_images
) {
530 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
531 next_binding_table_offset
+= info
->num_images
;
533 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
536 int num_ubos
= info
->num_ubos
+
537 ((nir
->num_uniforms
|| num_system_values
) ? 1 : 0);
540 //assert(info->num_ubos <= BRW_MAX_UBO);
541 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
542 next_binding_table_offset
+= num_ubos
;
544 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
547 if (info
->num_ssbos
|| info
->num_abos
) {
548 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
549 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
550 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
552 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
555 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
557 /* Plane 0 is just the regular texture section */
558 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
560 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
561 next_binding_table_offset
+= info
->num_textures
;
563 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
564 next_binding_table_offset
+= info
->num_textures
;
566 /* Set the binding table size */
567 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
569 return next_binding_table_offset
;
573 * Associate NIR uniform variables with the prog_data->param[] mechanism
574 * used by the backend. Also, decide which UBOs we'd like to push in an
575 * ideal situation (though the backend can reduce this).
578 iris_setup_uniforms(const struct brw_compiler
*compiler
,
581 struct brw_stage_prog_data
*prog_data
,
582 enum brw_param_builtin
**out_system_values
,
583 unsigned *out_num_system_values
)
585 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
586 * about it for compute shaders, so go ahead and make some fake ones
587 * which the backend will dead code eliminate.
589 prog_data
->nr_params
= nir
->num_uniforms
;
590 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
592 /* The intel compiler assumes that num_uniforms is in bytes. For
593 * scalar that means 4 bytes per uniform slot.
595 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
597 nir
->num_uniforms
*= 4;
599 const unsigned IRIS_MAX_SYSTEM_VALUES
= 32;
600 enum brw_param_builtin
*system_values
=
601 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
602 unsigned num_system_values
= 0;
604 unsigned patch_vert_idx
= -1;
605 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
606 memset(ucp_idx
, -1, sizeof(ucp_idx
));
608 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
611 nir_builder_init(&b
, impl
);
613 b
.cursor
= nir_before_block(nir_start_block(impl
));
614 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
616 /* Turn system value intrinsics into uniforms */
617 nir_foreach_block(block
, impl
) {
618 nir_foreach_instr_safe(instr
, block
) {
619 if (instr
->type
!= nir_instr_type_intrinsic
)
622 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
625 switch (intrin
->intrinsic
) {
626 case nir_intrinsic_load_user_clip_plane
: {
627 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
629 if (ucp_idx
[ucp
] == -1) {
630 ucp_idx
[ucp
] = num_system_values
;
631 num_system_values
+= 4;
634 for (int i
= 0; i
< 4; i
++) {
635 system_values
[ucp_idx
[ucp
] + i
] =
636 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
639 b
.cursor
= nir_before_instr(instr
);
640 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
643 case nir_intrinsic_load_patch_vertices_in
:
644 if (patch_vert_idx
== -1)
645 patch_vert_idx
= num_system_values
++;
647 system_values
[patch_vert_idx
] =
648 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
650 b
.cursor
= nir_before_instr(instr
);
651 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
657 unsigned comps
= nir_intrinsic_dest_components(intrin
);
659 nir_intrinsic_instr
*load
=
660 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
661 load
->num_components
= comps
;
662 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
663 load
->src
[1] = nir_src_for_ssa(offset
);
664 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
665 nir_builder_instr_insert(&b
, &load
->instr
);
666 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
667 nir_src_for_ssa(&load
->dest
.ssa
));
668 nir_instr_remove(instr
);
672 nir_validate_shader(nir
, "before remapping");
674 /* Place the new params at the front of constant buffer 0. */
675 if (num_system_values
> 0) {
676 nir
->num_uniforms
+= num_system_values
* sizeof(uint32_t);
678 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
681 nir_foreach_block(block
, impl
) {
682 nir_foreach_instr_safe(instr
, block
) {
683 if (instr
->type
!= nir_instr_type_intrinsic
)
686 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
688 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
691 b
.cursor
= nir_before_instr(instr
);
693 assert(load
->src
[0].is_ssa
);
695 if (load
->src
[0].ssa
== temp_ubo_name
) {
696 nir_instr_rewrite_src(instr
, &load
->src
[0],
697 nir_src_for_ssa(nir_imm_int(&b
, 0)));
698 } else if (nir_src_as_uint(load
->src
[0]) == 0) {
699 nir_ssa_def
*offset
=
700 nir_iadd(&b
, load
->src
[1].ssa
,
701 nir_imm_int(&b
, 4 * num_system_values
));
702 nir_instr_rewrite_src(instr
, &load
->src
[1],
703 nir_src_for_ssa(offset
));
708 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
709 nir_opt_constant_folding(nir
);
711 ralloc_free(system_values
);
712 system_values
= NULL
;
715 nir_validate_shader(nir
, "after remap");
717 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
718 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
720 *out_system_values
= system_values
;
721 *out_num_system_values
= num_system_values
;
725 * Compile a vertex shader, and upload the assembly.
727 static struct iris_compiled_shader
*
728 iris_compile_vs(struct iris_context
*ice
,
729 struct iris_uncompiled_shader
*ish
,
730 const struct brw_vs_prog_key
*key
)
732 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
733 const struct brw_compiler
*compiler
= screen
->compiler
;
734 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
735 void *mem_ctx
= ralloc_context(NULL
);
736 struct brw_vs_prog_data
*vs_prog_data
=
737 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
738 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
739 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
740 enum brw_param_builtin
*system_values
;
741 unsigned num_system_values
;
743 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
745 if (key
->nr_userclip_plane_consts
) {
746 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
747 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
748 nir_lower_io_to_temporaries(nir
, impl
, true, false);
749 nir_lower_global_vars_to_local(nir
);
750 nir_lower_vars_to_ssa(nir
);
751 nir_shader_gather_info(nir
, impl
);
756 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
759 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
762 brw_compute_vue_map(devinfo
,
763 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
764 nir
->info
.separate_shader
);
766 /* Don't tell the backend about our clip plane constants, we've already
767 * lowered them in NIR and we don't want it doing it again.
769 struct brw_vs_prog_key key_no_ucp
= *key
;
770 key_no_ucp
.nr_userclip_plane_consts
= 0;
772 char *error_str
= NULL
;
773 const unsigned *program
=
774 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
775 nir
, -1, &error_str
);
776 if (program
== NULL
) {
777 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
778 ralloc_free(mem_ctx
);
783 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
784 &vue_prog_data
->vue_map
);
786 struct iris_compiled_shader
*shader
=
787 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
788 prog_data
, so_decls
, system_values
, num_system_values
);
790 if (ish
->compiled_once
) {
791 perf_debug(&ice
->dbg
, "Recompiling vertex shader\n");
793 ish
->compiled_once
= true;
796 ralloc_free(mem_ctx
);
801 * Update the current vertex shader variant.
803 * Fill out the key, look in the cache, compile and bind if needed.
806 iris_update_compiled_vs(struct iris_context
*ice
)
808 struct iris_uncompiled_shader
*ish
=
809 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
811 struct brw_vs_prog_key key
= { KEY_INIT
};
812 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
814 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
815 struct iris_compiled_shader
*shader
=
816 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
819 shader
= iris_compile_vs(ice
, ish
, &key
);
822 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
823 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
824 IRIS_DIRTY_BINDINGS_VS
|
825 IRIS_DIRTY_CONSTANTS_VS
|
831 * Get the shader_info for a given stage, or NULL if the stage is disabled.
833 const struct shader_info
*
834 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
836 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
841 const nir_shader
*nir
= ish
->nir
;
845 // XXX: this function is gross
847 iris_get_shader_num_ubos(const struct iris_context
*ice
, gl_shader_stage stage
)
849 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
850 const struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
853 const nir_shader
*nir
= ish
->nir
;
854 /* see assign_common_binding_table_offsets */
855 return nir
->info
.num_ubos
+
856 ((nir
->num_uniforms
|| shader
->num_system_values
) ? 1 : 0);
862 * Get the union of TCS output and TES input slots.
864 * TCS and TES need to agree on a common URB entry layout. In particular,
865 * the data for all patch vertices is stored in a single URB entry (unlike
866 * GS which has one entry per input vertex). This means that per-vertex
867 * array indexing needs a stride.
869 * SSO requires locations to match, but doesn't require the number of
870 * outputs/inputs to match (in fact, the TCS often has extra outputs).
871 * So, we need to take the extra step of unifying these on the fly.
874 get_unified_tess_slots(const struct iris_context
*ice
,
875 uint64_t *per_vertex_slots
,
876 uint32_t *per_patch_slots
)
878 const struct shader_info
*tcs
=
879 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
880 const struct shader_info
*tes
=
881 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
883 *per_vertex_slots
= tes
->inputs_read
;
884 *per_patch_slots
= tes
->patch_inputs_read
;
887 *per_vertex_slots
|= tcs
->outputs_written
;
888 *per_patch_slots
|= tcs
->patch_outputs_written
;
893 * Compile a tessellation control shader, and upload the assembly.
895 static struct iris_compiled_shader
*
896 iris_compile_tcs(struct iris_context
*ice
,
897 struct iris_uncompiled_shader
*ish
,
898 const struct brw_tcs_prog_key
*key
)
900 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
901 const struct brw_compiler
*compiler
= screen
->compiler
;
902 const struct nir_shader_compiler_options
*options
=
903 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
904 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
905 void *mem_ctx
= ralloc_context(NULL
);
906 struct brw_tcs_prog_data
*tcs_prog_data
=
907 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
908 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
909 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
910 enum brw_param_builtin
*system_values
= NULL
;
911 unsigned num_system_values
= 0;
916 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
918 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
920 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
923 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
925 /* Reserve space for passing the default tess levels as constants. */
926 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
927 prog_data
->nr_params
= 8;
928 prog_data
->ubo_ranges
[0].length
= 1;
931 char *error_str
= NULL
;
932 const unsigned *program
=
933 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
935 if (program
== NULL
) {
936 dbg_printf("Failed to compile control shader: %s\n", error_str
);
937 ralloc_free(mem_ctx
);
941 struct iris_compiled_shader
*shader
=
942 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
943 prog_data
, NULL
, system_values
, num_system_values
);
946 if (ish
->compiled_once
) {
947 perf_debug(&ice
->dbg
, "Recompiling tessellation control shader\n");
949 ish
->compiled_once
= true;
953 ralloc_free(mem_ctx
);
958 * Update the current tessellation control shader variant.
960 * Fill out the key, look in the cache, compile and bind if needed.
963 iris_update_compiled_tcs(struct iris_context
*ice
)
965 struct iris_uncompiled_shader
*tcs
=
966 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
968 const struct shader_info
*tes_info
=
969 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
970 struct brw_tcs_prog_key key
= {
972 .program_string_id
= tcs
? tcs
->program_id
: 0,
973 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
974 .input_vertices
= ice
->state
.vertices_per_patch
,
976 get_unified_tess_slots(ice
, &key
.outputs_written
,
977 &key
.patch_outputs_written
);
978 ice
->vtbl
.populate_tcs_key(ice
, &key
);
980 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
981 struct iris_compiled_shader
*shader
=
982 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
985 shader
= iris_compile_tcs(ice
, tcs
, &key
);
988 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
989 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
990 IRIS_DIRTY_BINDINGS_TCS
|
991 IRIS_DIRTY_CONSTANTS_TCS
;
996 * Compile a tessellation evaluation shader, and upload the assembly.
998 static struct iris_compiled_shader
*
999 iris_compile_tes(struct iris_context
*ice
,
1000 struct iris_uncompiled_shader
*ish
,
1001 const struct brw_tes_prog_key
*key
)
1003 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1004 const struct brw_compiler
*compiler
= screen
->compiler
;
1005 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1006 void *mem_ctx
= ralloc_context(NULL
);
1007 struct brw_tes_prog_data
*tes_prog_data
=
1008 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1009 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1010 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1011 enum brw_param_builtin
*system_values
;
1012 unsigned num_system_values
;
1014 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1016 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1017 &num_system_values
);
1019 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
1022 struct brw_vue_map input_vue_map
;
1023 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1024 key
->patch_inputs_read
);
1026 char *error_str
= NULL
;
1027 const unsigned *program
=
1028 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
1029 tes_prog_data
, nir
, NULL
, -1, &error_str
);
1030 if (program
== NULL
) {
1031 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1032 ralloc_free(mem_ctx
);
1036 uint32_t *so_decls
=
1037 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1038 &vue_prog_data
->vue_map
);
1041 struct iris_compiled_shader
*shader
=
1042 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1043 prog_data
, so_decls
, system_values
, num_system_values
);
1045 if (ish
->compiled_once
) {
1046 perf_debug(&ice
->dbg
, "Recompiling tessellation evaluation shader\n");
1048 ish
->compiled_once
= true;
1051 ralloc_free(mem_ctx
);
1056 * Update the current tessellation evaluation shader variant.
1058 * Fill out the key, look in the cache, compile and bind if needed.
1061 iris_update_compiled_tes(struct iris_context
*ice
)
1063 struct iris_uncompiled_shader
*ish
=
1064 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1066 struct brw_tes_prog_key key
= { KEY_INIT
};
1067 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1068 ice
->vtbl
.populate_tes_key(ice
, &key
);
1070 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1071 struct iris_compiled_shader
*shader
=
1072 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1075 shader
= iris_compile_tes(ice
, ish
, &key
);
1077 if (old
!= shader
) {
1078 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1079 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1080 IRIS_DIRTY_BINDINGS_TES
|
1081 IRIS_DIRTY_CONSTANTS_TES
;
1086 * Compile a geometry shader, and upload the assembly.
1088 static struct iris_compiled_shader
*
1089 iris_compile_gs(struct iris_context
*ice
,
1090 struct iris_uncompiled_shader
*ish
,
1091 const struct brw_gs_prog_key
*key
)
1093 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1094 const struct brw_compiler
*compiler
= screen
->compiler
;
1095 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1096 void *mem_ctx
= ralloc_context(NULL
);
1097 struct brw_gs_prog_data
*gs_prog_data
=
1098 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1099 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1100 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1101 enum brw_param_builtin
*system_values
;
1102 unsigned num_system_values
;
1104 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1106 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1107 &num_system_values
);
1109 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
1112 brw_compute_vue_map(devinfo
,
1113 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1114 nir
->info
.separate_shader
);
1116 char *error_str
= NULL
;
1117 const unsigned *program
=
1118 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1119 NULL
, -1, &error_str
);
1120 if (program
== NULL
) {
1121 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1122 ralloc_free(mem_ctx
);
1126 uint32_t *so_decls
=
1127 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1128 &vue_prog_data
->vue_map
);
1130 struct iris_compiled_shader
*shader
=
1131 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1132 prog_data
, so_decls
, system_values
, num_system_values
);
1134 if (ish
->compiled_once
) {
1135 perf_debug(&ice
->dbg
, "Recompiling geometry shader\n");
1137 ish
->compiled_once
= true;
1140 ralloc_free(mem_ctx
);
1145 * Update the current geometry shader variant.
1147 * Fill out the key, look in the cache, compile and bind if needed.
1150 iris_update_compiled_gs(struct iris_context
*ice
)
1152 struct iris_uncompiled_shader
*ish
=
1153 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1154 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1155 struct iris_compiled_shader
*shader
= NULL
;
1158 struct brw_gs_prog_key key
= { KEY_INIT
};
1159 ice
->vtbl
.populate_gs_key(ice
, &key
);
1162 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1165 shader
= iris_compile_gs(ice
, ish
, &key
);
1168 if (old
!= shader
) {
1169 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1170 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1171 IRIS_DIRTY_BINDINGS_GS
|
1172 IRIS_DIRTY_CONSTANTS_GS
;
1177 * Compile a fragment (pixel) shader, and upload the assembly.
1179 static struct iris_compiled_shader
*
1180 iris_compile_fs(struct iris_context
*ice
,
1181 struct iris_uncompiled_shader
*ish
,
1182 const struct brw_wm_prog_key
*key
,
1183 struct brw_vue_map
*vue_map
)
1185 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1186 const struct brw_compiler
*compiler
= screen
->compiler
;
1187 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1188 void *mem_ctx
= ralloc_context(NULL
);
1189 struct brw_wm_prog_data
*fs_prog_data
=
1190 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1191 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1192 enum brw_param_builtin
*system_values
;
1193 unsigned num_system_values
;
1195 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1199 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1200 &num_system_values
);
1202 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
1203 MAX2(key
->nr_color_regions
, 1),
1205 char *error_str
= NULL
;
1206 const unsigned *program
=
1207 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1208 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1209 if (program
== NULL
) {
1210 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1211 ralloc_free(mem_ctx
);
1215 struct iris_compiled_shader
*shader
=
1216 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1217 prog_data
, NULL
, system_values
, num_system_values
);
1219 if (ish
->compiled_once
) {
1220 perf_debug(&ice
->dbg
, "Recompiling fragment shader\n");
1222 ish
->compiled_once
= true;
1225 ralloc_free(mem_ctx
);
1230 * Update the current fragment shader variant.
1232 * Fill out the key, look in the cache, compile and bind if needed.
1235 iris_update_compiled_fs(struct iris_context
*ice
)
1237 struct iris_uncompiled_shader
*ish
=
1238 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1239 struct brw_wm_prog_key key
= { KEY_INIT
};
1240 ice
->vtbl
.populate_fs_key(ice
, &key
);
1242 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1243 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1245 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1246 struct iris_compiled_shader
*shader
=
1247 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1250 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1252 if (old
!= shader
) {
1253 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1254 // toggles. might be able to avoid flagging SBE too.
1255 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1256 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1257 IRIS_DIRTY_BINDINGS_FS
|
1258 IRIS_DIRTY_CONSTANTS_FS
|
1266 * Get the compiled shader for the last enabled geometry stage.
1268 * This stage is the one which will feed stream output and the rasterizer.
1270 static gl_shader_stage
1271 last_vue_stage(struct iris_context
*ice
)
1273 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
1274 return MESA_SHADER_GEOMETRY
;
1276 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
1277 return MESA_SHADER_TESS_EVAL
;
1279 return MESA_SHADER_VERTEX
;
1283 * Update the last enabled stage's VUE map.
1285 * When the shader feeding the rasterizer's output interface changes, we
1286 * need to re-emit various packets.
1289 update_last_vue_map(struct iris_context
*ice
,
1290 struct brw_stage_prog_data
*prog_data
)
1292 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1293 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1294 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1295 const uint64_t changed_slots
=
1296 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1298 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1299 // XXX: could use ctx->Const.MaxViewports for old API efficiency
1300 ice
->state
.num_viewports
=
1301 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1302 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1303 IRIS_DIRTY_SF_CL_VIEWPORT
|
1304 IRIS_DIRTY_CC_VIEWPORT
|
1305 IRIS_DIRTY_SCISSOR_RECT
|
1306 IRIS_DIRTY_UNCOMPILED_FS
|
1307 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1308 // XXX: CC_VIEWPORT?
1311 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1312 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1315 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1319 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1321 static struct brw_vue_prog_data
*
1322 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1324 if (!ice
->shaders
.prog
[stage
])
1327 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1330 // XXX: iris_compiled_shaders are space-leaking :(
1331 // XXX: do remember to unbind them if deleting them.
1334 * Update the current shader variants for the given state.
1336 * This should be called on every draw call to ensure that the correct
1337 * shaders are bound. It will also flag any dirty state triggered by
1338 * swapping out those shaders.
1341 iris_update_compiled_shaders(struct iris_context
*ice
)
1343 const uint64_t dirty
= ice
->state
.dirty
;
1345 struct brw_vue_prog_data
*old_prog_datas
[4];
1346 if (!(dirty
& IRIS_DIRTY_URB
)) {
1347 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1348 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1351 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1352 struct iris_uncompiled_shader
*tes
=
1353 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1355 iris_update_compiled_tcs(ice
);
1356 iris_update_compiled_tes(ice
);
1358 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1359 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1361 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1362 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1363 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1367 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1368 iris_update_compiled_vs(ice
);
1369 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1370 iris_update_compiled_gs(ice
);
1372 gl_shader_stage last_stage
= last_vue_stage(ice
);
1373 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1374 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1375 update_last_vue_map(ice
, shader
->prog_data
);
1376 if (ice
->state
.streamout
!= shader
->streamout
) {
1377 ice
->state
.streamout
= shader
->streamout
;
1378 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1381 if (ice
->state
.streamout_active
) {
1382 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1383 struct iris_stream_output_target
*so
=
1384 (void *) ice
->state
.so_target
[i
];
1386 so
->stride
= ish
->stream_output
.stride
[i
];
1390 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1391 iris_update_compiled_fs(ice
);
1394 /* Changing shader interfaces may require a URB configuration. */
1395 if (!(dirty
& IRIS_DIRTY_URB
)) {
1396 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1397 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1398 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1399 if (!!old
!= !!new ||
1400 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1401 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1408 static struct iris_compiled_shader
*
1409 iris_compile_cs(struct iris_context
*ice
,
1410 struct iris_uncompiled_shader
*ish
,
1411 const struct brw_cs_prog_key
*key
)
1413 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1414 const struct brw_compiler
*compiler
= screen
->compiler
;
1415 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1416 void *mem_ctx
= ralloc_context(NULL
);
1417 struct brw_cs_prog_data
*cs_prog_data
=
1418 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1419 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1420 enum brw_param_builtin
*system_values
;
1421 unsigned num_system_values
;
1423 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1425 cs_prog_data
->binding_table
.work_groups_start
= 0;
1427 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1429 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1430 &num_system_values
);
1432 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1,
1435 char *error_str
= NULL
;
1436 const unsigned *program
=
1437 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1438 nir
, -1, &error_str
);
1439 if (program
== NULL
) {
1440 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1441 ralloc_free(mem_ctx
);
1445 struct iris_compiled_shader
*shader
=
1446 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1447 prog_data
, NULL
, system_values
, num_system_values
);
1449 if (ish
->compiled_once
) {
1450 perf_debug(&ice
->dbg
, "Recompiling compute shader\n");
1452 ish
->compiled_once
= true;
1455 ralloc_free(mem_ctx
);
1460 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1462 struct iris_uncompiled_shader
*ish
=
1463 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1465 struct brw_cs_prog_key key
= { KEY_INIT
};
1466 ice
->vtbl
.populate_cs_key(ice
, &key
);
1468 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1469 struct iris_compiled_shader
*shader
=
1470 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1473 shader
= iris_compile_cs(ice
, ish
, &key
);
1475 if (old
!= shader
) {
1476 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1477 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1478 IRIS_DIRTY_BINDINGS_CS
|
1479 IRIS_DIRTY_CONSTANTS_CS
;
1484 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1487 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1488 assert(cs_prog_data
->push
.total
.size
> 0);
1489 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1490 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1491 assert(prog_data
->param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1492 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1497 * Allocate scratch BOs as needed for the given per-thread size and stage.
1500 iris_get_scratch_space(struct iris_context
*ice
,
1501 unsigned per_thread_scratch
,
1502 gl_shader_stage stage
)
1504 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1505 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1506 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1508 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1509 assert(encoded_size
< (1 << 16));
1511 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1513 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1515 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1516 * must allocate scratch space enough so that each slice has 4
1519 * According to the other driver team, this applies to compute shaders
1520 * as well. This is not currently documented at all.
1522 * This hack is no longer necessary on Gen11+.
1524 unsigned subslice_total
= screen
->subslice_total
;
1525 if (devinfo
->gen
< 11)
1526 subslice_total
= 4 * devinfo
->num_slices
;
1527 assert(subslice_total
>= screen
->subslice_total
);
1530 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1531 uint32_t max_threads
[] = {
1532 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1533 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1534 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1535 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1536 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1537 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1540 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1542 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1549 iris_init_program_functions(struct pipe_context
*ctx
)
1551 ctx
->create_vs_state
= iris_create_vs_state
;
1552 ctx
->create_tcs_state
= iris_create_tcs_state
;
1553 ctx
->create_tes_state
= iris_create_tes_state
;
1554 ctx
->create_gs_state
= iris_create_gs_state
;
1555 ctx
->create_fs_state
= iris_create_fs_state
;
1556 ctx
->create_compute_state
= iris_create_compute_state
;
1558 ctx
->delete_vs_state
= iris_delete_shader_state
;
1559 ctx
->delete_tcs_state
= iris_delete_shader_state
;
1560 ctx
->delete_tes_state
= iris_delete_shader_state
;
1561 ctx
->delete_gs_state
= iris_delete_shader_state
;
1562 ctx
->delete_fs_state
= iris_delete_shader_state
;
1563 ctx
->delete_compute_state
= iris_delete_shader_state
;
1565 ctx
->bind_vs_state
= iris_bind_vs_state
;
1566 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1567 ctx
->bind_tes_state
= iris_bind_tes_state
;
1568 ctx
->bind_gs_state
= iris_bind_gs_state
;
1569 ctx
->bind_fs_state
= iris_bind_fs_state
;
1570 ctx
->bind_compute_state
= iris_bind_cs_state
;