2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "compiler/nir/nir.h"
41 #include "compiler/nir/nir_builder.h"
42 #include "compiler/nir/nir_serialize.h"
43 #include "intel/compiler/brw_compiler.h"
44 #include "intel/compiler/brw_nir.h"
45 #include "iris_context.h"
46 #include "nir/tgsi_to_nir.h"
48 #define KEY_INIT_NO_ID(gen) \
49 .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
50 .tex.compressed_multisample_layout_mask = ~0, \
51 .tex.msaa_16 = (gen >= 9 ? ~0 : 0)
52 #define KEY_INIT(gen) .program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
55 get_new_program_id(struct iris_screen
*screen
)
57 return p_atomic_inc_return(&screen
->program_id
);
61 upload_state(struct u_upload_mgr
*uploader
,
62 struct iris_state_ref
*ref
,
67 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
72 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
73 struct pipe_shader_buffer
*buf
,
74 struct iris_state_ref
*surf_state
,
77 struct pipe_context
*ctx
= &ice
->ctx
;
78 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
80 // XXX: these are not retained forever, use a separate uploader?
82 upload_state(ice
->state
.surface_uploader
, surf_state
,
83 screen
->isl_dev
.ss
.size
, 64);
85 surf_state
->res
= NULL
;
89 struct iris_resource
*res
= (void *) buf
->buffer
;
90 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
91 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
93 isl_buffer_fill_state(&screen
->isl_dev
, map
,
94 .address
= res
->bo
->gtt_offset
+ res
->offset
+
96 .size_B
= buf
->buffer_size
- res
->offset
,
97 .format
= ssbo
? ISL_FORMAT_RAW
98 : ISL_FORMAT_R32G32B32A32_FLOAT
,
99 .swizzle
= ISL_SWIZZLE_IDENTITY
,
101 .mocs
= ice
->vtbl
.mocs(res
->bo
));
105 get_aoa_deref_offset(nir_builder
*b
,
106 nir_deref_instr
*deref
,
109 unsigned array_size
= elem_size
;
110 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
112 while (deref
->deref_type
!= nir_deref_type_var
) {
113 assert(deref
->deref_type
== nir_deref_type_array
);
115 /* This level's element size is the previous level's array size */
116 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
117 assert(deref
->arr
.index
.ssa
);
118 offset
= nir_iadd(b
, offset
,
119 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
121 deref
= nir_deref_instr_parent(deref
);
122 assert(glsl_type_is_array(deref
->type
));
123 array_size
*= glsl_get_length(deref
->type
);
126 /* Accessing an invalid surface index with the dataport can result in a
127 * hang. According to the spec "if the index used to select an individual
128 * element is negative or greater than or equal to the size of the array,
129 * the results of the operation are undefined but may not lead to
130 * termination" -- which is one of the possible outcomes of the hang.
131 * Clamp the index to prevent access outside of the array bounds.
133 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
137 iris_lower_storage_image_derefs(nir_shader
*nir
)
139 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
142 nir_builder_init(&b
, impl
);
144 nir_foreach_block(block
, impl
) {
145 nir_foreach_instr_safe(instr
, block
) {
146 if (instr
->type
!= nir_instr_type_intrinsic
)
149 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
150 switch (intrin
->intrinsic
) {
151 case nir_intrinsic_image_deref_load
:
152 case nir_intrinsic_image_deref_store
:
153 case nir_intrinsic_image_deref_atomic_add
:
154 case nir_intrinsic_image_deref_atomic_min
:
155 case nir_intrinsic_image_deref_atomic_max
:
156 case nir_intrinsic_image_deref_atomic_and
:
157 case nir_intrinsic_image_deref_atomic_or
:
158 case nir_intrinsic_image_deref_atomic_xor
:
159 case nir_intrinsic_image_deref_atomic_exchange
:
160 case nir_intrinsic_image_deref_atomic_comp_swap
:
161 case nir_intrinsic_image_deref_size
:
162 case nir_intrinsic_image_deref_samples
:
163 case nir_intrinsic_image_deref_load_raw_intel
:
164 case nir_intrinsic_image_deref_store_raw_intel
: {
165 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
166 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
168 b
.cursor
= nir_before_instr(&intrin
->instr
);
170 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
171 get_aoa_deref_offset(&b
, deref
, 1));
172 nir_rewrite_image_intrinsic(intrin
, index
, false);
183 // XXX: need unify_interfaces() at link time...
186 * Fix an uncompiled shader's stream output info.
188 * Core Gallium stores output->register_index as a "slot" number, where
189 * slots are assigned consecutively to all outputs in info->outputs_written.
190 * This naive packing of outputs doesn't work for us - we too have slots,
191 * but the layout is defined by the VUE map, which we won't have until we
192 * compile a specific shader variant. So, we remap these and simply store
193 * VARYING_SLOT_* in our copy's output->register_index fields.
195 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
196 * components of our VUE header. See brw_vue_map.c for the layout.
199 update_so_info(struct pipe_stream_output_info
*so_info
,
200 uint64_t outputs_written
)
202 uint8_t reverse_map
[64] = {};
204 while (outputs_written
) {
205 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
208 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
209 struct pipe_stream_output
*output
= &so_info
->output
[i
];
211 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
212 output
->register_index
= reverse_map
[output
->register_index
];
214 /* The VUE header contains three scalar fields packed together:
215 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
216 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
217 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
219 switch (output
->register_index
) {
220 case VARYING_SLOT_LAYER
:
221 assert(output
->num_components
== 1);
222 output
->register_index
= VARYING_SLOT_PSIZ
;
223 output
->start_component
= 1;
225 case VARYING_SLOT_VIEWPORT
:
226 assert(output
->num_components
== 1);
227 output
->register_index
= VARYING_SLOT_PSIZ
;
228 output
->start_component
= 2;
230 case VARYING_SLOT_PSIZ
:
231 assert(output
->num_components
== 1);
232 output
->start_component
= 3;
236 //info->outputs_written |= 1ull << output->register_index;
241 * Sets up the starting offsets for the groups of binding table entries
242 * common to all pipeline stages.
244 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
245 * unused but also make sure that addition of small offsets to them will
246 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
249 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
250 const struct nir_shader
*nir
,
251 struct brw_stage_prog_data
*prog_data
,
252 uint32_t next_binding_table_offset
,
253 unsigned num_system_values
,
256 const struct shader_info
*info
= &nir
->info
;
258 unsigned num_textures
= util_last_bit(info
->textures_used
);
261 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
262 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
263 next_binding_table_offset
+= num_textures
;
265 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
266 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
269 if (info
->num_images
) {
270 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
271 next_binding_table_offset
+= info
->num_images
;
273 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
277 //assert(info->num_ubos <= BRW_MAX_UBO);
278 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
279 next_binding_table_offset
+= num_cbufs
;
281 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
284 if (info
->num_ssbos
|| info
->num_abos
) {
285 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
286 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
287 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
289 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
292 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
294 /* Plane 0 is just the regular texture section */
295 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
297 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
298 next_binding_table_offset
+= num_textures
;
300 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
301 next_binding_table_offset
+= num_textures
;
303 /* Set the binding table size */
304 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
306 return next_binding_table_offset
;
310 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
311 unsigned offset
, unsigned n
)
313 assert(offset
% sizeof(uint32_t) == 0);
315 for (unsigned i
= 0; i
< n
; ++i
)
316 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
318 for (unsigned i
= n
; i
< 4; ++i
)
319 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
323 * Associate NIR uniform variables with the prog_data->param[] mechanism
324 * used by the backend. Also, decide which UBOs we'd like to push in an
325 * ideal situation (though the backend can reduce this).
328 iris_setup_uniforms(const struct brw_compiler
*compiler
,
331 struct brw_stage_prog_data
*prog_data
,
332 enum brw_param_builtin
**out_system_values
,
333 unsigned *out_num_system_values
,
334 unsigned *out_num_cbufs
)
336 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
338 /* The intel compiler assumes that num_uniforms is in bytes. For
339 * scalar that means 4 bytes per uniform slot.
341 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
343 nir
->num_uniforms
*= 4;
345 const unsigned IRIS_MAX_SYSTEM_VALUES
=
346 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
347 enum brw_param_builtin
*system_values
=
348 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
349 unsigned num_system_values
= 0;
351 unsigned patch_vert_idx
= -1;
352 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
353 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
354 memset(ucp_idx
, -1, sizeof(ucp_idx
));
355 memset(img_idx
, -1, sizeof(img_idx
));
357 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
360 nir_builder_init(&b
, impl
);
362 b
.cursor
= nir_before_block(nir_start_block(impl
));
363 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
365 /* Turn system value intrinsics into uniforms */
366 nir_foreach_block(block
, impl
) {
367 nir_foreach_instr_safe(instr
, block
) {
368 if (instr
->type
!= nir_instr_type_intrinsic
)
371 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
374 switch (intrin
->intrinsic
) {
375 case nir_intrinsic_load_user_clip_plane
: {
376 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
378 if (ucp_idx
[ucp
] == -1) {
379 ucp_idx
[ucp
] = num_system_values
;
380 num_system_values
+= 4;
383 for (int i
= 0; i
< 4; i
++) {
384 system_values
[ucp_idx
[ucp
] + i
] =
385 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
388 b
.cursor
= nir_before_instr(instr
);
389 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
392 case nir_intrinsic_load_patch_vertices_in
:
393 if (patch_vert_idx
== -1)
394 patch_vert_idx
= num_system_values
++;
396 system_values
[patch_vert_idx
] =
397 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
399 b
.cursor
= nir_before_instr(instr
);
400 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
402 case nir_intrinsic_image_deref_load_param_intel
: {
403 assert(devinfo
->gen
< 9);
404 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
405 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
407 /* XXX: var->data.binding is not set properly. We need to run
408 * some form of gl_nir_lower_samplers_as_deref() to get it.
409 * This breaks tests which use more than one image.
411 if (img_idx
[var
->data
.binding
] == -1) {
412 /* GL only allows arrays of arrays of images. */
413 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
414 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
416 for (int i
= 0; i
< num_images
; i
++) {
417 const unsigned img
= var
->data
.binding
+ i
;
419 img_idx
[img
] = num_system_values
;
420 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
422 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
424 setup_vec4_image_sysval(
425 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
426 offsetof(struct brw_image_param
, offset
), 2);
427 setup_vec4_image_sysval(
428 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
429 offsetof(struct brw_image_param
, size
), 3);
430 setup_vec4_image_sysval(
431 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
432 offsetof(struct brw_image_param
, stride
), 4);
433 setup_vec4_image_sysval(
434 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
435 offsetof(struct brw_image_param
, tiling
), 3);
436 setup_vec4_image_sysval(
437 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
438 offsetof(struct brw_image_param
, swizzling
), 2);
442 b
.cursor
= nir_before_instr(instr
);
443 offset
= nir_iadd(&b
,
444 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
445 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
446 nir_intrinsic_base(intrin
) * 16));
453 unsigned comps
= nir_intrinsic_dest_components(intrin
);
455 nir_intrinsic_instr
*load
=
456 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
457 load
->num_components
= comps
;
458 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
459 load
->src
[1] = nir_src_for_ssa(offset
);
460 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
461 nir_builder_instr_insert(&b
, &load
->instr
);
462 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
463 nir_src_for_ssa(&load
->dest
.ssa
));
464 nir_instr_remove(instr
);
468 nir_validate_shader(nir
, "before remapping");
470 /* Place the new params at the front of constant buffer 0. */
471 if (num_system_values
> 0) {
472 nir
->num_uniforms
+= num_system_values
* sizeof(uint32_t);
474 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
477 nir_foreach_block(block
, impl
) {
478 nir_foreach_instr_safe(instr
, block
) {
479 if (instr
->type
!= nir_instr_type_intrinsic
)
482 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
484 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
487 b
.cursor
= nir_before_instr(instr
);
489 assert(load
->src
[0].is_ssa
);
491 if (load
->src
[0].ssa
== temp_ubo_name
) {
492 nir_instr_rewrite_src(instr
, &load
->src
[0],
493 nir_src_for_ssa(nir_imm_int(&b
, 0)));
494 } else if (nir_src_is_const(load
->src
[0]) &&
495 nir_src_as_uint(load
->src
[0]) == 0) {
496 nir_ssa_def
*offset
=
497 nir_iadd(&b
, load
->src
[1].ssa
,
498 nir_imm_int(&b
, 4 * num_system_values
));
499 nir_instr_rewrite_src(instr
, &load
->src
[1],
500 nir_src_for_ssa(offset
));
505 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
506 nir_opt_constant_folding(nir
);
508 ralloc_free(system_values
);
509 system_values
= NULL
;
512 nir_validate_shader(nir
, "after remap");
514 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
515 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
517 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
518 * about it for compute shaders, so go ahead and make some fake ones
519 * which the backend will dead code eliminate.
521 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
522 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
524 /* System values and uniforms are stored in constant buffer 0, the
525 * user-facing UBOs are indexed by one. So if any constant buffer is
526 * needed, the constant buffer 0 will be needed, so account for it.
528 unsigned num_cbufs
= nir
->info
.num_ubos
;
529 if (num_cbufs
|| num_system_values
|| nir
->num_uniforms
)
532 *out_system_values
= system_values
;
533 *out_num_system_values
= num_system_values
;
534 *out_num_cbufs
= num_cbufs
;
538 iris_debug_recompile(struct iris_context
*ice
,
539 struct shader_info
*info
,
540 unsigned program_string_id
,
543 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
544 const struct brw_compiler
*c
= screen
->compiler
;
549 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
550 _mesa_shader_stage_to_string(info
->stage
),
551 info
->name
? info
->name
: "(no identifier)",
552 info
->label
? info
->label
: "");
554 const void *old_key
=
555 iris_find_previous_compile(ice
, info
->stage
, program_string_id
);
557 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
562 * Compile a vertex shader, and upload the assembly.
564 static struct iris_compiled_shader
*
565 iris_compile_vs(struct iris_context
*ice
,
566 struct iris_uncompiled_shader
*ish
,
567 const struct brw_vs_prog_key
*key
)
569 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
570 const struct brw_compiler
*compiler
= screen
->compiler
;
571 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
572 void *mem_ctx
= ralloc_context(NULL
);
573 struct brw_vs_prog_data
*vs_prog_data
=
574 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
575 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
576 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
577 enum brw_param_builtin
*system_values
;
578 unsigned num_system_values
;
581 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
583 if (key
->nr_userclip_plane_consts
) {
584 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
585 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
586 nir_lower_io_to_temporaries(nir
, impl
, true, false);
587 nir_lower_global_vars_to_local(nir
);
588 nir_lower_vars_to_ssa(nir
);
589 nir_shader_gather_info(nir
, impl
);
592 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
594 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
595 &num_system_values
, &num_cbufs
);
597 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
598 num_system_values
, num_cbufs
);
600 brw_compute_vue_map(devinfo
,
601 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
602 nir
->info
.separate_shader
);
604 /* Don't tell the backend about our clip plane constants, we've already
605 * lowered them in NIR and we don't want it doing it again.
607 struct brw_vs_prog_key key_no_ucp
= *key
;
608 key_no_ucp
.nr_userclip_plane_consts
= 0;
610 char *error_str
= NULL
;
611 const unsigned *program
=
612 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
613 nir
, -1, &error_str
);
614 if (program
== NULL
) {
615 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
616 ralloc_free(mem_ctx
);
620 if (ish
->compiled_once
) {
621 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
623 ish
->compiled_once
= true;
627 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
628 &vue_prog_data
->vue_map
);
630 struct iris_compiled_shader
*shader
=
631 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
632 prog_data
, so_decls
, system_values
, num_system_values
,
635 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
637 ralloc_free(mem_ctx
);
642 * Update the current vertex shader variant.
644 * Fill out the key, look in the cache, compile and bind if needed.
647 iris_update_compiled_vs(struct iris_context
*ice
)
649 struct iris_uncompiled_shader
*ish
=
650 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
651 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
652 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
654 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
655 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
657 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
658 struct iris_compiled_shader
*shader
=
659 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
662 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
665 shader
= iris_compile_vs(ice
, ish
, &key
);
668 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
669 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
670 IRIS_DIRTY_BINDINGS_VS
|
671 IRIS_DIRTY_CONSTANTS_VS
|
673 const struct brw_vs_prog_data
*vs_prog_data
=
674 (void *) shader
->prog_data
;
675 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
676 vs_prog_data
->uses_baseinstance
;
677 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
678 vs_prog_data
->uses_is_indexed_draw
;
679 const bool needs_sgvs_element
= uses_draw_params
||
680 vs_prog_data
->uses_instanceid
||
681 vs_prog_data
->uses_vertexid
;
682 bool needs_edge_flag
= false;
683 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
684 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
685 needs_edge_flag
= true;
688 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
689 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
690 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
691 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
692 IRIS_DIRTY_VERTEX_ELEMENTS
;
694 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
695 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
696 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
697 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
702 * Get the shader_info for a given stage, or NULL if the stage is disabled.
704 const struct shader_info
*
705 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
707 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
712 const nir_shader
*nir
= ish
->nir
;
717 * Get the union of TCS output and TES input slots.
719 * TCS and TES need to agree on a common URB entry layout. In particular,
720 * the data for all patch vertices is stored in a single URB entry (unlike
721 * GS which has one entry per input vertex). This means that per-vertex
722 * array indexing needs a stride.
724 * SSO requires locations to match, but doesn't require the number of
725 * outputs/inputs to match (in fact, the TCS often has extra outputs).
726 * So, we need to take the extra step of unifying these on the fly.
729 get_unified_tess_slots(const struct iris_context
*ice
,
730 uint64_t *per_vertex_slots
,
731 uint32_t *per_patch_slots
)
733 const struct shader_info
*tcs
=
734 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
735 const struct shader_info
*tes
=
736 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
738 *per_vertex_slots
= tes
->inputs_read
;
739 *per_patch_slots
= tes
->patch_inputs_read
;
742 *per_vertex_slots
|= tcs
->outputs_written
;
743 *per_patch_slots
|= tcs
->patch_outputs_written
;
748 * Compile a tessellation control shader, and upload the assembly.
750 static struct iris_compiled_shader
*
751 iris_compile_tcs(struct iris_context
*ice
,
752 struct iris_uncompiled_shader
*ish
,
753 const struct brw_tcs_prog_key
*key
)
755 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
756 const struct brw_compiler
*compiler
= screen
->compiler
;
757 const struct nir_shader_compiler_options
*options
=
758 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
759 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
760 void *mem_ctx
= ralloc_context(NULL
);
761 struct brw_tcs_prog_data
*tcs_prog_data
=
762 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
763 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
764 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
765 enum brw_param_builtin
*system_values
= NULL
;
766 unsigned num_system_values
= 0;
767 unsigned num_cbufs
= 0;
772 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
774 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
775 &num_system_values
, &num_cbufs
);
776 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
777 num_system_values
, num_cbufs
);
779 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
781 /* Reserve space for passing the default tess levels as constants. */
782 num_system_values
= 8;
784 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
785 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
786 prog_data
->nr_params
= num_system_values
;
788 if (key
->tes_primitive_mode
== GL_QUADS
) {
789 for (int i
= 0; i
< 4; i
++)
790 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
792 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
793 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
794 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
795 for (int i
= 0; i
< 3; i
++)
796 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
798 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
800 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
801 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
802 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
805 prog_data
->ubo_ranges
[0].length
= 1;
808 char *error_str
= NULL
;
809 const unsigned *program
=
810 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
812 if (program
== NULL
) {
813 dbg_printf("Failed to compile control shader: %s\n", error_str
);
814 ralloc_free(mem_ctx
);
819 if (ish
->compiled_once
) {
820 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
822 ish
->compiled_once
= true;
826 struct iris_compiled_shader
*shader
=
827 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
828 prog_data
, NULL
, system_values
, num_system_values
,
832 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
834 ralloc_free(mem_ctx
);
839 * Update the current tessellation control shader variant.
841 * Fill out the key, look in the cache, compile and bind if needed.
844 iris_update_compiled_tcs(struct iris_context
*ice
)
846 struct iris_uncompiled_shader
*tcs
=
847 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
848 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
849 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
851 const struct shader_info
*tes_info
=
852 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
853 struct brw_tcs_prog_key key
= {
854 KEY_INIT_NO_ID(devinfo
->gen
),
855 .program_string_id
= tcs
? tcs
->program_id
: 0,
856 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
857 .input_vertices
= ice
->state
.vertices_per_patch
,
859 get_unified_tess_slots(ice
, &key
.outputs_written
,
860 &key
.patch_outputs_written
);
861 ice
->vtbl
.populate_tcs_key(ice
, &key
);
863 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
864 struct iris_compiled_shader
*shader
=
865 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
868 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
871 shader
= iris_compile_tcs(ice
, tcs
, &key
);
874 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
875 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
876 IRIS_DIRTY_BINDINGS_TCS
|
877 IRIS_DIRTY_CONSTANTS_TCS
;
882 * Compile a tessellation evaluation shader, and upload the assembly.
884 static struct iris_compiled_shader
*
885 iris_compile_tes(struct iris_context
*ice
,
886 struct iris_uncompiled_shader
*ish
,
887 const struct brw_tes_prog_key
*key
)
889 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
890 const struct brw_compiler
*compiler
= screen
->compiler
;
891 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
892 void *mem_ctx
= ralloc_context(NULL
);
893 struct brw_tes_prog_data
*tes_prog_data
=
894 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
895 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
896 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
897 enum brw_param_builtin
*system_values
;
898 unsigned num_system_values
;
901 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
903 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
904 &num_system_values
, &num_cbufs
);
906 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
907 num_system_values
, num_cbufs
);
909 struct brw_vue_map input_vue_map
;
910 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
911 key
->patch_inputs_read
);
913 char *error_str
= NULL
;
914 const unsigned *program
=
915 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
916 tes_prog_data
, nir
, NULL
, -1, &error_str
);
917 if (program
== NULL
) {
918 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
919 ralloc_free(mem_ctx
);
923 if (ish
->compiled_once
) {
924 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
926 ish
->compiled_once
= true;
930 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
931 &vue_prog_data
->vue_map
);
934 struct iris_compiled_shader
*shader
=
935 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
936 prog_data
, so_decls
, system_values
, num_system_values
,
939 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
941 ralloc_free(mem_ctx
);
946 * Update the current tessellation evaluation shader variant.
948 * Fill out the key, look in the cache, compile and bind if needed.
951 iris_update_compiled_tes(struct iris_context
*ice
)
953 struct iris_uncompiled_shader
*ish
=
954 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
955 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
956 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
958 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
959 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
960 ice
->vtbl
.populate_tes_key(ice
, &key
);
962 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
963 struct iris_compiled_shader
*shader
=
964 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
967 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
970 shader
= iris_compile_tes(ice
, ish
, &key
);
973 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
974 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
975 IRIS_DIRTY_BINDINGS_TES
|
976 IRIS_DIRTY_CONSTANTS_TES
;
979 /* TODO: Could compare and avoid flagging this. */
980 const struct shader_info
*tes_info
= &ish
->nir
->info
;
981 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
982 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
983 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].cbuf0_needs_upload
= true;
988 * Compile a geometry shader, and upload the assembly.
990 static struct iris_compiled_shader
*
991 iris_compile_gs(struct iris_context
*ice
,
992 struct iris_uncompiled_shader
*ish
,
993 const struct brw_gs_prog_key
*key
)
995 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
996 const struct brw_compiler
*compiler
= screen
->compiler
;
997 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
998 void *mem_ctx
= ralloc_context(NULL
);
999 struct brw_gs_prog_data
*gs_prog_data
=
1000 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1001 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1002 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1003 enum brw_param_builtin
*system_values
;
1004 unsigned num_system_values
;
1007 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1009 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1010 &num_system_values
, &num_cbufs
);
1012 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
1013 num_system_values
, num_cbufs
);
1015 brw_compute_vue_map(devinfo
,
1016 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1017 nir
->info
.separate_shader
);
1019 char *error_str
= NULL
;
1020 const unsigned *program
=
1021 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1022 NULL
, -1, &error_str
);
1023 if (program
== NULL
) {
1024 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1025 ralloc_free(mem_ctx
);
1029 if (ish
->compiled_once
) {
1030 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1032 ish
->compiled_once
= true;
1035 uint32_t *so_decls
=
1036 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1037 &vue_prog_data
->vue_map
);
1039 struct iris_compiled_shader
*shader
=
1040 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1041 prog_data
, so_decls
, system_values
, num_system_values
,
1044 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1046 ralloc_free(mem_ctx
);
1051 * Update the current geometry shader variant.
1053 * Fill out the key, look in the cache, compile and bind if needed.
1056 iris_update_compiled_gs(struct iris_context
*ice
)
1058 struct iris_uncompiled_shader
*ish
=
1059 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1060 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1061 struct iris_compiled_shader
*shader
= NULL
;
1064 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1065 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1066 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1067 ice
->vtbl
.populate_gs_key(ice
, &key
);
1070 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1073 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1076 shader
= iris_compile_gs(ice
, ish
, &key
);
1079 if (old
!= shader
) {
1080 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1081 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1082 IRIS_DIRTY_BINDINGS_GS
|
1083 IRIS_DIRTY_CONSTANTS_GS
;
1088 * Compile a fragment (pixel) shader, and upload the assembly.
1090 static struct iris_compiled_shader
*
1091 iris_compile_fs(struct iris_context
*ice
,
1092 struct iris_uncompiled_shader
*ish
,
1093 const struct brw_wm_prog_key
*key
,
1094 struct brw_vue_map
*vue_map
)
1096 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1097 const struct brw_compiler
*compiler
= screen
->compiler
;
1098 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1099 void *mem_ctx
= ralloc_context(NULL
);
1100 struct brw_wm_prog_data
*fs_prog_data
=
1101 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1102 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1103 enum brw_param_builtin
*system_values
;
1104 unsigned num_system_values
;
1107 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1109 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1111 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1112 &num_system_values
, &num_cbufs
);
1114 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
1115 MAX2(key
->nr_color_regions
, 1),
1116 num_system_values
, num_cbufs
);
1117 char *error_str
= NULL
;
1118 const unsigned *program
=
1119 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1120 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1121 if (program
== NULL
) {
1122 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1123 ralloc_free(mem_ctx
);
1127 if (ish
->compiled_once
) {
1128 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1130 ish
->compiled_once
= true;
1133 struct iris_compiled_shader
*shader
=
1134 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1135 prog_data
, NULL
, system_values
, num_system_values
,
1138 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1140 ralloc_free(mem_ctx
);
1145 * Update the current fragment shader variant.
1147 * Fill out the key, look in the cache, compile and bind if needed.
1150 iris_update_compiled_fs(struct iris_context
*ice
)
1152 struct iris_uncompiled_shader
*ish
=
1153 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1154 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1155 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1156 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1157 ice
->vtbl
.populate_fs_key(ice
, &key
);
1159 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1160 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1162 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1163 struct iris_compiled_shader
*shader
=
1164 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1167 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1170 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1172 if (old
!= shader
) {
1173 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1174 // toggles. might be able to avoid flagging SBE too.
1175 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1176 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1177 IRIS_DIRTY_BINDINGS_FS
|
1178 IRIS_DIRTY_CONSTANTS_FS
|
1186 * Get the compiled shader for the last enabled geometry stage.
1188 * This stage is the one which will feed stream output and the rasterizer.
1190 static gl_shader_stage
1191 last_vue_stage(struct iris_context
*ice
)
1193 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
1194 return MESA_SHADER_GEOMETRY
;
1196 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
1197 return MESA_SHADER_TESS_EVAL
;
1199 return MESA_SHADER_VERTEX
;
1203 * Update the last enabled stage's VUE map.
1205 * When the shader feeding the rasterizer's output interface changes, we
1206 * need to re-emit various packets.
1209 update_last_vue_map(struct iris_context
*ice
,
1210 struct brw_stage_prog_data
*prog_data
)
1212 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1213 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1214 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1215 const uint64_t changed_slots
=
1216 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1218 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1219 // XXX: could use ctx->Const.MaxViewports for old API efficiency
1220 ice
->state
.num_viewports
=
1221 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1222 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1223 IRIS_DIRTY_SF_CL_VIEWPORT
|
1224 IRIS_DIRTY_CC_VIEWPORT
|
1225 IRIS_DIRTY_SCISSOR_RECT
|
1226 IRIS_DIRTY_UNCOMPILED_FS
|
1227 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1228 // XXX: CC_VIEWPORT?
1231 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1232 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1235 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1239 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1241 static struct brw_vue_prog_data
*
1242 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1244 if (!ice
->shaders
.prog
[stage
])
1247 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1250 // XXX: iris_compiled_shaders are space-leaking :(
1251 // XXX: do remember to unbind them if deleting them.
1254 * Update the current shader variants for the given state.
1256 * This should be called on every draw call to ensure that the correct
1257 * shaders are bound. It will also flag any dirty state triggered by
1258 * swapping out those shaders.
1261 iris_update_compiled_shaders(struct iris_context
*ice
)
1263 const uint64_t dirty
= ice
->state
.dirty
;
1265 struct brw_vue_prog_data
*old_prog_datas
[4];
1266 if (!(dirty
& IRIS_DIRTY_URB
)) {
1267 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1268 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1271 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1272 struct iris_uncompiled_shader
*tes
=
1273 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1275 iris_update_compiled_tcs(ice
);
1276 iris_update_compiled_tes(ice
);
1278 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1279 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1281 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1282 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1283 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1287 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1288 iris_update_compiled_vs(ice
);
1289 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1290 iris_update_compiled_gs(ice
);
1292 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1293 const struct iris_compiled_shader
*gs
=
1294 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1295 const struct iris_compiled_shader
*tes
=
1296 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1298 bool points_or_lines
= false;
1301 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1303 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1304 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1306 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1308 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1309 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1312 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1313 /* Outbound to XY Clip enables */
1314 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1315 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1319 gl_shader_stage last_stage
= last_vue_stage(ice
);
1320 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1321 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1322 update_last_vue_map(ice
, shader
->prog_data
);
1323 if (ice
->state
.streamout
!= shader
->streamout
) {
1324 ice
->state
.streamout
= shader
->streamout
;
1325 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1328 if (ice
->state
.streamout_active
) {
1329 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1330 struct iris_stream_output_target
*so
=
1331 (void *) ice
->state
.so_target
[i
];
1333 so
->stride
= ish
->stream_output
.stride
[i
];
1337 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1338 iris_update_compiled_fs(ice
);
1340 /* Changing shader interfaces may require a URB configuration. */
1341 if (!(dirty
& IRIS_DIRTY_URB
)) {
1342 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1343 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1344 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1345 if (!!old
!= !!new ||
1346 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1347 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1354 static struct iris_compiled_shader
*
1355 iris_compile_cs(struct iris_context
*ice
,
1356 struct iris_uncompiled_shader
*ish
,
1357 const struct brw_cs_prog_key
*key
)
1359 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1360 const struct brw_compiler
*compiler
= screen
->compiler
;
1361 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1362 void *mem_ctx
= ralloc_context(NULL
);
1363 struct brw_cs_prog_data
*cs_prog_data
=
1364 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1365 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1366 enum brw_param_builtin
*system_values
;
1367 unsigned num_system_values
;
1370 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1372 cs_prog_data
->binding_table
.work_groups_start
= 0;
1374 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1376 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1377 &num_system_values
, &num_cbufs
);
1379 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1,
1380 num_system_values
, num_cbufs
);
1382 char *error_str
= NULL
;
1383 const unsigned *program
=
1384 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1385 nir
, -1, &error_str
);
1386 if (program
== NULL
) {
1387 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1388 ralloc_free(mem_ctx
);
1392 if (ish
->compiled_once
) {
1393 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1395 ish
->compiled_once
= true;
1398 struct iris_compiled_shader
*shader
=
1399 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1400 prog_data
, NULL
, system_values
, num_system_values
,
1403 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1405 ralloc_free(mem_ctx
);
1410 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1412 struct iris_uncompiled_shader
*ish
=
1413 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1415 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1416 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1417 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1418 ice
->vtbl
.populate_cs_key(ice
, &key
);
1420 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1421 struct iris_compiled_shader
*shader
=
1422 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1425 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1428 shader
= iris_compile_cs(ice
, ish
, &key
);
1430 if (old
!= shader
) {
1431 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1432 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1433 IRIS_DIRTY_BINDINGS_CS
|
1434 IRIS_DIRTY_CONSTANTS_CS
;
1439 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1442 assert(cs_prog_data
->push
.total
.size
> 0);
1443 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1444 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1445 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1446 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1451 * Allocate scratch BOs as needed for the given per-thread size and stage.
1454 iris_get_scratch_space(struct iris_context
*ice
,
1455 unsigned per_thread_scratch
,
1456 gl_shader_stage stage
)
1458 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1459 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1460 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1462 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1463 assert(encoded_size
< (1 << 16));
1465 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1467 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1469 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1470 * must allocate scratch space enough so that each slice has 4
1473 * According to the other driver team, this applies to compute shaders
1474 * as well. This is not currently documented at all.
1476 * This hack is no longer necessary on Gen11+.
1478 unsigned subslice_total
= screen
->subslice_total
;
1479 if (devinfo
->gen
< 11)
1480 subslice_total
= 4 * devinfo
->num_slices
;
1481 assert(subslice_total
>= screen
->subslice_total
);
1484 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1485 uint32_t max_threads
[] = {
1486 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1487 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1488 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1489 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1490 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1491 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1494 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1496 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1502 /* ------------------------------------------------------------------- */
1505 * The pipe->create_[stage]_state() driver hooks.
1507 * Performs basic NIR preprocessing, records any state dependencies, and
1508 * returns an iris_uncompiled_shader as the Gallium CSO.
1510 * Actual shader compilation to assembly happens later, at first use.
1513 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1515 const struct pipe_stream_output_info
*so_info
)
1517 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1518 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1520 struct iris_uncompiled_shader
*ish
=
1521 calloc(1, sizeof(struct iris_uncompiled_shader
));
1525 nir
= brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1527 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1528 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1530 ish
->program_id
= get_new_program_id(screen
);
1533 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1534 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1537 /* Save this now before potentially dropping nir->info.name */
1538 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1539 ish
->use_alt_mode
= true;
1541 if (screen
->disk_cache
) {
1542 /* Serialize the NIR to a binary blob that we can hash for the disk
1543 * cache. First, drop unnecessary information (like variable names)
1544 * so the serialized NIR is smaller, and also to let us detect more
1545 * isomorphic shaders when hashing, increasing cache hits. We clone
1546 * the NIR before stripping away this info because it can be useful
1547 * when inspecting and debugging shaders.
1549 nir_shader
*clone
= nir_shader_clone(NULL
, nir
);
1554 nir_serialize(&blob
, clone
);
1555 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
1564 static struct iris_uncompiled_shader
*
1565 iris_create_shader_state(struct pipe_context
*ctx
,
1566 const struct pipe_shader_state
*state
)
1568 struct nir_shader
*nir
;
1570 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1571 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1573 nir
= state
->ir
.nir
;
1575 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1579 iris_create_vs_state(struct pipe_context
*ctx
,
1580 const struct pipe_shader_state
*state
)
1582 struct iris_context
*ice
= (void *) ctx
;
1583 struct iris_screen
*screen
= (void *) ctx
->screen
;
1584 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1586 /* User clip planes */
1587 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1588 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
1590 if (screen
->precompile
) {
1591 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1592 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1594 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1595 iris_compile_vs(ice
, ish
, &key
);
1602 iris_create_tcs_state(struct pipe_context
*ctx
,
1603 const struct pipe_shader_state
*state
)
1605 struct iris_context
*ice
= (void *) ctx
;
1606 struct iris_screen
*screen
= (void *) ctx
->screen
;
1607 const struct brw_compiler
*compiler
= screen
->compiler
;
1608 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1609 struct shader_info
*info
= &ish
->nir
->info
;
1613 if (screen
->precompile
) {
1614 const unsigned _GL_TRIANGLES
= 0x0004;
1615 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1616 struct brw_tcs_prog_key key
= {
1617 KEY_INIT(devinfo
->gen
),
1618 // XXX: make sure the linker fills this out from the TES...
1619 .tes_primitive_mode
=
1620 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
1622 .outputs_written
= info
->outputs_written
,
1623 .patch_outputs_written
= info
->patch_outputs_written
,
1626 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
1627 * We don't have that information, so we randomly guess that the input
1628 * and output patches are the same size. This is a bad guess, but we
1629 * can't do much better.
1631 if (compiler
->use_tcs_8_patch
)
1632 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
1634 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1635 iris_compile_tcs(ice
, ish
, &key
);
1642 iris_create_tes_state(struct pipe_context
*ctx
,
1643 const struct pipe_shader_state
*state
)
1645 struct iris_context
*ice
= (void *) ctx
;
1646 struct iris_screen
*screen
= (void *) ctx
->screen
;
1647 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1648 struct shader_info
*info
= &ish
->nir
->info
;
1652 if (screen
->precompile
) {
1653 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1654 struct brw_tes_prog_key key
= {
1655 KEY_INIT(devinfo
->gen
),
1656 // XXX: not ideal, need TCS output/TES input unification
1657 .inputs_read
= info
->inputs_read
,
1658 .patch_inputs_read
= info
->patch_inputs_read
,
1661 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1662 iris_compile_tes(ice
, ish
, &key
);
1669 iris_create_gs_state(struct pipe_context
*ctx
,
1670 const struct pipe_shader_state
*state
)
1672 struct iris_context
*ice
= (void *) ctx
;
1673 struct iris_screen
*screen
= (void *) ctx
->screen
;
1674 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1678 if (screen
->precompile
) {
1679 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1680 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1682 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1683 iris_compile_gs(ice
, ish
, &key
);
1690 iris_create_fs_state(struct pipe_context
*ctx
,
1691 const struct pipe_shader_state
*state
)
1693 struct iris_context
*ice
= (void *) ctx
;
1694 struct iris_screen
*screen
= (void *) ctx
->screen
;
1695 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1696 struct shader_info
*info
= &ish
->nir
->info
;
1698 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
1699 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
1700 (1ull << IRIS_NOS_RASTERIZER
) |
1701 (1ull << IRIS_NOS_BLEND
);
1703 /* The program key needs the VUE map if there are > 16 inputs */
1704 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
1705 BRW_FS_VARYING_INPUT_MASK
) > 16) {
1706 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
1709 if (screen
->precompile
) {
1710 const uint64_t color_outputs
= info
->outputs_written
&
1711 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
1712 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
1713 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
1715 bool can_rearrange_varyings
=
1716 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
1718 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1719 struct brw_wm_prog_key key
= {
1720 KEY_INIT(devinfo
->gen
),
1721 .nr_color_regions
= util_bitcount(color_outputs
),
1722 .coherent_fb_fetch
= true,
1723 .input_slots_valid
=
1724 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
1727 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1728 iris_compile_fs(ice
, ish
, &key
, NULL
);
1735 iris_create_compute_state(struct pipe_context
*ctx
,
1736 const struct pipe_compute_state
*state
)
1738 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
1740 struct iris_context
*ice
= (void *) ctx
;
1741 struct iris_screen
*screen
= (void *) ctx
->screen
;
1742 struct iris_uncompiled_shader
*ish
=
1743 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
1745 // XXX: disallow more than 64KB of shared variables
1747 if (screen
->precompile
) {
1748 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1749 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1751 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1752 iris_compile_cs(ice
, ish
, &key
);
1759 * The pipe->delete_[stage]_state() driver hooks.
1761 * Frees the iris_uncompiled_shader.
1764 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
1766 struct iris_uncompiled_shader
*ish
= state
;
1767 struct iris_context
*ice
= (void *) ctx
;
1769 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
1770 ice
->shaders
.uncompiled
[stage
] = NULL
;
1771 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
1774 ralloc_free(ish
->nir
);
1779 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1781 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
1785 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1787 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
1791 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1793 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
1797 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1799 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
1803 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
1805 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
1809 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
1811 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
1815 * The pipe->bind_[stage]_state() driver hook.
1817 * Binds an uncompiled shader as the current one for a particular stage.
1818 * Updates dirty tracking to account for the shader's NOS.
1821 bind_state(struct iris_context
*ice
,
1822 struct iris_uncompiled_shader
*ish
,
1823 gl_shader_stage stage
)
1825 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
1826 const uint64_t nos
= ish
? ish
->nos
: 0;
1828 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
1829 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
1831 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
1832 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
1833 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1836 ice
->shaders
.uncompiled
[stage
] = ish
;
1837 ice
->state
.dirty
|= dirty_bit
;
1839 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
1840 * (or that they no longer need to do so).
1842 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
1844 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
1846 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
1851 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1853 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
1857 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1859 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
1863 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1865 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1867 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1868 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
1869 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1871 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
1875 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1877 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1879 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1880 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
1881 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1883 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
1887 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
1889 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1890 struct iris_uncompiled_shader
*old_ish
=
1891 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1892 struct iris_uncompiled_shader
*new_ish
= state
;
1894 const unsigned color_bits
=
1895 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
1896 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
1898 /* Fragment shader outputs influence HasWriteableRT */
1899 if (!old_ish
|| !new_ish
||
1900 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
1901 (new_ish
->nir
->info
.outputs_written
& color_bits
))
1902 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1904 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
1908 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
1910 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
1914 iris_init_program_functions(struct pipe_context
*ctx
)
1916 ctx
->create_vs_state
= iris_create_vs_state
;
1917 ctx
->create_tcs_state
= iris_create_tcs_state
;
1918 ctx
->create_tes_state
= iris_create_tes_state
;
1919 ctx
->create_gs_state
= iris_create_gs_state
;
1920 ctx
->create_fs_state
= iris_create_fs_state
;
1921 ctx
->create_compute_state
= iris_create_compute_state
;
1923 ctx
->delete_vs_state
= iris_delete_vs_state
;
1924 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
1925 ctx
->delete_tes_state
= iris_delete_tes_state
;
1926 ctx
->delete_gs_state
= iris_delete_gs_state
;
1927 ctx
->delete_fs_state
= iris_delete_fs_state
;
1928 ctx
->delete_compute_state
= iris_delete_cs_state
;
1930 ctx
->bind_vs_state
= iris_bind_vs_state
;
1931 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1932 ctx
->bind_tes_state
= iris_bind_tes_state
;
1933 ctx
->bind_gs_state
= iris_bind_gs_state
;
1934 ctx
->bind_fs_state
= iris_bind_fs_state
;
1935 ctx
->bind_compute_state
= iris_bind_cs_state
;