src/gallium/drivers/iris/iris_program.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_atomic.h"
  30 #include "compiler/nir/nir.h"
  31 #include "compiler/nir/nir_builder.h"
  32 #include "intel/compiler/brw_compiler.h"
  33 #include "intel/compiler/brw_nir.h"
  34 #include "iris_context.h"
  35
  36 static unsigned
  37 get_new_program_id(struct iris_screen *screen)
  38 {
  39    return p_atomic_inc_return(&screen->program_id);
  40 }
  41
  42 struct iris_uncompiled_shader {
  43    struct pipe_shader_state base;
  44    unsigned program_id;
  45 };
  46
  47 // XXX: need unify_interfaces() at link time...
  48
  49 static void *
  50 iris_create_shader_state(struct pipe_context *ctx,
  51                          const struct pipe_shader_state *state)
  52 {
  53    //struct iris_context *ice = (struct iris_context *)ctx;
  54    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
  55
  56    assert(state->type == PIPE_SHADER_IR_NIR);
  57
  58    nir_shader *nir = state->ir.nir;
  59
  60    struct iris_uncompiled_shader *ish =
  61       calloc(1, sizeof(struct iris_uncompiled_shader));
  62    if (!ish)
  63       return NULL;
  64
  65    nir = brw_preprocess_nir(screen->compiler, nir);
  66
  67 #if 0
  68    /* Reassign uniform locations using type_size_scalar_bytes instead of
  69     * the slot based calculation that st_nir uses.
  70     */
  71    nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
  72                             type_size_scalar_bytes);
  73    nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes, 0);
  74 #endif
  75    nir_foreach_variable(var, &nir->uniforms) {
  76       var->data.driver_location *= 4;
  77    }
  78    nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes, 0);
  79
  80    ish->program_id = get_new_program_id(screen);
  81    ish->base.type = PIPE_SHADER_IR_NIR;
  82    ish->base.ir.nir = nir;
  83
  84    return ish;
  85 }
  86
  87 static void
  88 iris_delete_shader_state(struct pipe_context *ctx, void *hwcso)
  89 {
  90    struct iris_uncompiled_shader *ish = hwcso;
  91
  92    ralloc_free(ish->base.ir.nir);
  93    free(ish);
  94 }
  95
  96 static void
  97 iris_bind_vs_state(struct pipe_context *ctx, void *hwcso)
  98 {
  99    struct iris_context *ice = (struct iris_context *)ctx;
 100
 101    ice->shaders.uncompiled[MESA_SHADER_VERTEX] = hwcso;
 102    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_VS;
 103 }
 104
 105 static void
 106 iris_bind_tcs_state(struct pipe_context *ctx, void *hwcso)
 107 {
 108    struct iris_context *ice = (struct iris_context *)ctx;
 109
 110    ice->shaders.uncompiled[MESA_SHADER_TESS_CTRL] = hwcso;
 111    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TCS;
 112 }
 113
 114 static void
 115 iris_bind_tes_state(struct pipe_context *ctx, void *hwcso)
 116 {
 117    struct iris_context *ice = (struct iris_context *)ctx;
 118
 119    if (!!hwcso != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
 120       ice->state.dirty |= IRIS_DIRTY_URB;
 121
 122    ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL] = hwcso;
 123    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TES;
 124 }
 125
 126 static void
 127 iris_bind_gs_state(struct pipe_context *ctx, void *hwcso)
 128 {
 129    struct iris_context *ice = (struct iris_context *)ctx;
 130
 131    if (!!hwcso != !!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
 132       ice->state.dirty |= IRIS_DIRTY_URB;
 133
 134    ice->shaders.uncompiled[MESA_SHADER_GEOMETRY] = hwcso;
 135    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_GS;
 136 }
 137
 138 static void
 139 iris_bind_fs_state(struct pipe_context *ctx, void *hwcso)
 140 {
 141    struct iris_context *ice = (struct iris_context *)ctx;
 142
 143    ice->shaders.uncompiled[MESA_SHADER_FRAGMENT] = hwcso;
 144    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_FS;
 145 }
 146
 147 /**
 148  * Sets up the starting offsets for the groups of binding table entries
 149  * common to all pipeline stages.
 150  *
 151  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 152  * unused but also make sure that addition of small offsets to them will
 153  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 154  */
 155 static uint32_t
 156 assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
 157                                     const struct shader_info *info,
 158                                     struct brw_stage_prog_data *prog_data,
 159                                     uint32_t next_binding_table_offset)
 160 {
 161    if (info->num_textures) {
 162       prog_data->binding_table.texture_start = next_binding_table_offset;
 163       prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 164       next_binding_table_offset += info->num_textures;
 165    } else {
 166       prog_data->binding_table.texture_start = 0xd0d0d0d0;
 167       prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
 168    }
 169
 170    if (info->num_ubos) {
 171       //assert(info->num_ubos <= BRW_MAX_UBO);
 172       prog_data->binding_table.ubo_start = next_binding_table_offset;
 173       next_binding_table_offset += info->num_ubos;
 174    } else {
 175       prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 176    }
 177
 178    if (info->num_ssbos || info->num_abos) {
 179       //assert(info->num_abos <= BRW_MAX_ABO);
 180       //assert(info->num_ssbos <= BRW_MAX_SSBO);
 181       prog_data->binding_table.ssbo_start = next_binding_table_offset;
 182       next_binding_table_offset += info->num_abos + info->num_ssbos;
 183    } else {
 184       prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
 185    }
 186
 187    prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 188
 189    if (info->num_images) {
 190       prog_data->binding_table.image_start = next_binding_table_offset;
 191       next_binding_table_offset += info->num_images;
 192    } else {
 193       prog_data->binding_table.image_start = 0xd0d0d0d0;
 194    }
 195
 196    /* This may or may not be used depending on how the compile goes. */
 197    prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 198    next_binding_table_offset++;
 199
 200    /* Plane 0 is just the regular texture section */
 201    prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
 202
 203    prog_data->binding_table.plane_start[1] = next_binding_table_offset;
 204    next_binding_table_offset += info->num_textures;
 205
 206    prog_data->binding_table.plane_start[2] = next_binding_table_offset;
 207    next_binding_table_offset += info->num_textures;
 208
 209    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 210
 211    //assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 212    return next_binding_table_offset;
 213 }
 214
 215 static void
 216 iris_setup_uniforms(void *mem_ctx,
 217                     nir_shader *nir,
 218                     struct brw_stage_prog_data *prog_data)
 219 {
 220    prog_data->nr_params = nir->num_uniforms * 4;
 221    prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
 222
 223    nir->num_uniforms *= 16;
 224
 225    nir_foreach_variable(var, &nir->uniforms) {
 226       /* UBO's, atomics and samplers don't take up space */
 227       //if (var->interface_type != NULL || var->type->contains_atomic())
 228          //continue;
 229
 230       const unsigned components = glsl_get_components(var->type);
 231
 232       for (unsigned i = 0; i < 4; i++) {
 233          prog_data->param[var->data.driver_location] =
 234             i < components ? BRW_PARAM_PARAMETER(var->data.driver_location, i)
 235                            : BRW_PARAM_BUILTIN_ZERO;
 236       }
 237    }
 238 }
 239
 240 static bool
 241 iris_compile_vs(struct iris_context *ice,
 242                 struct iris_uncompiled_shader *ish,
 243                 const struct brw_vs_prog_key *key)
 244 {
 245    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 246    const struct brw_compiler *compiler = screen->compiler;
 247    const struct gen_device_info *devinfo = &screen->devinfo;
 248    void *mem_ctx = ralloc_context(NULL);
 249    struct brw_vs_prog_data *vs_prog_data =
 250       rzalloc(mem_ctx, struct brw_vs_prog_data);
 251    struct brw_vue_prog_data *vue_prog_data = &vs_prog_data->base;
 252    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 253
 254    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 255
 256    nir_shader *nir = ish->base.ir.nir;
 257
 258    // XXX: alt mode
 259    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data, 0);
 260
 261    iris_setup_uniforms(mem_ctx, nir, prog_data);
 262
 263    brw_compute_vue_map(devinfo,
 264                        &vue_prog_data->vue_map, nir->info.outputs_written,
 265                        nir->info.separate_shader);
 266
 267    char *error_str = NULL;
 268    const unsigned *program =
 269       brw_compile_vs(compiler, &ice->dbg, mem_ctx, key, vs_prog_data,
 270                      nir, -1, &error_str);
 271    if (program == NULL) {
 272       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 273       ralloc_free(mem_ctx);
 274       return false;
 275    }
 276
 277    iris_upload_and_bind_shader(ice, IRIS_CACHE_VS, key, program, prog_data);
 278
 279    ralloc_free(mem_ctx);
 280    return true;
 281 }
 282
 283 static void
 284 iris_update_compiled_vs(struct iris_context *ice)
 285 {
 286    struct brw_vs_prog_key key;
 287    ice->vtbl.populate_vs_key(ice, &key);
 288
 289    if (iris_bind_cached_shader(ice, IRIS_CACHE_VS, &key))
 290       return;
 291
 292    UNUSED bool success =
 293       iris_compile_vs(ice, ice->shaders.uncompiled[MESA_SHADER_VERTEX], &key);
 294 }
 295
 296 static void
 297 iris_update_compiled_tcs(struct iris_context *ice)
 298 {
 299    // XXX: TCS
 300 }
 301
 302 static bool
 303 iris_compile_tes(struct iris_context *ice,
 304                  struct iris_uncompiled_shader *ish,
 305                  const struct brw_tes_prog_key *key)
 306 {
 307    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 308    const struct brw_compiler *compiler = screen->compiler;
 309    const struct gen_device_info *devinfo = &screen->devinfo;
 310    void *mem_ctx = ralloc_context(NULL);
 311    struct brw_tes_prog_data *tes_prog_data =
 312       rzalloc(mem_ctx, struct brw_tes_prog_data);
 313    struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
 314    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 315
 316    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 317
 318    nir_shader *nir = ish->base.ir.nir;
 319
 320    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data, 0);
 321
 322    struct brw_vue_map input_vue_map;
 323    brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
 324                             key->patch_inputs_read);
 325
 326    char *error_str = NULL;
 327    const unsigned *program =
 328       brw_compile_tes(compiler, &ice->dbg, mem_ctx, key, &input_vue_map,
 329                       tes_prog_data, nir, NULL, -1, &error_str);
 330    if (program == NULL) {
 331       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 332       ralloc_free(mem_ctx);
 333       return false;
 334    }
 335
 336    iris_upload_and_bind_shader(ice, IRIS_CACHE_TES, key, program, prog_data);
 337
 338    ralloc_free(mem_ctx);
 339    return true;
 340 }
 341
 342
 343 static void
 344 iris_update_compiled_tes(struct iris_context *ice)
 345 {
 346    struct iris_uncompiled_shader *ish =
 347       ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
 348
 349    if (!ish)
 350       return;
 351
 352    struct brw_tes_prog_key key;
 353    ice->vtbl.populate_tes_key(ice, &key);
 354
 355    if (iris_bind_cached_shader(ice, IRIS_CACHE_TES, &key))
 356       return;
 357
 358    UNUSED bool success = iris_compile_tes(ice, ish, &key);
 359 }
 360
 361 static void
 362 iris_update_compiled_gs(struct iris_context *ice)
 363 {
 364    // XXX: GS
 365 }
 366
 367 static bool
 368 iris_compile_fs(struct iris_context *ice,
 369                 struct iris_uncompiled_shader *ish,
 370                 const struct brw_wm_prog_key *key,
 371                 struct brw_vue_map *vue_map)
 372 {
 373    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 374    const struct brw_compiler *compiler = screen->compiler;
 375    const struct gen_device_info *devinfo = &screen->devinfo;
 376    void *mem_ctx = ralloc_context(NULL);
 377    struct brw_wm_prog_data *fs_prog_data =
 378       rzalloc(mem_ctx, struct brw_wm_prog_data);
 379    struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
 380
 381    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 382
 383    nir_shader *nir = ish->base.ir.nir;
 384
 385    // XXX: alt mode
 386    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data,
 387                                        MAX2(key->nr_color_regions, 1));
 388
 389    iris_setup_uniforms(mem_ctx, nir, prog_data);
 390
 391    char *error_str = NULL;
 392    const unsigned *program =
 393       brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, fs_prog_data,
 394                      nir, NULL, -1, -1, -1, true, false, vue_map, &error_str);
 395    if (program == NULL) {
 396       dbg_printf("Failed to compile fragment shader: %s\n", error_str);
 397       ralloc_free(mem_ctx);
 398       return false;
 399    }
 400
 401    //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
 402
 403    iris_upload_and_bind_shader(ice, IRIS_CACHE_FS, key, program, prog_data);
 404
 405    ralloc_free(mem_ctx);
 406    return true;
 407 }
 408
 409 static void
 410 iris_update_compiled_fs(struct iris_context *ice)
 411 {
 412    struct brw_wm_prog_key key;
 413    ice->vtbl.populate_fs_key(ice, &key);
 414
 415    if (iris_bind_cached_shader(ice, IRIS_CACHE_FS, &key))
 416       return;
 417
 418    UNUSED bool success =
 419       iris_compile_fs(ice, ice->shaders.uncompiled[MESA_SHADER_FRAGMENT], &key,
 420                       ice->shaders.last_vue_map);
 421 }
 422
 423 static void
 424 update_last_vue_map(struct iris_context *ice)
 425 {
 426    struct brw_stage_prog_data *prog_data;
 427
 428    if (ice->shaders.prog[MESA_SHADER_GEOMETRY])
 429       prog_data = ice->shaders.prog[MESA_SHADER_GEOMETRY]->prog_data;
 430    else if (ice->shaders.prog[MESA_SHADER_TESS_EVAL])
 431       prog_data = ice->shaders.prog[MESA_SHADER_TESS_EVAL]->prog_data;
 432    else
 433       prog_data = ice->shaders.prog[MESA_SHADER_VERTEX]->prog_data;
 434
 435    struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
 436    ice->shaders.last_vue_map = &vue_prog_data->vue_map;
 437 }
 438
 439 static struct brw_vue_prog_data *
 440 get_vue_prog_data(struct iris_context *ice, gl_shader_stage stage)
 441 {
 442    if (!ice->shaders.prog[stage])
 443       return NULL;
 444
 445    return (void *) ice->shaders.prog[stage]->prog_data;
 446 }
 447
 448 void
 449 iris_update_compiled_shaders(struct iris_context *ice)
 450 {
 451    struct brw_vue_prog_data *old_prog_datas[4];
 452    if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
 453       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++)
 454          old_prog_datas[i] = get_vue_prog_data(ice, i);
 455    }
 456
 457    iris_update_compiled_vs(ice);
 458    iris_update_compiled_tcs(ice);
 459    iris_update_compiled_tes(ice);
 460    iris_update_compiled_gs(ice);
 461    update_last_vue_map(ice);
 462    iris_update_compiled_fs(ice);
 463    // ...
 464
 465    if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
 466       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 467          struct brw_vue_prog_data *old = old_prog_datas[i];
 468          struct brw_vue_prog_data *new = get_vue_prog_data(ice, i);
 469          if (!!old != !!new ||
 470              (new && new->urb_entry_size != old->urb_entry_size)) {
 471             ice->state.dirty |= IRIS_DIRTY_URB;
 472             break;
 473          }
 474       }
 475    }
 476 }
 477
 478 void
 479 iris_init_program_functions(struct pipe_context *ctx)
 480 {
 481    ctx->create_vs_state  = iris_create_shader_state;
 482    ctx->create_tcs_state = iris_create_shader_state;
 483    ctx->create_tes_state = iris_create_shader_state;
 484    ctx->create_gs_state  = iris_create_shader_state;
 485    ctx->create_fs_state  = iris_create_shader_state;
 486
 487    ctx->delete_vs_state  = iris_delete_shader_state;
 488    ctx->delete_tcs_state = iris_delete_shader_state;
 489    ctx->delete_tes_state = iris_delete_shader_state;
 490    ctx->delete_gs_state  = iris_delete_shader_state;
 491    ctx->delete_fs_state  = iris_delete_shader_state;
 492
 493    ctx->bind_vs_state  = iris_bind_vs_state;
 494    ctx->bind_tcs_state = iris_bind_tcs_state;
 495    ctx->bind_tes_state = iris_bind_tes_state;
 496    ctx->bind_gs_state  = iris_bind_gs_state;
 497    ctx->bind_fs_state  = iris_bind_fs_state;
 498 }