src/gallium/drivers/iris/iris_program.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file iris_program.c
  26  *
  27  * This file contains the driver interface for compiling shaders.
  28  *
  29  * See iris_program_cache.c for the in-memory program cache where the
  30  * compiled shaders are stored.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include "pipe/p_defines.h"
  36 #include "pipe/p_state.h"
  37 #include "pipe/p_context.h"
  38 #include "pipe/p_screen.h"
  39 #include "util/u_atomic.h"
  40 #include "compiler/nir/nir.h"
  41 #include "compiler/nir/nir_builder.h"
  42 #include "intel/compiler/brw_compiler.h"
  43 #include "intel/compiler/brw_nir.h"
  44 #include "iris_context.h"
  45
  46 static unsigned
  47 get_new_program_id(struct iris_screen *screen)
  48 {
  49    return p_atomic_inc_return(&screen->program_id);
  50 }
  51
  52 /**
  53  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
  54  * It primarily contains the NIR for the shader.
  55  *
  56  * Each API-facing shader can be compiled into multiple shader variants,
  57  * based on non-orthogonal state dependencies, recorded in the shader key.
  58  *
  59  * See iris_compiled_shader, which represents a compiled shader variant.
  60  */
  61 struct iris_uncompiled_shader {
  62    nir_shader *nir;
  63
  64    struct pipe_stream_output_info stream_output;
  65
  66    unsigned program_id;
  67
  68    /** Bitfield of (1 << IRIS_NOS_*) flags. */
  69    unsigned nos;
  70 };
  71
  72 // XXX: need unify_interfaces() at link time...
  73
  74 /**
  75  * The pipe->create_[stage]_state() driver hooks.
  76  *
  77  * Performs basic NIR preprocessing, records any state dependencies, and
  78  * returns an iris_uncompiled_shader as the Gallium CSO.
  79  *
  80  * Actual shader compilation to assembly happens later, at first use.
  81  */
  82 static void *
  83 iris_create_shader_state(struct pipe_context *ctx,
  84                          const struct pipe_shader_state *state)
  85 {
  86    //struct iris_context *ice = (struct iris_context *)ctx;
  87    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
  88
  89    assert(state->type == PIPE_SHADER_IR_NIR);
  90
  91    nir_shader *nir = state->ir.nir;
  92
  93    struct iris_uncompiled_shader *ish =
  94       calloc(1, sizeof(struct iris_uncompiled_shader));
  95    if (!ish)
  96       return NULL;
  97
  98    nir = brw_preprocess_nir(screen->compiler, nir);
  99
 100    ish->program_id = get_new_program_id(screen);
 101    ish->nir = nir;
 102    memcpy(&ish->stream_output, &state->stream_output,
 103           sizeof(struct pipe_stream_output_info));
 104
 105    switch (nir->info.stage) {
 106    case MESA_SHADER_VERTEX:
 107       // XXX: NOS
 108       break;
 109    case MESA_SHADER_TESS_CTRL:
 110       // XXX: NOS
 111       break;
 112    case MESA_SHADER_TESS_EVAL:
 113       // XXX: NOS
 114       break;
 115    case MESA_SHADER_GEOMETRY:
 116       // XXX: NOS
 117       break;
 118    case MESA_SHADER_FRAGMENT:
 119       ish->nos |= IRIS_NOS_FRAMEBUFFER |
 120                   IRIS_NOS_DEPTH_STENCIL_ALPHA |
 121                   IRIS_NOS_RASTERIZER |
 122                   IRIS_NOS_BLEND;
 123
 124       /* The program key needs the VUE map if there are > 16 inputs */
 125       if (util_bitcount64(ish->nir->info.inputs_read &
 126                           BRW_FS_VARYING_INPUT_MASK) > 16) {
 127          ish->nos |= IRIS_NOS_LAST_VUE_MAP;
 128       }
 129       break;
 130    case MESA_SHADER_COMPUTE:
 131       // XXX: NOS
 132       break;
 133    default:
 134       break;
 135    }
 136
 137    // XXX: precompile!
 138
 139    return ish;
 140 }
 141
 142 /**
 143  * The pipe->delete_[stage]_state() driver hooks.
 144  *
 145  * Frees the iris_uncompiled_shader.
 146  */
 147 static void
 148 iris_delete_shader_state(struct pipe_context *ctx, void *state)
 149 {
 150    struct iris_uncompiled_shader *ish = state;
 151
 152    ralloc_free(ish->nir);
 153    free(ish);
 154 }
 155
 156 /**
 157  * The pipe->bind_[stage]_state() driver hook.
 158  *
 159  * Binds an uncompiled shader as the current one for a particular stage.
 160  * Updates dirty tracking to account for the shader's NOS.
 161  */
 162 static void
 163 bind_state(struct iris_context *ice,
 164            struct iris_uncompiled_shader *ish,
 165            gl_shader_stage stage)
 166 {
 167    uint64_t dirty_bit = IRIS_DIRTY_UNCOMPILED_VS << stage;
 168    const uint64_t nos = ish ? ish->nos : 0;
 169
 170    ice->shaders.uncompiled[stage] = ish;
 171    ice->state.dirty |= dirty_bit;
 172
 173    /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
 174     * (or that they no longer need to do so).
 175     */
 176    for (int i = 0; i < IRIS_NOS_COUNT; i++) {
 177       if (nos & (1 << i))
 178          ice->state.dirty_for_nos[i] |= dirty_bit;
 179       else
 180          ice->state.dirty_for_nos[i] &= ~dirty_bit;
 181    }
 182 }
 183
 184 static void
 185 iris_bind_vs_state(struct pipe_context *ctx, void *state)
 186 {
 187    bind_state((void *) ctx, state, MESA_SHADER_VERTEX);
 188 }
 189
 190 static void
 191 iris_bind_tcs_state(struct pipe_context *ctx, void *state)
 192 {
 193    bind_state((void *) ctx, state, MESA_SHADER_TESS_CTRL);
 194 }
 195
 196 static void
 197 iris_bind_tes_state(struct pipe_context *ctx, void *state)
 198 {
 199    struct iris_context *ice = (struct iris_context *)ctx;
 200
 201    /* Enabling/disabling optional stages requires a URB reconfiguration. */
 202    if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
 203       ice->state.dirty |= IRIS_DIRTY_URB;
 204
 205    bind_state((void *) ctx, state, MESA_SHADER_TESS_EVAL);
 206 }
 207
 208 static void
 209 iris_bind_gs_state(struct pipe_context *ctx, void *state)
 210 {
 211    struct iris_context *ice = (struct iris_context *)ctx;
 212
 213    /* Enabling/disabling optional stages requires a URB reconfiguration. */
 214    if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
 215       ice->state.dirty |= IRIS_DIRTY_URB;
 216
 217    bind_state((void *) ctx, state, MESA_SHADER_GEOMETRY);
 218 }
 219
 220 static void
 221 iris_bind_fs_state(struct pipe_context *ctx, void *state)
 222 {
 223    bind_state((void *) ctx, state, MESA_SHADER_FRAGMENT);
 224 }
 225
 226 /**
 227  * Sets up the starting offsets for the groups of binding table entries
 228  * common to all pipeline stages.
 229  *
 230  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 231  * unused but also make sure that addition of small offsets to them will
 232  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 233  */
 234 static uint32_t
 235 assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
 236                                     const struct nir_shader *nir,
 237                                     struct brw_stage_prog_data *prog_data,
 238                                     uint32_t next_binding_table_offset)
 239 {
 240    const struct shader_info *info = &nir->info;
 241
 242    if (info->num_textures) {
 243       prog_data->binding_table.texture_start = next_binding_table_offset;
 244       prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 245       next_binding_table_offset += info->num_textures;
 246    } else {
 247       prog_data->binding_table.texture_start = 0xd0d0d0d0;
 248       prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
 249    }
 250
 251    int num_ubos = info->num_ubos + (nir->num_uniforms > 0 ? 1 : 0);
 252
 253    if (num_ubos) {
 254       //assert(info->num_ubos <= BRW_MAX_UBO);
 255       prog_data->binding_table.ubo_start = next_binding_table_offset;
 256       next_binding_table_offset += num_ubos;
 257    } else {
 258       prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 259    }
 260
 261    if (info->num_ssbos || info->num_abos) {
 262       //assert(info->num_abos <= BRW_MAX_ABO);
 263       //assert(info->num_ssbos <= BRW_MAX_SSBO);
 264       prog_data->binding_table.ssbo_start = next_binding_table_offset;
 265       next_binding_table_offset += info->num_abos + info->num_ssbos;
 266    } else {
 267       prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
 268    }
 269
 270    prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 271
 272    if (info->num_images) {
 273       prog_data->binding_table.image_start = next_binding_table_offset;
 274       next_binding_table_offset += info->num_images;
 275    } else {
 276       prog_data->binding_table.image_start = 0xd0d0d0d0;
 277    }
 278
 279    /* This may or may not be used depending on how the compile goes. */
 280    prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 281    next_binding_table_offset++;
 282
 283    /* Plane 0 is just the regular texture section */
 284    prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
 285
 286    prog_data->binding_table.plane_start[1] = next_binding_table_offset;
 287    next_binding_table_offset += info->num_textures;
 288
 289    prog_data->binding_table.plane_start[2] = next_binding_table_offset;
 290    next_binding_table_offset += info->num_textures;
 291
 292    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 293
 294    //assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 295    return next_binding_table_offset;
 296 }
 297
 298 /**
 299  * Associate NIR uniform variables with the prog_data->param[] mechanism
 300  * used by the backend.  Also, decide which UBOs we'd like to push in an
 301  * ideal situation (though the backend can reduce this).
 302  */
 303 static void
 304 iris_setup_uniforms(const struct brw_compiler *compiler,
 305                     void *mem_ctx,
 306                     nir_shader *nir,
 307                     struct brw_stage_prog_data *prog_data)
 308 {
 309    prog_data->nr_params = nir->num_uniforms;
 310    prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
 311
 312    nir_foreach_variable(var, &nir->uniforms) {
 313       const unsigned components = glsl_get_components(var->type);
 314
 315       for (unsigned i = 0; i < components; i++) {
 316          prog_data->param[var->data.driver_location] =
 317             var->data.driver_location;
 318       }
 319    }
 320
 321    // XXX: vs clip planes?
 322    brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
 323 }
 324
 325 /**
 326  * If we still have regular uniforms as push constants after the backend
 327  * compilation, set up a UBO range for them.  This will be used to fill
 328  * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
 329  */
 330 static void
 331 iris_setup_push_uniform_range(const struct brw_compiler *compiler,
 332                               struct brw_stage_prog_data *prog_data)
 333 {
 334    if (prog_data->nr_params) {
 335       for (int i = 3; i > 0; i--)
 336          prog_data->ubo_ranges[i] = prog_data->ubo_ranges[i - 1];
 337
 338       prog_data->ubo_ranges[0] = (struct brw_ubo_range) {
 339          .block = 0,
 340          .start = 0,
 341          .length = DIV_ROUND_UP(prog_data->nr_params, 8),
 342       };
 343    }
 344 }
 345
 346 /**
 347  * Compile a vertex shader, and upload the assembly.
 348  */
 349 static bool
 350 iris_compile_vs(struct iris_context *ice,
 351                 struct iris_uncompiled_shader *ish,
 352                 const struct brw_vs_prog_key *key)
 353 {
 354    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 355    const struct brw_compiler *compiler = screen->compiler;
 356    const struct gen_device_info *devinfo = &screen->devinfo;
 357    void *mem_ctx = ralloc_context(NULL);
 358    struct brw_vs_prog_data *vs_prog_data =
 359       rzalloc(mem_ctx, struct brw_vs_prog_data);
 360    struct brw_vue_prog_data *vue_prog_data = &vs_prog_data->base;
 361    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 362
 363    nir_shader *nir = ish->nir;
 364
 365    // XXX: alt mode
 366    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 367
 368    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 369
 370    brw_compute_vue_map(devinfo,
 371                        &vue_prog_data->vue_map, nir->info.outputs_written,
 372                        nir->info.separate_shader);
 373
 374    char *error_str = NULL;
 375    const unsigned *program =
 376       brw_compile_vs(compiler, &ice->dbg, mem_ctx, key, vs_prog_data,
 377                      nir, -1, &error_str);
 378    if (program == NULL) {
 379       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 380       ralloc_free(mem_ctx);
 381       return false;
 382    }
 383
 384    iris_setup_push_uniform_range(compiler, prog_data);
 385
 386    uint32_t *so_decls =
 387       ice->vtbl.create_so_decl_list(&ish->stream_output,
 388                                     &vue_prog_data->vue_map);
 389
 390    iris_upload_and_bind_shader(ice, IRIS_CACHE_VS, key, program, prog_data,
 391                                so_decls);
 392
 393    ralloc_free(mem_ctx);
 394    return true;
 395 }
 396
 397 /**
 398  * Update the current vertex shader variant.
 399  *
 400  * Fill out the key, look in the cache, compile and bind if needed.
 401  */
 402 static void
 403 iris_update_compiled_vs(struct iris_context *ice)
 404 {
 405    struct iris_uncompiled_shader *ish =
 406       ice->shaders.uncompiled[MESA_SHADER_VERTEX];
 407
 408    struct brw_vs_prog_key key = { .program_string_id = ish->program_id };
 409    ice->vtbl.populate_vs_key(ice, &key);
 410
 411    if (iris_bind_cached_shader(ice, IRIS_CACHE_VS, &key))
 412       return;
 413
 414    UNUSED bool success = iris_compile_vs(ice, ish, &key);
 415 }
 416
 417 /**
 418  * Get the shader_info for a given stage, or NULL if the stage is disabled.
 419  */
 420 const struct shader_info *
 421 iris_get_shader_info(const struct iris_context *ice, gl_shader_stage stage)
 422 {
 423    const struct iris_uncompiled_shader *ish = ice->shaders.uncompiled[stage];
 424
 425    if (!ish)
 426       return NULL;
 427
 428    const nir_shader *nir = ish->nir;
 429    return &nir->info;
 430 }
 431
 432 /**
 433  * Get the union of TCS output and TES input slots.
 434  *
 435  * TCS and TES need to agree on a common URB entry layout.  In particular,
 436  * the data for all patch vertices is stored in a single URB entry (unlike
 437  * GS which has one entry per input vertex).  This means that per-vertex
 438  * array indexing needs a stride.
 439  *
 440  * SSO requires locations to match, but doesn't require the number of
 441  * outputs/inputs to match (in fact, the TCS often has extra outputs).
 442  * So, we need to take the extra step of unifying these on the fly.
 443  */
 444 static void
 445 get_unified_tess_slots(const struct iris_context *ice,
 446                        uint64_t *per_vertex_slots,
 447                        uint32_t *per_patch_slots)
 448 {
 449    const struct shader_info *tcs =
 450       iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL);
 451    const struct shader_info *tes =
 452       iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
 453
 454    *per_vertex_slots = tes->inputs_read;
 455    *per_patch_slots = tes->patch_inputs_read;
 456
 457    if (tcs) {
 458       *per_vertex_slots |= tcs->inputs_read;
 459       *per_patch_slots |= tcs->patch_inputs_read;
 460    }
 461 }
 462
 463 /**
 464  * Compile a tessellation control shader, and upload the assembly.
 465  */
 466 static bool
 467 iris_compile_tcs(struct iris_context *ice,
 468                  struct iris_uncompiled_shader *ish,
 469                  const struct brw_tcs_prog_key *key)
 470 {
 471    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 472    const struct brw_compiler *compiler = screen->compiler;
 473    const struct gen_device_info *devinfo = &screen->devinfo;
 474    void *mem_ctx = ralloc_context(NULL);
 475    struct brw_tcs_prog_data *tcs_prog_data =
 476       rzalloc(mem_ctx, struct brw_tcs_prog_data);
 477    struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
 478    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 479
 480    nir_shader *nir = ish->nir;
 481
 482    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 483
 484    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 485
 486    char *error_str = NULL;
 487    const unsigned *program =
 488       brw_compile_tcs(compiler, &ice->dbg, mem_ctx, key, tcs_prog_data, nir,
 489                       -1, &error_str);
 490    if (program == NULL) {
 491       dbg_printf("Failed to compile evaluation shader: %s\n", error_str);
 492       ralloc_free(mem_ctx);
 493       return false;
 494    }
 495
 496    iris_setup_push_uniform_range(compiler, prog_data);
 497
 498    iris_upload_and_bind_shader(ice, IRIS_CACHE_TCS, key, program, prog_data,
 499                                NULL);
 500
 501    ralloc_free(mem_ctx);
 502    return true;
 503 }
 504
 505 /**
 506  * Update the current tessellation control shader variant.
 507  *
 508  * Fill out the key, look in the cache, compile and bind if needed.
 509  */
 510 static void
 511 iris_update_compiled_tcs(struct iris_context *ice)
 512 {
 513    struct iris_uncompiled_shader *tcs =
 514       ice->shaders.uncompiled[MESA_SHADER_TESS_CTRL];
 515    struct iris_uncompiled_shader *tes =
 516       ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
 517
 518    assert(!(tes && !tcs));
 519
 520    if (!tcs) {
 521       iris_unbind_shader(ice, IRIS_CACHE_TCS);
 522       return;
 523    }
 524
 525    const struct shader_info *tes_info =
 526       iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
 527    struct brw_tcs_prog_key key = {
 528       .program_string_id = tcs->program_id,
 529       .tes_primitive_mode = tes_info->tess.primitive_mode,
 530    };
 531    get_unified_tess_slots(ice, &key.outputs_written,
 532                           &key.patch_outputs_written);
 533    ice->vtbl.populate_tcs_key(ice, &key);
 534
 535    if (iris_bind_cached_shader(ice, IRIS_CACHE_TCS, &key))
 536       return;
 537
 538    UNUSED bool success = iris_compile_tcs(ice, tcs, &key);
 539 }
 540
 541 /**
 542  * Compile a tessellation evaluation shader, and upload the assembly.
 543  */
 544 static bool
 545 iris_compile_tes(struct iris_context *ice,
 546                  struct iris_uncompiled_shader *ish,
 547                  const struct brw_tes_prog_key *key)
 548 {
 549    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 550    const struct brw_compiler *compiler = screen->compiler;
 551    const struct gen_device_info *devinfo = &screen->devinfo;
 552    void *mem_ctx = ralloc_context(NULL);
 553    struct brw_tes_prog_data *tes_prog_data =
 554       rzalloc(mem_ctx, struct brw_tes_prog_data);
 555    struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
 556    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 557
 558    nir_shader *nir = ish->nir;
 559
 560    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 561
 562    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 563
 564    struct brw_vue_map input_vue_map;
 565    brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
 566                             key->patch_inputs_read);
 567
 568    char *error_str = NULL;
 569    const unsigned *program =
 570       brw_compile_tes(compiler, &ice->dbg, mem_ctx, key, &input_vue_map,
 571                       tes_prog_data, nir, NULL, -1, &error_str);
 572    if (program == NULL) {
 573       dbg_printf("Failed to compile evaluation shader: %s\n", error_str);
 574       ralloc_free(mem_ctx);
 575       return false;
 576    }
 577
 578    iris_setup_push_uniform_range(compiler, prog_data);
 579
 580    uint32_t *so_decls =
 581       ice->vtbl.create_so_decl_list(&ish->stream_output,
 582                                     &vue_prog_data->vue_map);
 583
 584    iris_upload_and_bind_shader(ice, IRIS_CACHE_TES, key, program, prog_data,
 585                                so_decls);
 586
 587    ralloc_free(mem_ctx);
 588    return true;
 589 }
 590
 591 /**
 592  * Update the current tessellation evaluation shader variant.
 593  *
 594  * Fill out the key, look in the cache, compile and bind if needed.
 595  */
 596 static void
 597 iris_update_compiled_tes(struct iris_context *ice)
 598 {
 599    struct iris_uncompiled_shader *ish =
 600       ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
 601
 602    if (!ish) {
 603       iris_unbind_shader(ice, IRIS_CACHE_TES);
 604       return;
 605    }
 606
 607    struct brw_tes_prog_key key = { .program_string_id = ish->program_id };
 608    get_unified_tess_slots(ice, &key.inputs_read, &key.patch_inputs_read);
 609    ice->vtbl.populate_tes_key(ice, &key);
 610
 611    if (iris_bind_cached_shader(ice, IRIS_CACHE_TES, &key))
 612       return;
 613
 614    UNUSED bool success = iris_compile_tes(ice, ish, &key);
 615 }
 616
 617 /**
 618  * Compile a geometry shader, and upload the assembly.
 619  */
 620 static bool
 621 iris_compile_gs(struct iris_context *ice,
 622                 struct iris_uncompiled_shader *ish,
 623                 const struct brw_gs_prog_key *key)
 624 {
 625    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 626    const struct brw_compiler *compiler = screen->compiler;
 627    const struct gen_device_info *devinfo = &screen->devinfo;
 628    void *mem_ctx = ralloc_context(NULL);
 629    struct brw_gs_prog_data *gs_prog_data =
 630       rzalloc(mem_ctx, struct brw_gs_prog_data);
 631    struct brw_vue_prog_data *vue_prog_data = &gs_prog_data->base;
 632    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 633
 634    nir_shader *nir = ish->nir;
 635
 636    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 637
 638    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 639
 640    brw_compute_vue_map(devinfo,
 641                        &vue_prog_data->vue_map, nir->info.outputs_written,
 642                        nir->info.separate_shader);
 643
 644    char *error_str = NULL;
 645    const unsigned *program =
 646       brw_compile_gs(compiler, &ice->dbg, mem_ctx, key, gs_prog_data, nir,
 647                      NULL, -1, &error_str);
 648    if (program == NULL) {
 649       dbg_printf("Failed to compile geometry shader: %s\n", error_str);
 650       ralloc_free(mem_ctx);
 651       return false;
 652    }
 653
 654    iris_setup_push_uniform_range(compiler, prog_data);
 655
 656    uint32_t *so_decls =
 657       ice->vtbl.create_so_decl_list(&ish->stream_output,
 658                                     &vue_prog_data->vue_map);
 659
 660    iris_upload_and_bind_shader(ice, IRIS_CACHE_GS, key, program, prog_data,
 661                                so_decls);
 662
 663    ralloc_free(mem_ctx);
 664    return true;
 665 }
 666
 667 /**
 668  * Update the current geometry shader variant.
 669  *
 670  * Fill out the key, look in the cache, compile and bind if needed.
 671  */
 672 static void
 673 iris_update_compiled_gs(struct iris_context *ice)
 674 {
 675    struct iris_uncompiled_shader *ish =
 676       ice->shaders.uncompiled[MESA_SHADER_GEOMETRY];
 677
 678    if (!ish) {
 679       iris_unbind_shader(ice, IRIS_CACHE_GS);
 680       return;
 681    }
 682
 683    struct brw_gs_prog_key key = { .program_string_id = ish->program_id };
 684    ice->vtbl.populate_gs_key(ice, &key);
 685
 686    if (iris_bind_cached_shader(ice, IRIS_CACHE_GS, &key))
 687       return;
 688
 689    UNUSED bool success = iris_compile_gs(ice, ish, &key);
 690 }
 691
 692 /**
 693  * Compile a fragment (pixel) shader, and upload the assembly.
 694  */
 695 static bool
 696 iris_compile_fs(struct iris_context *ice,
 697                 struct iris_uncompiled_shader *ish,
 698                 const struct brw_wm_prog_key *key,
 699                 struct brw_vue_map *vue_map)
 700 {
 701    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 702    const struct brw_compiler *compiler = screen->compiler;
 703    const struct gen_device_info *devinfo = &screen->devinfo;
 704    void *mem_ctx = ralloc_context(NULL);
 705    struct brw_wm_prog_data *fs_prog_data =
 706       rzalloc(mem_ctx, struct brw_wm_prog_data);
 707    struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
 708
 709    nir_shader *nir = ish->nir;
 710
 711    // XXX: alt mode
 712    assign_common_binding_table_offsets(devinfo, nir, prog_data,
 713                                        MAX2(key->nr_color_regions, 1));
 714
 715    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 716
 717    char *error_str = NULL;
 718    const unsigned *program =
 719       brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, fs_prog_data,
 720                      nir, NULL, -1, -1, -1, true, false, vue_map, &error_str);
 721    if (program == NULL) {
 722       dbg_printf("Failed to compile fragment shader: %s\n", error_str);
 723       ralloc_free(mem_ctx);
 724       return false;
 725    }
 726
 727    //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
 728
 729    iris_setup_push_uniform_range(compiler, prog_data);
 730
 731    iris_upload_and_bind_shader(ice, IRIS_CACHE_FS, key, program, prog_data,
 732                                NULL);
 733
 734    ralloc_free(mem_ctx);
 735    return true;
 736 }
 737
 738 /**
 739  * Update the current fragment shader variant.
 740  *
 741  * Fill out the key, look in the cache, compile and bind if needed.
 742  */
 743 static void
 744 iris_update_compiled_fs(struct iris_context *ice)
 745 {
 746    struct iris_uncompiled_shader *ish =
 747       ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
 748    struct brw_wm_prog_key key = { .program_string_id = ish->program_id };
 749    ice->vtbl.populate_fs_key(ice, &key);
 750
 751    if (ish->nos & IRIS_NOS_LAST_VUE_MAP)
 752       key.input_slots_valid = ice->shaders.last_vue_map->slots_valid;
 753
 754    if (iris_bind_cached_shader(ice, IRIS_CACHE_FS, &key))
 755       return;
 756
 757    UNUSED bool success =
 758       iris_compile_fs(ice, ish, &key, ice->shaders.last_vue_map);
 759 }
 760
 761 /**
 762  * Get the compiled shader for the last enabled geometry stage.
 763  *
 764  * This stage is the one which will feed stream output and the rasterizer.
 765  */
 766 static struct iris_compiled_shader *
 767 last_vue_shader(struct iris_context *ice)
 768 {
 769    if (ice->shaders.prog[MESA_SHADER_GEOMETRY])
 770       return ice->shaders.prog[MESA_SHADER_GEOMETRY];
 771
 772    if (ice->shaders.prog[MESA_SHADER_TESS_EVAL])
 773       return ice->shaders.prog[MESA_SHADER_TESS_EVAL];
 774
 775    return ice->shaders.prog[MESA_SHADER_VERTEX];
 776 }
 777
 778 /**
 779  * Update the last enabled stage's VUE map.
 780  *
 781  * When the shader feeding the rasterizer's output interface changes, we
 782  * need to re-emit various packets.
 783  */
 784 static void
 785 update_last_vue_map(struct iris_context *ice,
 786                     struct brw_stage_prog_data *prog_data)
 787 {
 788    struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
 789    struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
 790    struct brw_vue_map *old_map = ice->shaders.last_vue_map;
 791    const uint64_t changed_slots =
 792       (old_map ? old_map->slots_valid : 0ull) ^ vue_map->slots_valid;
 793
 794    if (changed_slots & VARYING_BIT_VIEWPORT) {
 795       // XXX: could use ctx->Const.MaxViewports for old API efficiency
 796       ice->state.num_viewports =
 797          (vue_map->slots_valid & VARYING_BIT_VIEWPORT) ? IRIS_MAX_VIEWPORTS : 1;
 798       ice->state.dirty |= IRIS_DIRTY_CLIP |
 799                           IRIS_DIRTY_SF_CL_VIEWPORT |
 800                           IRIS_DIRTY_SCISSOR_RECT |
 801                           IRIS_DIRTY_UNCOMPILED_FS |
 802                           ice->state.dirty_for_nos[IRIS_NOS_LAST_VUE_MAP];
 803       // XXX: CC_VIEWPORT?
 804    }
 805
 806    if (changed_slots || (old_map && old_map->separate != vue_map->separate)) {
 807       ice->state.dirty |= IRIS_DIRTY_SBE;
 808    }
 809
 810    ice->shaders.last_vue_map = &vue_prog_data->vue_map;
 811 }
 812
 813 /**
 814  * Get the prog_data for a given stage, or NULL if the stage is disabled.
 815  */
 816 static struct brw_vue_prog_data *
 817 get_vue_prog_data(struct iris_context *ice, gl_shader_stage stage)
 818 {
 819    if (!ice->shaders.prog[stage])
 820       return NULL;
 821
 822    return (void *) ice->shaders.prog[stage]->prog_data;
 823 }
 824
 825 /**
 826  * Update the current shader variants for the given state.
 827  *
 828  * This should be called on every draw call to ensure that the correct
 829  * shaders are bound.  It will also flag any dirty state triggered by
 830  * swapping out those shaders.
 831  */
 832 void
 833 iris_update_compiled_shaders(struct iris_context *ice)
 834 {
 835    const uint64_t dirty = ice->state.dirty;
 836
 837    struct brw_vue_prog_data *old_prog_datas[4];
 838    if (!(dirty & IRIS_DIRTY_URB)) {
 839       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++)
 840          old_prog_datas[i] = get_vue_prog_data(ice, i);
 841    }
 842
 843    if (dirty & IRIS_DIRTY_UNCOMPILED_VS)
 844       iris_update_compiled_vs(ice);
 845    if (dirty & IRIS_DIRTY_UNCOMPILED_TCS)
 846       iris_update_compiled_tcs(ice);
 847    if (dirty & IRIS_DIRTY_UNCOMPILED_TES)
 848       iris_update_compiled_tes(ice);
 849    if (dirty & IRIS_DIRTY_UNCOMPILED_GS)
 850       iris_update_compiled_gs(ice);
 851
 852    struct iris_compiled_shader *shader = last_vue_shader(ice);
 853    update_last_vue_map(ice, shader->prog_data);
 854    if (ice->state.streamout != shader->streamout) {
 855       ice->state.streamout = shader->streamout;
 856       ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST | IRIS_DIRTY_STREAMOUT;
 857    }
 858
 859    if (dirty & IRIS_DIRTY_UNCOMPILED_FS)
 860       iris_update_compiled_fs(ice);
 861    // ...
 862
 863    /* Changing shader interfaces may require a URB configuration. */
 864    if (!(dirty & IRIS_DIRTY_URB)) {
 865       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 866          struct brw_vue_prog_data *old = old_prog_datas[i];
 867          struct brw_vue_prog_data *new = get_vue_prog_data(ice, i);
 868          if (!!old != !!new ||
 869              (new && new->urb_entry_size != old->urb_entry_size)) {
 870             ice->state.dirty |= IRIS_DIRTY_URB;
 871             break;
 872          }
 873       }
 874    }
 875 }
 876
 877 void
 878 iris_init_program_functions(struct pipe_context *ctx)
 879 {
 880    ctx->create_vs_state  = iris_create_shader_state;
 881    ctx->create_tcs_state = iris_create_shader_state;
 882    ctx->create_tes_state = iris_create_shader_state;
 883    ctx->create_gs_state  = iris_create_shader_state;
 884    ctx->create_fs_state  = iris_create_shader_state;
 885
 886    ctx->delete_vs_state  = iris_delete_shader_state;
 887    ctx->delete_tcs_state = iris_delete_shader_state;
 888    ctx->delete_tes_state = iris_delete_shader_state;
 889    ctx->delete_gs_state  = iris_delete_shader_state;
 890    ctx->delete_fs_state  = iris_delete_shader_state;
 891
 892    ctx->bind_vs_state  = iris_bind_vs_state;
 893    ctx->bind_tcs_state = iris_bind_tcs_state;
 894    ctx->bind_tes_state = iris_bind_tes_state;
 895    ctx->bind_gs_state  = iris_bind_gs_state;
 896    ctx->bind_fs_state  = iris_bind_fs_state;
 897 }