2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/debug.h"
41 #include "compiler/nir/nir.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "compiler/nir/nir_serialize.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/compiler/brw_nir.h"
46 #include "iris_context.h"
47 #include "nir/tgsi_to_nir.h"
49 #define KEY_INIT_NO_ID(gen) \
50 .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
51 .tex.compressed_multisample_layout_mask = ~0, \
52 .tex.msaa_16 = (gen >= 9 ? ~0 : 0)
53 #define KEY_INIT(gen) .program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
56 get_new_program_id(struct iris_screen
*screen
)
58 return p_atomic_inc_return(&screen
->program_id
);
62 upload_state(struct u_upload_mgr
*uploader
,
63 struct iris_state_ref
*ref
,
68 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
73 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
74 struct pipe_shader_buffer
*buf
,
75 struct iris_state_ref
*surf_state
,
78 struct pipe_context
*ctx
= &ice
->ctx
;
79 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
81 // XXX: these are not retained forever, use a separate uploader?
83 upload_state(ice
->state
.surface_uploader
, surf_state
,
84 screen
->isl_dev
.ss
.size
, 64);
86 surf_state
->res
= NULL
;
90 struct iris_resource
*res
= (void *) buf
->buffer
;
91 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
92 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
94 isl_buffer_fill_state(&screen
->isl_dev
, map
,
95 .address
= res
->bo
->gtt_offset
+ res
->offset
+
97 .size_B
= buf
->buffer_size
- res
->offset
,
98 .format
= ssbo
? ISL_FORMAT_RAW
99 : ISL_FORMAT_R32G32B32A32_FLOAT
,
100 .swizzle
= ISL_SWIZZLE_IDENTITY
,
102 .mocs
= ice
->vtbl
.mocs(res
->bo
));
106 get_aoa_deref_offset(nir_builder
*b
,
107 nir_deref_instr
*deref
,
110 unsigned array_size
= elem_size
;
111 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
113 while (deref
->deref_type
!= nir_deref_type_var
) {
114 assert(deref
->deref_type
== nir_deref_type_array
);
116 /* This level's element size is the previous level's array size */
117 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
118 assert(deref
->arr
.index
.ssa
);
119 offset
= nir_iadd(b
, offset
,
120 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
122 deref
= nir_deref_instr_parent(deref
);
123 assert(glsl_type_is_array(deref
->type
));
124 array_size
*= glsl_get_length(deref
->type
);
127 /* Accessing an invalid surface index with the dataport can result in a
128 * hang. According to the spec "if the index used to select an individual
129 * element is negative or greater than or equal to the size of the array,
130 * the results of the operation are undefined but may not lead to
131 * termination" -- which is one of the possible outcomes of the hang.
132 * Clamp the index to prevent access outside of the array bounds.
134 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
138 iris_lower_storage_image_derefs(nir_shader
*nir
)
140 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
143 nir_builder_init(&b
, impl
);
145 nir_foreach_block(block
, impl
) {
146 nir_foreach_instr_safe(instr
, block
) {
147 if (instr
->type
!= nir_instr_type_intrinsic
)
150 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
151 switch (intrin
->intrinsic
) {
152 case nir_intrinsic_image_deref_load
:
153 case nir_intrinsic_image_deref_store
:
154 case nir_intrinsic_image_deref_atomic_add
:
155 case nir_intrinsic_image_deref_atomic_min
:
156 case nir_intrinsic_image_deref_atomic_max
:
157 case nir_intrinsic_image_deref_atomic_and
:
158 case nir_intrinsic_image_deref_atomic_or
:
159 case nir_intrinsic_image_deref_atomic_xor
:
160 case nir_intrinsic_image_deref_atomic_exchange
:
161 case nir_intrinsic_image_deref_atomic_comp_swap
:
162 case nir_intrinsic_image_deref_size
:
163 case nir_intrinsic_image_deref_samples
:
164 case nir_intrinsic_image_deref_load_raw_intel
:
165 case nir_intrinsic_image_deref_store_raw_intel
: {
166 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
167 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
169 b
.cursor
= nir_before_instr(&intrin
->instr
);
171 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
172 get_aoa_deref_offset(&b
, deref
, 1));
173 nir_rewrite_image_intrinsic(intrin
, index
, false);
184 // XXX: need unify_interfaces() at link time...
187 * Fix an uncompiled shader's stream output info.
189 * Core Gallium stores output->register_index as a "slot" number, where
190 * slots are assigned consecutively to all outputs in info->outputs_written.
191 * This naive packing of outputs doesn't work for us - we too have slots,
192 * but the layout is defined by the VUE map, which we won't have until we
193 * compile a specific shader variant. So, we remap these and simply store
194 * VARYING_SLOT_* in our copy's output->register_index fields.
196 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
197 * components of our VUE header. See brw_vue_map.c for the layout.
200 update_so_info(struct pipe_stream_output_info
*so_info
,
201 uint64_t outputs_written
)
203 uint8_t reverse_map
[64] = {};
205 while (outputs_written
) {
206 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
209 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
210 struct pipe_stream_output
*output
= &so_info
->output
[i
];
212 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
213 output
->register_index
= reverse_map
[output
->register_index
];
215 /* The VUE header contains three scalar fields packed together:
216 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
217 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
218 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
220 switch (output
->register_index
) {
221 case VARYING_SLOT_LAYER
:
222 assert(output
->num_components
== 1);
223 output
->register_index
= VARYING_SLOT_PSIZ
;
224 output
->start_component
= 1;
226 case VARYING_SLOT_VIEWPORT
:
227 assert(output
->num_components
== 1);
228 output
->register_index
= VARYING_SLOT_PSIZ
;
229 output
->start_component
= 2;
231 case VARYING_SLOT_PSIZ
:
232 assert(output
->num_components
== 1);
233 output
->start_component
= 3;
237 //info->outputs_written |= 1ull << output->register_index;
242 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
243 unsigned offset
, unsigned n
)
245 assert(offset
% sizeof(uint32_t) == 0);
247 for (unsigned i
= 0; i
< n
; ++i
)
248 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
250 for (unsigned i
= n
; i
< 4; ++i
)
251 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
255 * Associate NIR uniform variables with the prog_data->param[] mechanism
256 * used by the backend. Also, decide which UBOs we'd like to push in an
257 * ideal situation (though the backend can reduce this).
260 iris_setup_uniforms(const struct brw_compiler
*compiler
,
263 struct brw_stage_prog_data
*prog_data
,
264 enum brw_param_builtin
**out_system_values
,
265 unsigned *out_num_system_values
,
266 unsigned *out_num_cbufs
)
268 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
270 /* The intel compiler assumes that num_uniforms is in bytes. For
271 * scalar that means 4 bytes per uniform slot.
273 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
275 nir
->num_uniforms
*= 4;
277 const unsigned IRIS_MAX_SYSTEM_VALUES
=
278 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
279 enum brw_param_builtin
*system_values
=
280 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
281 unsigned num_system_values
= 0;
283 unsigned patch_vert_idx
= -1;
284 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
285 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
286 memset(ucp_idx
, -1, sizeof(ucp_idx
));
287 memset(img_idx
, -1, sizeof(img_idx
));
289 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
292 nir_builder_init(&b
, impl
);
294 b
.cursor
= nir_before_block(nir_start_block(impl
));
295 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
296 nir_ssa_def
*temp_const_ubo_name
= NULL
;
298 /* Turn system value intrinsics into uniforms */
299 nir_foreach_block(block
, impl
) {
300 nir_foreach_instr_safe(instr
, block
) {
301 if (instr
->type
!= nir_instr_type_intrinsic
)
304 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
307 switch (intrin
->intrinsic
) {
308 case nir_intrinsic_load_constant
: {
309 /* This one is special because it reads from the shader constant
310 * data and not cbuf0 which gallium uploads for us.
312 b
.cursor
= nir_before_instr(instr
);
313 nir_ssa_def
*offset
=
314 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
315 nir_intrinsic_base(intrin
));
317 if (temp_const_ubo_name
== NULL
)
318 temp_const_ubo_name
= nir_imm_int(&b
, 0);
320 nir_intrinsic_instr
*load_ubo
=
321 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
322 load_ubo
->num_components
= intrin
->num_components
;
323 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
324 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
325 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
326 intrin
->dest
.ssa
.num_components
,
327 intrin
->dest
.ssa
.bit_size
,
328 intrin
->dest
.ssa
.name
);
329 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
331 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
332 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
333 nir_instr_remove(&intrin
->instr
);
336 case nir_intrinsic_load_user_clip_plane
: {
337 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
339 if (ucp_idx
[ucp
] == -1) {
340 ucp_idx
[ucp
] = num_system_values
;
341 num_system_values
+= 4;
344 for (int i
= 0; i
< 4; i
++) {
345 system_values
[ucp_idx
[ucp
] + i
] =
346 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
349 b
.cursor
= nir_before_instr(instr
);
350 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
353 case nir_intrinsic_load_patch_vertices_in
:
354 if (patch_vert_idx
== -1)
355 patch_vert_idx
= num_system_values
++;
357 system_values
[patch_vert_idx
] =
358 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
360 b
.cursor
= nir_before_instr(instr
);
361 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
363 case nir_intrinsic_image_deref_load_param_intel
: {
364 assert(devinfo
->gen
< 9);
365 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
366 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
368 /* XXX: var->data.binding is not set properly. We need to run
369 * some form of gl_nir_lower_samplers_as_deref() to get it.
370 * This breaks tests which use more than one image.
372 if (img_idx
[var
->data
.binding
] == -1) {
373 /* GL only allows arrays of arrays of images. */
374 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
375 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
377 for (int i
= 0; i
< num_images
; i
++) {
378 const unsigned img
= var
->data
.binding
+ i
;
380 img_idx
[img
] = num_system_values
;
381 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
383 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
385 setup_vec4_image_sysval(
386 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
387 offsetof(struct brw_image_param
, offset
), 2);
388 setup_vec4_image_sysval(
389 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
390 offsetof(struct brw_image_param
, size
), 3);
391 setup_vec4_image_sysval(
392 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
393 offsetof(struct brw_image_param
, stride
), 4);
394 setup_vec4_image_sysval(
395 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
396 offsetof(struct brw_image_param
, tiling
), 3);
397 setup_vec4_image_sysval(
398 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
399 offsetof(struct brw_image_param
, swizzling
), 2);
403 b
.cursor
= nir_before_instr(instr
);
404 offset
= nir_iadd(&b
,
405 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
406 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
407 nir_intrinsic_base(intrin
) * 16));
414 unsigned comps
= nir_intrinsic_dest_components(intrin
);
416 nir_intrinsic_instr
*load
=
417 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
418 load
->num_components
= comps
;
419 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
420 load
->src
[1] = nir_src_for_ssa(offset
);
421 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
422 nir_builder_instr_insert(&b
, &load
->instr
);
423 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
424 nir_src_for_ssa(&load
->dest
.ssa
));
425 nir_instr_remove(instr
);
429 nir_validate_shader(nir
, "before remapping");
431 /* Place the new params at the front of constant buffer 0. */
432 if (num_system_values
> 0) {
433 nir
->num_uniforms
+= num_system_values
* sizeof(uint32_t);
435 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
438 nir_foreach_block(block
, impl
) {
439 nir_foreach_instr_safe(instr
, block
) {
440 if (instr
->type
!= nir_instr_type_intrinsic
)
443 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
445 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
448 b
.cursor
= nir_before_instr(instr
);
450 assert(load
->src
[0].is_ssa
);
452 if (load
->src
[0].ssa
== temp_ubo_name
) {
453 nir_instr_rewrite_src(instr
, &load
->src
[0],
454 nir_src_for_ssa(nir_imm_int(&b
, 0)));
455 } else if (nir_src_is_const(load
->src
[0]) &&
456 nir_src_as_uint(load
->src
[0]) == 0) {
457 nir_ssa_def
*offset
=
458 nir_iadd(&b
, load
->src
[1].ssa
,
459 nir_imm_int(&b
, 4 * num_system_values
));
460 nir_instr_rewrite_src(instr
, &load
->src
[1],
461 nir_src_for_ssa(offset
));
466 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
467 nir_opt_constant_folding(nir
);
469 ralloc_free(system_values
);
470 system_values
= NULL
;
473 nir_validate_shader(nir
, "after remap");
475 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
476 * about it for compute shaders, so go ahead and make some fake ones
477 * which the backend will dead code eliminate.
479 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
480 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
482 /* System values and uniforms are stored in constant buffer 0, the
483 * user-facing UBOs are indexed by one. So if any constant buffer is
484 * needed, the constant buffer 0 will be needed, so account for it.
486 unsigned num_cbufs
= nir
->info
.num_ubos
;
487 if (num_cbufs
|| num_system_values
|| nir
->num_uniforms
)
490 /* Constant loads (if any) need to go at the end of the constant buffers so
491 * we need to know num_cbufs before we can lower to them.
493 if (temp_const_ubo_name
!= NULL
) {
494 nir_load_const_instr
*const_ubo_index
=
495 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
496 assert(const_ubo_index
->def
.bit_size
== 32);
497 const_ubo_index
->value
[0].u32
= num_cbufs
;
500 *out_system_values
= system_values
;
501 *out_num_system_values
= num_system_values
;
502 *out_num_cbufs
= num_cbufs
;
505 static const char *surface_group_names
[] = {
506 [IRIS_SURFACE_GROUP_RENDER_TARGET
] = "render target",
507 [IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = "CS work groups",
508 [IRIS_SURFACE_GROUP_TEXTURE
] = "texture",
509 [IRIS_SURFACE_GROUP_UBO
] = "ubo",
510 [IRIS_SURFACE_GROUP_SSBO
] = "ssbo",
511 [IRIS_SURFACE_GROUP_IMAGE
] = "image",
515 iris_print_binding_table(FILE *fp
, const char *name
,
516 const struct iris_binding_table
*bt
)
518 STATIC_ASSERT(ARRAY_SIZE(surface_group_names
) == IRIS_SURFACE_GROUP_COUNT
);
521 uint32_t compacted
= 0;
523 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
524 uint32_t size
= bt
->sizes
[i
];
527 compacted
+= util_bitcount64(bt
->used_mask
[i
]);
531 fprintf(fp
, "Binding table for %s is empty\n\n", name
);
535 if (total
!= compacted
) {
536 fprintf(fp
, "Binding table for %s "
537 "(compacted to %u entries from %u entries)\n",
538 name
, compacted
, total
);
540 fprintf(fp
, "Binding table for %s (%u entries)\n", name
, total
);
544 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
545 uint64_t mask
= bt
->used_mask
[i
];
547 int index
= u_bit_scan64(&mask
);
548 fprintf(fp
, " [%u] %s #%d\n", entry
++, surface_group_names
[i
], index
);
555 /* Max elements in a surface group. */
556 SURFACE_GROUP_MAX_ELEMENTS
= 64,
560 * Map a <group, index> pair to a binding table index.
562 * For example: <UBO, 5> => binding table index 12
565 iris_group_index_to_bti(const struct iris_binding_table
*bt
,
566 enum iris_surface_group group
, uint32_t index
)
568 assert(index
< bt
->sizes
[group
]);
569 uint64_t mask
= bt
->used_mask
[group
];
570 uint64_t bit
= 1ull << index
;
572 return bt
->offsets
[group
] + util_bitcount64((bit
- 1) & mask
);
574 return IRIS_SURFACE_NOT_USED
;
579 * Map a binding table index back to a <group, index> pair.
581 * For example: binding table index 12 => <UBO, 5>
584 iris_bti_to_group_index(const struct iris_binding_table
*bt
,
585 enum iris_surface_group group
, uint32_t bti
)
587 uint64_t used_mask
= bt
->used_mask
[group
];
588 assert(bti
>= bt
->offsets
[group
]);
590 uint32_t c
= bti
- bt
->offsets
[group
];
592 int i
= u_bit_scan64(&used_mask
);
598 return IRIS_SURFACE_NOT_USED
;
602 rewrite_src_with_bti(nir_builder
*b
, struct iris_binding_table
*bt
,
603 nir_instr
*instr
, nir_src
*src
,
604 enum iris_surface_group group
)
606 assert(bt
->sizes
[group
] > 0);
608 b
->cursor
= nir_before_instr(instr
);
610 if (nir_src_is_const(*src
)) {
611 uint32_t index
= nir_src_as_uint(*src
);
612 bti
= nir_imm_intN_t(b
, iris_group_index_to_bti(bt
, group
, index
),
615 /* Indirect usage makes all the surfaces of the group to be available,
616 * so we can just add the base.
618 assert(bt
->used_mask
[group
] == BITFIELD64_MASK(bt
->sizes
[group
]));
619 bti
= nir_iadd_imm(b
, src
->ssa
, bt
->offsets
[group
]);
621 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(bti
));
625 mark_used_with_src(struct iris_binding_table
*bt
, nir_src
*src
,
626 enum iris_surface_group group
)
628 assert(bt
->sizes
[group
] > 0);
630 if (nir_src_is_const(*src
)) {
631 uint64_t index
= nir_src_as_uint(*src
);
632 assert(index
< bt
->sizes
[group
]);
633 bt
->used_mask
[group
] |= 1ull << index
;
635 /* There's an indirect usage, we need all the surfaces. */
636 bt
->used_mask
[group
] = BITFIELD64_MASK(bt
->sizes
[group
]);
641 skip_compacting_binding_tables(void)
643 static int skip
= -1;
645 skip
= env_var_as_boolean("INTEL_DISABLE_COMPACT_BINDING_TABLE", false);
650 * Set up the binding table indices and apply to the shader.
653 iris_setup_binding_table(struct nir_shader
*nir
,
654 struct iris_binding_table
*bt
,
655 unsigned num_render_targets
,
656 unsigned num_system_values
,
659 const struct shader_info
*info
= &nir
->info
;
661 memset(bt
, 0, sizeof(*bt
));
663 /* Set the sizes for each surface group. For some groups, we already know
664 * upfront how many will be used, so mark them.
666 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
667 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET
] = num_render_targets
;
668 /* All render targets used. */
669 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET
] =
670 BITFIELD64_MASK(num_render_targets
);
671 } else if (info
->stage
== MESA_SHADER_COMPUTE
) {
672 bt
->sizes
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
673 bt
->used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
676 bt
->sizes
[IRIS_SURFACE_GROUP_TEXTURE
] = util_last_bit(info
->textures_used
);
677 bt
->used_mask
[IRIS_SURFACE_GROUP_TEXTURE
] = info
->textures_used
;
679 bt
->sizes
[IRIS_SURFACE_GROUP_IMAGE
] = info
->num_images
;
681 /* Allocate an extra slot in the UBO section for NIR constants.
682 * Binding table compaction will remove it if unnecessary.
684 * We don't include them in iris_compiled_shader::num_cbufs because
685 * they are uploaded separately from shs->constbuf[], but from a shader
686 * point of view, they're another UBO (at the end of the section).
688 bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] = num_cbufs
+ 1;
690 /* The first IRIS_MAX_ABOs indices in the SSBO group are for atomics, real
691 * SSBOs start after that. Compaction will remove unused ABOs.
693 bt
->sizes
[IRIS_SURFACE_GROUP_SSBO
] = IRIS_MAX_ABOS
+ info
->num_ssbos
;
695 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
696 assert(bt
->sizes
[i
] <= SURFACE_GROUP_MAX_ELEMENTS
);
698 /* Mark surfaces used for the cases we don't have the information available
701 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
702 nir_foreach_block (block
, impl
) {
703 nir_foreach_instr (instr
, block
) {
704 if (instr
->type
!= nir_instr_type_intrinsic
)
707 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
708 switch (intrin
->intrinsic
) {
709 case nir_intrinsic_image_size
:
710 case nir_intrinsic_image_load
:
711 case nir_intrinsic_image_store
:
712 case nir_intrinsic_image_atomic_add
:
713 case nir_intrinsic_image_atomic_min
:
714 case nir_intrinsic_image_atomic_max
:
715 case nir_intrinsic_image_atomic_and
:
716 case nir_intrinsic_image_atomic_or
:
717 case nir_intrinsic_image_atomic_xor
:
718 case nir_intrinsic_image_atomic_exchange
:
719 case nir_intrinsic_image_atomic_comp_swap
:
720 case nir_intrinsic_image_load_raw_intel
:
721 case nir_intrinsic_image_store_raw_intel
:
722 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_IMAGE
);
725 case nir_intrinsic_load_ubo
:
726 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_UBO
);
729 case nir_intrinsic_store_ssbo
:
730 mark_used_with_src(bt
, &intrin
->src
[1], IRIS_SURFACE_GROUP_SSBO
);
733 case nir_intrinsic_get_buffer_size
:
734 case nir_intrinsic_ssbo_atomic_add
:
735 case nir_intrinsic_ssbo_atomic_imin
:
736 case nir_intrinsic_ssbo_atomic_umin
:
737 case nir_intrinsic_ssbo_atomic_imax
:
738 case nir_intrinsic_ssbo_atomic_umax
:
739 case nir_intrinsic_ssbo_atomic_and
:
740 case nir_intrinsic_ssbo_atomic_or
:
741 case nir_intrinsic_ssbo_atomic_xor
:
742 case nir_intrinsic_ssbo_atomic_exchange
:
743 case nir_intrinsic_ssbo_atomic_comp_swap
:
744 case nir_intrinsic_ssbo_atomic_fmin
:
745 case nir_intrinsic_ssbo_atomic_fmax
:
746 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
747 case nir_intrinsic_load_ssbo
:
748 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_SSBO
);
757 /* When disable we just mark everything as used. */
758 if (unlikely(skip_compacting_binding_tables())) {
759 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
760 bt
->used_mask
[i
] = BITFIELD64_MASK(bt
->sizes
[i
]);
763 /* Calculate the offsets and the binding table size based on the used
764 * surfaces. After this point, the functions to go between "group indices"
765 * and binding table indices can be used.
768 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
769 if (bt
->used_mask
[i
] != 0) {
770 bt
->offsets
[i
] = next
;
771 next
+= util_bitcount64(bt
->used_mask
[i
]);
774 bt
->size_bytes
= next
* 4;
776 if (unlikely(INTEL_DEBUG
& DEBUG_BT
)) {
777 iris_print_binding_table(stderr
, gl_shader_stage_name(info
->stage
), bt
);
780 /* Apply the binding table indices. The backend compiler is not expected
781 * to change those, as we haven't set any of the *_start entries in brw
785 nir_builder_init(&b
, impl
);
787 nir_foreach_block (block
, impl
) {
788 nir_foreach_instr (instr
, block
) {
789 if (instr
->type
== nir_instr_type_tex
) {
790 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
792 iris_group_index_to_bti(bt
, IRIS_SURFACE_GROUP_TEXTURE
,
797 if (instr
->type
!= nir_instr_type_intrinsic
)
800 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
801 switch (intrin
->intrinsic
) {
802 case nir_intrinsic_image_size
:
803 case nir_intrinsic_image_load
:
804 case nir_intrinsic_image_store
:
805 case nir_intrinsic_image_atomic_add
:
806 case nir_intrinsic_image_atomic_min
:
807 case nir_intrinsic_image_atomic_max
:
808 case nir_intrinsic_image_atomic_and
:
809 case nir_intrinsic_image_atomic_or
:
810 case nir_intrinsic_image_atomic_xor
:
811 case nir_intrinsic_image_atomic_exchange
:
812 case nir_intrinsic_image_atomic_comp_swap
:
813 case nir_intrinsic_image_load_raw_intel
:
814 case nir_intrinsic_image_store_raw_intel
:
815 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
816 IRIS_SURFACE_GROUP_IMAGE
);
819 case nir_intrinsic_load_ubo
:
820 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
821 IRIS_SURFACE_GROUP_UBO
);
824 case nir_intrinsic_store_ssbo
:
825 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[1],
826 IRIS_SURFACE_GROUP_SSBO
);
829 case nir_intrinsic_get_buffer_size
:
830 case nir_intrinsic_ssbo_atomic_add
:
831 case nir_intrinsic_ssbo_atomic_imin
:
832 case nir_intrinsic_ssbo_atomic_umin
:
833 case nir_intrinsic_ssbo_atomic_imax
:
834 case nir_intrinsic_ssbo_atomic_umax
:
835 case nir_intrinsic_ssbo_atomic_and
:
836 case nir_intrinsic_ssbo_atomic_or
:
837 case nir_intrinsic_ssbo_atomic_xor
:
838 case nir_intrinsic_ssbo_atomic_exchange
:
839 case nir_intrinsic_ssbo_atomic_comp_swap
:
840 case nir_intrinsic_ssbo_atomic_fmin
:
841 case nir_intrinsic_ssbo_atomic_fmax
:
842 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
843 case nir_intrinsic_load_ssbo
:
844 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
845 IRIS_SURFACE_GROUP_SSBO
);
856 iris_debug_recompile(struct iris_context
*ice
,
857 struct shader_info
*info
,
858 unsigned program_string_id
,
861 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
862 const struct brw_compiler
*c
= screen
->compiler
;
867 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
868 _mesa_shader_stage_to_string(info
->stage
),
869 info
->name
? info
->name
: "(no identifier)",
870 info
->label
? info
->label
: "");
872 const void *old_key
=
873 iris_find_previous_compile(ice
, info
->stage
, program_string_id
);
875 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
880 * Compile a vertex shader, and upload the assembly.
882 static struct iris_compiled_shader
*
883 iris_compile_vs(struct iris_context
*ice
,
884 struct iris_uncompiled_shader
*ish
,
885 const struct brw_vs_prog_key
*key
)
887 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
888 const struct brw_compiler
*compiler
= screen
->compiler
;
889 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
890 void *mem_ctx
= ralloc_context(NULL
);
891 struct brw_vs_prog_data
*vs_prog_data
=
892 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
893 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
894 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
895 enum brw_param_builtin
*system_values
;
896 unsigned num_system_values
;
899 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
901 if (key
->nr_userclip_plane_consts
) {
902 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
903 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
904 nir_lower_io_to_temporaries(nir
, impl
, true, false);
905 nir_lower_global_vars_to_local(nir
);
906 nir_lower_vars_to_ssa(nir
);
907 nir_shader_gather_info(nir
, impl
);
910 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
912 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
913 &num_system_values
, &num_cbufs
);
915 struct iris_binding_table bt
;
916 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
917 num_system_values
, num_cbufs
);
919 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
921 brw_compute_vue_map(devinfo
,
922 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
923 nir
->info
.separate_shader
);
925 /* Don't tell the backend about our clip plane constants, we've already
926 * lowered them in NIR and we don't want it doing it again.
928 struct brw_vs_prog_key key_no_ucp
= *key
;
929 key_no_ucp
.nr_userclip_plane_consts
= 0;
931 char *error_str
= NULL
;
932 const unsigned *program
=
933 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
934 nir
, -1, &error_str
);
935 if (program
== NULL
) {
936 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
937 ralloc_free(mem_ctx
);
941 if (ish
->compiled_once
) {
942 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
944 ish
->compiled_once
= true;
948 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
949 &vue_prog_data
->vue_map
);
951 struct iris_compiled_shader
*shader
=
952 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
953 prog_data
, so_decls
, system_values
, num_system_values
,
956 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
958 ralloc_free(mem_ctx
);
963 * Update the current vertex shader variant.
965 * Fill out the key, look in the cache, compile and bind if needed.
968 iris_update_compiled_vs(struct iris_context
*ice
)
970 struct iris_uncompiled_shader
*ish
=
971 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
972 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
973 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
975 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
976 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
978 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
979 struct iris_compiled_shader
*shader
=
980 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
983 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
986 shader
= iris_compile_vs(ice
, ish
, &key
);
989 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
990 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
991 IRIS_DIRTY_BINDINGS_VS
|
992 IRIS_DIRTY_CONSTANTS_VS
|
994 const struct brw_vs_prog_data
*vs_prog_data
=
995 (void *) shader
->prog_data
;
996 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
997 vs_prog_data
->uses_baseinstance
;
998 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
999 vs_prog_data
->uses_is_indexed_draw
;
1000 const bool needs_sgvs_element
= uses_draw_params
||
1001 vs_prog_data
->uses_instanceid
||
1002 vs_prog_data
->uses_vertexid
;
1003 bool needs_edge_flag
= false;
1004 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
1005 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
1006 needs_edge_flag
= true;
1009 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
1010 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
1011 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
1012 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
1013 IRIS_DIRTY_VERTEX_ELEMENTS
;
1015 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
1016 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
1017 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
1018 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
1023 * Get the shader_info for a given stage, or NULL if the stage is disabled.
1025 const struct shader_info
*
1026 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
1028 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
1033 const nir_shader
*nir
= ish
->nir
;
1038 * Get the union of TCS output and TES input slots.
1040 * TCS and TES need to agree on a common URB entry layout. In particular,
1041 * the data for all patch vertices is stored in a single URB entry (unlike
1042 * GS which has one entry per input vertex). This means that per-vertex
1043 * array indexing needs a stride.
1045 * SSO requires locations to match, but doesn't require the number of
1046 * outputs/inputs to match (in fact, the TCS often has extra outputs).
1047 * So, we need to take the extra step of unifying these on the fly.
1050 get_unified_tess_slots(const struct iris_context
*ice
,
1051 uint64_t *per_vertex_slots
,
1052 uint32_t *per_patch_slots
)
1054 const struct shader_info
*tcs
=
1055 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
1056 const struct shader_info
*tes
=
1057 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1059 *per_vertex_slots
= tes
->inputs_read
;
1060 *per_patch_slots
= tes
->patch_inputs_read
;
1063 *per_vertex_slots
|= tcs
->outputs_written
;
1064 *per_patch_slots
|= tcs
->patch_outputs_written
;
1069 * Compile a tessellation control shader, and upload the assembly.
1071 static struct iris_compiled_shader
*
1072 iris_compile_tcs(struct iris_context
*ice
,
1073 struct iris_uncompiled_shader
*ish
,
1074 const struct brw_tcs_prog_key
*key
)
1076 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1077 const struct brw_compiler
*compiler
= screen
->compiler
;
1078 const struct nir_shader_compiler_options
*options
=
1079 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
1080 void *mem_ctx
= ralloc_context(NULL
);
1081 struct brw_tcs_prog_data
*tcs_prog_data
=
1082 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
1083 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
1084 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1085 enum brw_param_builtin
*system_values
= NULL
;
1086 unsigned num_system_values
= 0;
1087 unsigned num_cbufs
= 0;
1091 struct iris_binding_table bt
;
1094 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1096 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1097 &num_system_values
, &num_cbufs
);
1098 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1099 num_system_values
, num_cbufs
);
1100 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1102 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
1104 /* Reserve space for passing the default tess levels as constants. */
1105 num_system_values
= 8;
1107 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
1108 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
1109 prog_data
->nr_params
= num_system_values
;
1111 if (key
->tes_primitive_mode
== GL_QUADS
) {
1112 for (int i
= 0; i
< 4; i
++)
1113 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1115 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1116 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
1117 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
1118 for (int i
= 0; i
< 3; i
++)
1119 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1121 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1123 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
1124 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
1125 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
1128 /* Manually setup the TCS binding table. */
1129 memset(&bt
, 0, sizeof(bt
));
1130 bt
.sizes
[IRIS_SURFACE_GROUP_UBO
] = 1;
1131 bt
.used_mask
[IRIS_SURFACE_GROUP_UBO
] = 1;
1134 prog_data
->ubo_ranges
[0].length
= 1;
1137 char *error_str
= NULL
;
1138 const unsigned *program
=
1139 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
1141 if (program
== NULL
) {
1142 dbg_printf("Failed to compile control shader: %s\n", error_str
);
1143 ralloc_free(mem_ctx
);
1148 if (ish
->compiled_once
) {
1149 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1151 ish
->compiled_once
= true;
1155 struct iris_compiled_shader
*shader
=
1156 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
1157 prog_data
, NULL
, system_values
, num_system_values
,
1161 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1163 ralloc_free(mem_ctx
);
1168 * Update the current tessellation control shader variant.
1170 * Fill out the key, look in the cache, compile and bind if needed.
1173 iris_update_compiled_tcs(struct iris_context
*ice
)
1175 struct iris_uncompiled_shader
*tcs
=
1176 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
1177 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1178 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1180 const struct shader_info
*tes_info
=
1181 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1182 struct brw_tcs_prog_key key
= {
1183 KEY_INIT_NO_ID(devinfo
->gen
),
1184 .program_string_id
= tcs
? tcs
->program_id
: 0,
1185 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
1186 .input_vertices
= ice
->state
.vertices_per_patch
,
1188 get_unified_tess_slots(ice
, &key
.outputs_written
,
1189 &key
.patch_outputs_written
);
1190 ice
->vtbl
.populate_tcs_key(ice
, &key
);
1192 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
1193 struct iris_compiled_shader
*shader
=
1194 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
1197 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
1200 shader
= iris_compile_tcs(ice
, tcs
, &key
);
1202 if (old
!= shader
) {
1203 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
1204 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
1205 IRIS_DIRTY_BINDINGS_TCS
|
1206 IRIS_DIRTY_CONSTANTS_TCS
;
1209 /* We're binding a passthrough TCS, which doesn't have uniforms.
1210 * Since there's no actual TCS, the state tracker doesn't bother
1211 * to call set_constant_buffers to clear stale constant buffers.
1213 * We do upload TCS constants for the default tesslevel system
1214 * values, however. In this case, we would see stale constant
1215 * data and try and read a dangling cbuf0->user_buffer pointer.
1216 * Just zero out the stale constants to avoid the upload.
1218 struct iris_shader_state
*shs
=
1219 &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
1221 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
1227 * Compile a tessellation evaluation shader, and upload the assembly.
1229 static struct iris_compiled_shader
*
1230 iris_compile_tes(struct iris_context
*ice
,
1231 struct iris_uncompiled_shader
*ish
,
1232 const struct brw_tes_prog_key
*key
)
1234 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1235 const struct brw_compiler
*compiler
= screen
->compiler
;
1236 void *mem_ctx
= ralloc_context(NULL
);
1237 struct brw_tes_prog_data
*tes_prog_data
=
1238 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1239 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1240 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1241 enum brw_param_builtin
*system_values
;
1242 unsigned num_system_values
;
1245 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1247 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1248 &num_system_values
, &num_cbufs
);
1250 struct iris_binding_table bt
;
1251 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1252 num_system_values
, num_cbufs
);
1254 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1256 struct brw_vue_map input_vue_map
;
1257 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1258 key
->patch_inputs_read
);
1260 char *error_str
= NULL
;
1261 const unsigned *program
=
1262 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
1263 tes_prog_data
, nir
, NULL
, -1, &error_str
);
1264 if (program
== NULL
) {
1265 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1266 ralloc_free(mem_ctx
);
1270 if (ish
->compiled_once
) {
1271 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1273 ish
->compiled_once
= true;
1276 uint32_t *so_decls
=
1277 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1278 &vue_prog_data
->vue_map
);
1281 struct iris_compiled_shader
*shader
=
1282 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1283 prog_data
, so_decls
, system_values
, num_system_values
,
1286 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1288 ralloc_free(mem_ctx
);
1293 * Update the current tessellation evaluation shader variant.
1295 * Fill out the key, look in the cache, compile and bind if needed.
1298 iris_update_compiled_tes(struct iris_context
*ice
)
1300 struct iris_uncompiled_shader
*ish
=
1301 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1302 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1303 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1305 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1306 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1307 ice
->vtbl
.populate_tes_key(ice
, &key
);
1309 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1310 struct iris_compiled_shader
*shader
=
1311 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1314 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1317 shader
= iris_compile_tes(ice
, ish
, &key
);
1319 if (old
!= shader
) {
1320 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1321 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1322 IRIS_DIRTY_BINDINGS_TES
|
1323 IRIS_DIRTY_CONSTANTS_TES
;
1326 /* TODO: Could compare and avoid flagging this. */
1327 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1328 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1329 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1330 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].cbuf0_needs_upload
= true;
1335 * Compile a geometry shader, and upload the assembly.
1337 static struct iris_compiled_shader
*
1338 iris_compile_gs(struct iris_context
*ice
,
1339 struct iris_uncompiled_shader
*ish
,
1340 const struct brw_gs_prog_key
*key
)
1342 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1343 const struct brw_compiler
*compiler
= screen
->compiler
;
1344 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1345 void *mem_ctx
= ralloc_context(NULL
);
1346 struct brw_gs_prog_data
*gs_prog_data
=
1347 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1348 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1349 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1350 enum brw_param_builtin
*system_values
;
1351 unsigned num_system_values
;
1354 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1356 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1357 &num_system_values
, &num_cbufs
);
1359 struct iris_binding_table bt
;
1360 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1361 num_system_values
, num_cbufs
);
1363 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1365 brw_compute_vue_map(devinfo
,
1366 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1367 nir
->info
.separate_shader
);
1369 char *error_str
= NULL
;
1370 const unsigned *program
=
1371 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1372 NULL
, -1, &error_str
);
1373 if (program
== NULL
) {
1374 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1375 ralloc_free(mem_ctx
);
1379 if (ish
->compiled_once
) {
1380 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1382 ish
->compiled_once
= true;
1385 uint32_t *so_decls
=
1386 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1387 &vue_prog_data
->vue_map
);
1389 struct iris_compiled_shader
*shader
=
1390 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1391 prog_data
, so_decls
, system_values
, num_system_values
,
1394 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1396 ralloc_free(mem_ctx
);
1401 * Update the current geometry shader variant.
1403 * Fill out the key, look in the cache, compile and bind if needed.
1406 iris_update_compiled_gs(struct iris_context
*ice
)
1408 struct iris_uncompiled_shader
*ish
=
1409 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1410 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1411 struct iris_compiled_shader
*shader
= NULL
;
1414 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1415 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1416 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1417 ice
->vtbl
.populate_gs_key(ice
, &key
);
1420 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1423 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1426 shader
= iris_compile_gs(ice
, ish
, &key
);
1429 if (old
!= shader
) {
1430 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1431 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1432 IRIS_DIRTY_BINDINGS_GS
|
1433 IRIS_DIRTY_CONSTANTS_GS
;
1438 * Compile a fragment (pixel) shader, and upload the assembly.
1440 static struct iris_compiled_shader
*
1441 iris_compile_fs(struct iris_context
*ice
,
1442 struct iris_uncompiled_shader
*ish
,
1443 const struct brw_wm_prog_key
*key
,
1444 struct brw_vue_map
*vue_map
)
1446 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1447 const struct brw_compiler
*compiler
= screen
->compiler
;
1448 void *mem_ctx
= ralloc_context(NULL
);
1449 struct brw_wm_prog_data
*fs_prog_data
=
1450 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1451 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1452 enum brw_param_builtin
*system_values
;
1453 unsigned num_system_values
;
1456 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1458 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1460 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1461 &num_system_values
, &num_cbufs
);
1463 struct iris_binding_table bt
;
1464 iris_setup_binding_table(nir
, &bt
, MAX2(key
->nr_color_regions
, 1),
1465 num_system_values
, num_cbufs
);
1467 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1469 char *error_str
= NULL
;
1470 const unsigned *program
=
1471 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1472 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1473 if (program
== NULL
) {
1474 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1475 ralloc_free(mem_ctx
);
1479 if (ish
->compiled_once
) {
1480 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1482 ish
->compiled_once
= true;
1485 struct iris_compiled_shader
*shader
=
1486 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1487 prog_data
, NULL
, system_values
, num_system_values
,
1490 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1492 ralloc_free(mem_ctx
);
1497 * Update the current fragment shader variant.
1499 * Fill out the key, look in the cache, compile and bind if needed.
1502 iris_update_compiled_fs(struct iris_context
*ice
)
1504 struct iris_uncompiled_shader
*ish
=
1505 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1506 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1507 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1508 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1509 ice
->vtbl
.populate_fs_key(ice
, &key
);
1511 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1512 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1514 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1515 struct iris_compiled_shader
*shader
=
1516 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1519 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1522 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1524 if (old
!= shader
) {
1525 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1526 // toggles. might be able to avoid flagging SBE too.
1527 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1528 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1529 IRIS_DIRTY_BINDINGS_FS
|
1530 IRIS_DIRTY_CONSTANTS_FS
|
1538 * Get the compiled shader for the last enabled geometry stage.
1540 * This stage is the one which will feed stream output and the rasterizer.
1542 static gl_shader_stage
1543 last_vue_stage(struct iris_context
*ice
)
1545 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
1546 return MESA_SHADER_GEOMETRY
;
1548 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
1549 return MESA_SHADER_TESS_EVAL
;
1551 return MESA_SHADER_VERTEX
;
1555 * Update the last enabled stage's VUE map.
1557 * When the shader feeding the rasterizer's output interface changes, we
1558 * need to re-emit various packets.
1561 update_last_vue_map(struct iris_context
*ice
,
1562 struct brw_stage_prog_data
*prog_data
)
1564 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1565 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1566 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1567 const uint64_t changed_slots
=
1568 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1570 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1571 // XXX: could use ctx->Const.MaxViewports for old API efficiency
1572 ice
->state
.num_viewports
=
1573 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1574 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1575 IRIS_DIRTY_SF_CL_VIEWPORT
|
1576 IRIS_DIRTY_CC_VIEWPORT
|
1577 IRIS_DIRTY_SCISSOR_RECT
|
1578 IRIS_DIRTY_UNCOMPILED_FS
|
1579 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1580 // XXX: CC_VIEWPORT?
1583 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1584 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1587 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1591 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1593 static struct brw_vue_prog_data
*
1594 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1596 if (!ice
->shaders
.prog
[stage
])
1599 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1602 // XXX: iris_compiled_shaders are space-leaking :(
1603 // XXX: do remember to unbind them if deleting them.
1606 * Update the current shader variants for the given state.
1608 * This should be called on every draw call to ensure that the correct
1609 * shaders are bound. It will also flag any dirty state triggered by
1610 * swapping out those shaders.
1613 iris_update_compiled_shaders(struct iris_context
*ice
)
1615 const uint64_t dirty
= ice
->state
.dirty
;
1617 struct brw_vue_prog_data
*old_prog_datas
[4];
1618 if (!(dirty
& IRIS_DIRTY_URB
)) {
1619 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1620 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1623 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1624 struct iris_uncompiled_shader
*tes
=
1625 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1627 iris_update_compiled_tcs(ice
);
1628 iris_update_compiled_tes(ice
);
1630 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1631 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1633 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1634 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1635 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1639 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1640 iris_update_compiled_vs(ice
);
1641 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1642 iris_update_compiled_gs(ice
);
1644 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1645 const struct iris_compiled_shader
*gs
=
1646 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1647 const struct iris_compiled_shader
*tes
=
1648 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1650 bool points_or_lines
= false;
1653 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1655 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1656 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1658 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1660 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1661 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1664 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1665 /* Outbound to XY Clip enables */
1666 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1667 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1671 gl_shader_stage last_stage
= last_vue_stage(ice
);
1672 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1673 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1674 update_last_vue_map(ice
, shader
->prog_data
);
1675 if (ice
->state
.streamout
!= shader
->streamout
) {
1676 ice
->state
.streamout
= shader
->streamout
;
1677 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1680 if (ice
->state
.streamout_active
) {
1681 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1682 struct iris_stream_output_target
*so
=
1683 (void *) ice
->state
.so_target
[i
];
1685 so
->stride
= ish
->stream_output
.stride
[i
] * sizeof(uint32_t);
1689 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1690 iris_update_compiled_fs(ice
);
1692 /* Changing shader interfaces may require a URB configuration. */
1693 if (!(dirty
& IRIS_DIRTY_URB
)) {
1694 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1695 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1696 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1697 if (!!old
!= !!new ||
1698 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1699 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1706 static struct iris_compiled_shader
*
1707 iris_compile_cs(struct iris_context
*ice
,
1708 struct iris_uncompiled_shader
*ish
,
1709 const struct brw_cs_prog_key
*key
)
1711 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1712 const struct brw_compiler
*compiler
= screen
->compiler
;
1713 void *mem_ctx
= ralloc_context(NULL
);
1714 struct brw_cs_prog_data
*cs_prog_data
=
1715 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1716 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1717 enum brw_param_builtin
*system_values
;
1718 unsigned num_system_values
;
1721 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1723 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1725 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1726 &num_system_values
, &num_cbufs
);
1728 struct iris_binding_table bt
;
1729 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1730 num_system_values
, num_cbufs
);
1732 char *error_str
= NULL
;
1733 const unsigned *program
=
1734 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1735 nir
, -1, &error_str
);
1736 if (program
== NULL
) {
1737 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1738 ralloc_free(mem_ctx
);
1742 if (ish
->compiled_once
) {
1743 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1745 ish
->compiled_once
= true;
1748 struct iris_compiled_shader
*shader
=
1749 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1750 prog_data
, NULL
, system_values
, num_system_values
,
1753 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1755 ralloc_free(mem_ctx
);
1760 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1762 struct iris_uncompiled_shader
*ish
=
1763 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1765 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1766 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1767 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1768 ice
->vtbl
.populate_cs_key(ice
, &key
);
1770 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1771 struct iris_compiled_shader
*shader
=
1772 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1775 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1778 shader
= iris_compile_cs(ice
, ish
, &key
);
1780 if (old
!= shader
) {
1781 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1782 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1783 IRIS_DIRTY_BINDINGS_CS
|
1784 IRIS_DIRTY_CONSTANTS_CS
;
1789 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1792 assert(cs_prog_data
->push
.total
.size
> 0);
1793 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1794 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1795 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1796 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1801 * Allocate scratch BOs as needed for the given per-thread size and stage.
1804 iris_get_scratch_space(struct iris_context
*ice
,
1805 unsigned per_thread_scratch
,
1806 gl_shader_stage stage
)
1808 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1809 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1810 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1812 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1813 assert(encoded_size
< (1 << 16));
1815 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1817 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1819 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1820 * must allocate scratch space enough so that each slice has 4
1823 * According to the other driver team, this applies to compute shaders
1824 * as well. This is not currently documented at all.
1826 * This hack is no longer necessary on Gen11+.
1828 unsigned subslice_total
= screen
->subslice_total
;
1829 if (devinfo
->gen
< 11)
1830 subslice_total
= 4 * devinfo
->num_slices
;
1831 assert(subslice_total
>= screen
->subslice_total
);
1834 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1835 uint32_t max_threads
[] = {
1836 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1837 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1838 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1839 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1840 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1841 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1844 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1846 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1852 /* ------------------------------------------------------------------- */
1855 * The pipe->create_[stage]_state() driver hooks.
1857 * Performs basic NIR preprocessing, records any state dependencies, and
1858 * returns an iris_uncompiled_shader as the Gallium CSO.
1860 * Actual shader compilation to assembly happens later, at first use.
1863 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1865 const struct pipe_stream_output_info
*so_info
)
1867 struct iris_context
*ice
= (void *)ctx
;
1868 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1869 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1871 struct iris_uncompiled_shader
*ish
=
1872 calloc(1, sizeof(struct iris_uncompiled_shader
));
1876 brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1878 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1879 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1883 if (nir
->constant_data_size
> 0) {
1884 unsigned data_offset
;
1885 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
1886 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
1888 struct pipe_shader_buffer psb
= {
1889 .buffer
= ish
->const_data
,
1890 .buffer_offset
= data_offset
,
1891 .buffer_size
= nir
->constant_data_size
,
1893 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
1896 ish
->program_id
= get_new_program_id(screen
);
1899 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1900 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1903 /* Save this now before potentially dropping nir->info.name */
1904 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1905 ish
->use_alt_mode
= true;
1907 if (screen
->disk_cache
) {
1908 /* Serialize the NIR to a binary blob that we can hash for the disk
1909 * cache. First, drop unnecessary information (like variable names)
1910 * so the serialized NIR is smaller, and also to let us detect more
1911 * isomorphic shaders when hashing, increasing cache hits. We clone
1912 * the NIR before stripping away this info because it can be useful
1913 * when inspecting and debugging shaders.
1915 nir_shader
*clone
= nir_shader_clone(NULL
, nir
);
1920 nir_serialize(&blob
, clone
);
1921 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
1930 static struct iris_uncompiled_shader
*
1931 iris_create_shader_state(struct pipe_context
*ctx
,
1932 const struct pipe_shader_state
*state
)
1934 struct nir_shader
*nir
;
1936 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1937 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1939 nir
= state
->ir
.nir
;
1941 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1945 iris_create_vs_state(struct pipe_context
*ctx
,
1946 const struct pipe_shader_state
*state
)
1948 struct iris_context
*ice
= (void *) ctx
;
1949 struct iris_screen
*screen
= (void *) ctx
->screen
;
1950 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1952 /* User clip planes */
1953 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1954 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
1956 if (screen
->precompile
) {
1957 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1958 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1960 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1961 iris_compile_vs(ice
, ish
, &key
);
1968 iris_create_tcs_state(struct pipe_context
*ctx
,
1969 const struct pipe_shader_state
*state
)
1971 struct iris_context
*ice
= (void *) ctx
;
1972 struct iris_screen
*screen
= (void *) ctx
->screen
;
1973 const struct brw_compiler
*compiler
= screen
->compiler
;
1974 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1975 struct shader_info
*info
= &ish
->nir
->info
;
1979 if (screen
->precompile
) {
1980 const unsigned _GL_TRIANGLES
= 0x0004;
1981 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1982 struct brw_tcs_prog_key key
= {
1983 KEY_INIT(devinfo
->gen
),
1984 // XXX: make sure the linker fills this out from the TES...
1985 .tes_primitive_mode
=
1986 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
1988 .outputs_written
= info
->outputs_written
,
1989 .patch_outputs_written
= info
->patch_outputs_written
,
1992 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
1993 * We don't have that information, so we randomly guess that the input
1994 * and output patches are the same size. This is a bad guess, but we
1995 * can't do much better.
1997 if (compiler
->use_tcs_8_patch
)
1998 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
2000 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2001 iris_compile_tcs(ice
, ish
, &key
);
2008 iris_create_tes_state(struct pipe_context
*ctx
,
2009 const struct pipe_shader_state
*state
)
2011 struct iris_context
*ice
= (void *) ctx
;
2012 struct iris_screen
*screen
= (void *) ctx
->screen
;
2013 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2014 struct shader_info
*info
= &ish
->nir
->info
;
2018 if (screen
->precompile
) {
2019 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2020 struct brw_tes_prog_key key
= {
2021 KEY_INIT(devinfo
->gen
),
2022 // XXX: not ideal, need TCS output/TES input unification
2023 .inputs_read
= info
->inputs_read
,
2024 .patch_inputs_read
= info
->patch_inputs_read
,
2027 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2028 iris_compile_tes(ice
, ish
, &key
);
2035 iris_create_gs_state(struct pipe_context
*ctx
,
2036 const struct pipe_shader_state
*state
)
2038 struct iris_context
*ice
= (void *) ctx
;
2039 struct iris_screen
*screen
= (void *) ctx
->screen
;
2040 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2044 if (screen
->precompile
) {
2045 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2046 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2048 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2049 iris_compile_gs(ice
, ish
, &key
);
2056 iris_create_fs_state(struct pipe_context
*ctx
,
2057 const struct pipe_shader_state
*state
)
2059 struct iris_context
*ice
= (void *) ctx
;
2060 struct iris_screen
*screen
= (void *) ctx
->screen
;
2061 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2062 struct shader_info
*info
= &ish
->nir
->info
;
2064 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
2065 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
2066 (1ull << IRIS_NOS_RASTERIZER
) |
2067 (1ull << IRIS_NOS_BLEND
);
2069 /* The program key needs the VUE map if there are > 16 inputs */
2070 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
2071 BRW_FS_VARYING_INPUT_MASK
) > 16) {
2072 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
2075 if (screen
->precompile
) {
2076 const uint64_t color_outputs
= info
->outputs_written
&
2077 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
2078 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
2079 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
2081 bool can_rearrange_varyings
=
2082 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
2084 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2085 struct brw_wm_prog_key key
= {
2086 KEY_INIT(devinfo
->gen
),
2087 .nr_color_regions
= util_bitcount(color_outputs
),
2088 .coherent_fb_fetch
= true,
2089 .input_slots_valid
=
2090 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
2093 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2094 iris_compile_fs(ice
, ish
, &key
, NULL
);
2101 iris_create_compute_state(struct pipe_context
*ctx
,
2102 const struct pipe_compute_state
*state
)
2104 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
2106 struct iris_context
*ice
= (void *) ctx
;
2107 struct iris_screen
*screen
= (void *) ctx
->screen
;
2108 struct iris_uncompiled_shader
*ish
=
2109 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
2111 // XXX: disallow more than 64KB of shared variables
2113 if (screen
->precompile
) {
2114 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2115 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2117 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2118 iris_compile_cs(ice
, ish
, &key
);
2125 * The pipe->delete_[stage]_state() driver hooks.
2127 * Frees the iris_uncompiled_shader.
2130 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
2132 struct iris_uncompiled_shader
*ish
= state
;
2133 struct iris_context
*ice
= (void *) ctx
;
2135 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
2136 ice
->shaders
.uncompiled
[stage
] = NULL
;
2137 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2140 if (ish
->const_data
) {
2141 pipe_resource_reference(&ish
->const_data
, NULL
);
2142 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
2145 ralloc_free(ish
->nir
);
2150 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
2152 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
2156 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
2158 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
2162 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
2164 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
2168 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
2170 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
2174 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
2176 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
2180 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
2182 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
2186 * The pipe->bind_[stage]_state() driver hook.
2188 * Binds an uncompiled shader as the current one for a particular stage.
2189 * Updates dirty tracking to account for the shader's NOS.
2192 bind_shader_state(struct iris_context
*ice
,
2193 struct iris_uncompiled_shader
*ish
,
2194 gl_shader_stage stage
)
2196 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2197 const uint64_t nos
= ish
? ish
->nos
: 0;
2199 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
2200 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
2202 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
2203 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
2204 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
2207 ice
->shaders
.uncompiled
[stage
] = ish
;
2208 ice
->state
.dirty
|= dirty_bit
;
2210 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
2211 * (or that they no longer need to do so).
2213 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
2215 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
2217 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
2222 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
2224 bind_shader_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
2228 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
2230 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
2234 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
2236 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2238 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2239 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
2240 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2242 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
2246 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
2248 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2250 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2251 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
2252 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2254 bind_shader_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
2258 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
2260 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2261 struct iris_uncompiled_shader
*old_ish
=
2262 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2263 struct iris_uncompiled_shader
*new_ish
= state
;
2265 const unsigned color_bits
=
2266 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
2267 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
2269 /* Fragment shader outputs influence HasWriteableRT */
2270 if (!old_ish
|| !new_ish
||
2271 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
2272 (new_ish
->nir
->info
.outputs_written
& color_bits
))
2273 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
2275 bind_shader_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
2279 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
2281 bind_shader_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
2285 iris_init_program_functions(struct pipe_context
*ctx
)
2287 ctx
->create_vs_state
= iris_create_vs_state
;
2288 ctx
->create_tcs_state
= iris_create_tcs_state
;
2289 ctx
->create_tes_state
= iris_create_tes_state
;
2290 ctx
->create_gs_state
= iris_create_gs_state
;
2291 ctx
->create_fs_state
= iris_create_fs_state
;
2292 ctx
->create_compute_state
= iris_create_compute_state
;
2294 ctx
->delete_vs_state
= iris_delete_vs_state
;
2295 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
2296 ctx
->delete_tes_state
= iris_delete_tes_state
;
2297 ctx
->delete_gs_state
= iris_delete_gs_state
;
2298 ctx
->delete_fs_state
= iris_delete_fs_state
;
2299 ctx
->delete_compute_state
= iris_delete_cs_state
;
2301 ctx
->bind_vs_state
= iris_bind_vs_state
;
2302 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2303 ctx
->bind_tes_state
= iris_bind_tes_state
;
2304 ctx
->bind_gs_state
= iris_bind_gs_state
;
2305 ctx
->bind_fs_state
= iris_bind_fs_state
;
2306 ctx
->bind_compute_state
= iris_bind_cs_state
;