2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
46 get_new_program_id(struct iris_screen
*screen
)
48 return p_atomic_inc_return(&screen
->program_id
);
52 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
53 * It primarily contains the NIR for the shader.
55 * Each API-facing shader can be compiled into multiple shader variants,
56 * based on non-orthogonal state dependencies, recorded in the shader key.
58 * See iris_compiled_shader, which represents a compiled shader variant.
60 struct iris_uncompiled_shader
{
63 struct pipe_stream_output_info stream_output
;
67 /** Bitfield of (1 << IRIS_NOS_*) flags. */
71 // XXX: need unify_interfaces() at link time...
74 * The pipe->create_[stage]_state() driver hooks.
76 * Performs basic NIR preprocessing, records any state dependencies, and
77 * returns an iris_uncompiled_shader as the Gallium CSO.
79 * Actual shader compilation to assembly happens later, at first use.
82 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
84 const struct pipe_stream_output_info
*so_info
)
86 //struct iris_context *ice = (struct iris_context *)ctx;
87 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
89 struct iris_uncompiled_shader
*ish
=
90 calloc(1, sizeof(struct iris_uncompiled_shader
));
94 nir
= brw_preprocess_nir(screen
->compiler
, nir
);
96 ish
->program_id
= get_new_program_id(screen
);
99 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
101 switch (nir
->info
.stage
) {
102 case MESA_SHADER_VERTEX
:
105 case MESA_SHADER_TESS_CTRL
:
108 case MESA_SHADER_TESS_EVAL
:
111 case MESA_SHADER_GEOMETRY
:
114 case MESA_SHADER_FRAGMENT
:
115 ish
->nos
|= IRIS_NOS_FRAMEBUFFER
|
116 IRIS_NOS_DEPTH_STENCIL_ALPHA
|
117 IRIS_NOS_RASTERIZER
|
120 /* The program key needs the VUE map if there are > 16 inputs */
121 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
122 BRW_FS_VARYING_INPUT_MASK
) > 16) {
123 ish
->nos
|= IRIS_NOS_LAST_VUE_MAP
;
126 case MESA_SHADER_COMPUTE
:
139 * The pipe->delete_[stage]_state() driver hooks.
141 * Frees the iris_uncompiled_shader.
144 iris_create_shader_state(struct pipe_context
*ctx
,
145 const struct pipe_shader_state
*state
)
147 assert(state
->type
== PIPE_SHADER_IR_NIR
);
149 return iris_create_uncompiled_shader(ctx
, state
->ir
.nir
,
150 &state
->stream_output
);
154 iris_create_compute_state(struct pipe_context
*ctx
,
155 const struct pipe_compute_state
*state
)
157 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
159 return iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
163 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
165 struct iris_uncompiled_shader
*ish
= state
;
167 ralloc_free(ish
->nir
);
172 * The pipe->bind_[stage]_state() driver hook.
174 * Binds an uncompiled shader as the current one for a particular stage.
175 * Updates dirty tracking to account for the shader's NOS.
178 bind_state(struct iris_context
*ice
,
179 struct iris_uncompiled_shader
*ish
,
180 gl_shader_stage stage
)
182 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
183 const uint64_t nos
= ish
? ish
->nos
: 0;
185 ice
->shaders
.uncompiled
[stage
] = ish
;
186 ice
->state
.dirty
|= dirty_bit
;
188 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
189 * (or that they no longer need to do so).
191 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
193 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
195 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
200 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
202 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
206 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
208 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
212 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
214 struct iris_context
*ice
= (struct iris_context
*)ctx
;
216 /* Enabling/disabling optional stages requires a URB reconfiguration. */
217 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
218 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
220 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
224 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
226 struct iris_context
*ice
= (struct iris_context
*)ctx
;
228 /* Enabling/disabling optional stages requires a URB reconfiguration. */
229 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
230 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
232 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
236 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
238 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
242 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
244 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
248 * Sets up the starting offsets for the groups of binding table entries
249 * common to all pipeline stages.
251 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
252 * unused but also make sure that addition of small offsets to them will
253 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
256 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
257 const struct nir_shader
*nir
,
258 struct brw_stage_prog_data
*prog_data
,
259 uint32_t next_binding_table_offset
)
261 const struct shader_info
*info
= &nir
->info
;
263 if (info
->num_textures
) {
264 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
265 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
266 next_binding_table_offset
+= info
->num_textures
;
268 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
269 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
272 int num_ubos
= info
->num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
275 //assert(info->num_ubos <= BRW_MAX_UBO);
276 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
277 next_binding_table_offset
+= num_ubos
;
279 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
282 if (info
->num_ssbos
|| info
->num_abos
) {
283 //assert(info->num_abos <= BRW_MAX_ABO);
284 //assert(info->num_ssbos <= BRW_MAX_SSBO);
285 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
286 next_binding_table_offset
+= info
->num_abos
+ info
->num_ssbos
;
288 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
291 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
293 if (info
->num_images
) {
294 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
295 next_binding_table_offset
+= info
->num_images
;
297 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
300 /* This may or may not be used depending on how the compile goes. */
301 prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
302 next_binding_table_offset
++;
304 /* Plane 0 is just the regular texture section */
305 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
307 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
308 next_binding_table_offset
+= info
->num_textures
;
310 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
311 next_binding_table_offset
+= info
->num_textures
;
313 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
315 //assert(next_binding_table_offset <= BRW_MAX_SURFACES);
316 return next_binding_table_offset
;
320 * Associate NIR uniform variables with the prog_data->param[] mechanism
321 * used by the backend. Also, decide which UBOs we'd like to push in an
322 * ideal situation (though the backend can reduce this).
325 iris_setup_uniforms(const struct brw_compiler
*compiler
,
328 struct brw_stage_prog_data
*prog_data
)
330 prog_data
->nr_params
= nir
->num_uniforms
;
331 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
333 nir_foreach_variable(var
, &nir
->uniforms
) {
334 const unsigned components
= glsl_get_components(var
->type
);
336 for (unsigned i
= 0; i
< components
; i
++) {
337 prog_data
->param
[var
->data
.driver_location
] =
338 var
->data
.driver_location
;
342 // XXX: vs clip planes?
343 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
347 * If we still have regular uniforms as push constants after the backend
348 * compilation, set up a UBO range for them. This will be used to fill
349 * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
352 iris_setup_push_uniform_range(const struct brw_compiler
*compiler
,
353 struct brw_stage_prog_data
*prog_data
)
355 if (prog_data
->nr_params
) {
356 for (int i
= 3; i
> 0; i
--)
357 prog_data
->ubo_ranges
[i
] = prog_data
->ubo_ranges
[i
- 1];
359 prog_data
->ubo_ranges
[0] = (struct brw_ubo_range
) {
362 .length
= DIV_ROUND_UP(prog_data
->nr_params
, 8),
368 * Compile a vertex shader, and upload the assembly.
371 iris_compile_vs(struct iris_context
*ice
,
372 struct iris_uncompiled_shader
*ish
,
373 const struct brw_vs_prog_key
*key
)
375 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
376 const struct brw_compiler
*compiler
= screen
->compiler
;
377 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
378 void *mem_ctx
= ralloc_context(NULL
);
379 struct brw_vs_prog_data
*vs_prog_data
=
380 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
381 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
382 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
384 nir_shader
*nir
= ish
->nir
;
387 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
389 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
391 brw_compute_vue_map(devinfo
,
392 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
393 nir
->info
.separate_shader
);
395 char *error_str
= NULL
;
396 const unsigned *program
=
397 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, key
, vs_prog_data
,
398 nir
, -1, &error_str
);
399 if (program
== NULL
) {
400 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
401 ralloc_free(mem_ctx
);
405 iris_setup_push_uniform_range(compiler
, prog_data
);
408 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
409 &vue_prog_data
->vue_map
);
411 iris_upload_and_bind_shader(ice
, IRIS_CACHE_VS
, key
, program
, prog_data
,
414 ralloc_free(mem_ctx
);
419 * Update the current vertex shader variant.
421 * Fill out the key, look in the cache, compile and bind if needed.
424 iris_update_compiled_vs(struct iris_context
*ice
)
426 struct iris_uncompiled_shader
*ish
=
427 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
429 struct brw_vs_prog_key key
= { .program_string_id
= ish
->program_id
};
430 ice
->vtbl
.populate_vs_key(ice
, &key
);
432 if (iris_bind_cached_shader(ice
, IRIS_CACHE_VS
, &key
))
435 UNUSED
bool success
= iris_compile_vs(ice
, ish
, &key
);
439 * Get the shader_info for a given stage, or NULL if the stage is disabled.
441 const struct shader_info
*
442 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
444 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
449 const nir_shader
*nir
= ish
->nir
;
454 * Get the union of TCS output and TES input slots.
456 * TCS and TES need to agree on a common URB entry layout. In particular,
457 * the data for all patch vertices is stored in a single URB entry (unlike
458 * GS which has one entry per input vertex). This means that per-vertex
459 * array indexing needs a stride.
461 * SSO requires locations to match, but doesn't require the number of
462 * outputs/inputs to match (in fact, the TCS often has extra outputs).
463 * So, we need to take the extra step of unifying these on the fly.
466 get_unified_tess_slots(const struct iris_context
*ice
,
467 uint64_t *per_vertex_slots
,
468 uint32_t *per_patch_slots
)
470 const struct shader_info
*tcs
=
471 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
472 const struct shader_info
*tes
=
473 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
475 *per_vertex_slots
= tes
->inputs_read
;
476 *per_patch_slots
= tes
->patch_inputs_read
;
479 *per_vertex_slots
|= tcs
->inputs_read
;
480 *per_patch_slots
|= tcs
->patch_inputs_read
;
485 * Compile a tessellation control shader, and upload the assembly.
488 iris_compile_tcs(struct iris_context
*ice
,
489 struct iris_uncompiled_shader
*ish
,
490 const struct brw_tcs_prog_key
*key
)
492 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
493 const struct brw_compiler
*compiler
= screen
->compiler
;
494 const struct nir_shader_compiler_options
*options
=
495 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
496 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
497 void *mem_ctx
= ralloc_context(NULL
);
498 struct brw_tcs_prog_data
*tcs_prog_data
=
499 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
500 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
501 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
508 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
509 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
511 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
513 /* Reserve space for passing the default tess levels as constants. */
514 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
515 prog_data
->nr_params
= 8;
516 prog_data
->ubo_ranges
[0].length
= 1;
519 char *error_str
= NULL
;
520 const unsigned *program
=
521 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
523 if (program
== NULL
) {
524 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
525 ralloc_free(mem_ctx
);
529 iris_setup_push_uniform_range(compiler
, prog_data
);
531 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TCS
, key
, program
, prog_data
,
534 ralloc_free(mem_ctx
);
539 * Update the current tessellation control shader variant.
541 * Fill out the key, look in the cache, compile and bind if needed.
544 iris_update_compiled_tcs(struct iris_context
*ice
)
546 struct iris_uncompiled_shader
*tcs
=
547 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
549 const struct shader_info
*tes_info
=
550 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
551 struct brw_tcs_prog_key key
= {
552 .program_string_id
= tcs
? tcs
->program_id
: 0,
553 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
554 .input_vertices
= ice
->state
.vertices_per_patch
,
556 get_unified_tess_slots(ice
, &key
.outputs_written
,
557 &key
.patch_outputs_written
);
558 ice
->vtbl
.populate_tcs_key(ice
, &key
);
560 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TCS
, &key
))
563 UNUSED
bool success
= iris_compile_tcs(ice
, tcs
, &key
);
567 * Compile a tessellation evaluation shader, and upload the assembly.
570 iris_compile_tes(struct iris_context
*ice
,
571 struct iris_uncompiled_shader
*ish
,
572 const struct brw_tes_prog_key
*key
)
574 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
575 const struct brw_compiler
*compiler
= screen
->compiler
;
576 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
577 void *mem_ctx
= ralloc_context(NULL
);
578 struct brw_tes_prog_data
*tes_prog_data
=
579 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
580 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
581 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
583 nir_shader
*nir
= ish
->nir
;
585 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
587 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
589 struct brw_vue_map input_vue_map
;
590 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
591 key
->patch_inputs_read
);
593 char *error_str
= NULL
;
594 const unsigned *program
=
595 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
596 tes_prog_data
, nir
, NULL
, -1, &error_str
);
597 if (program
== NULL
) {
598 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
599 ralloc_free(mem_ctx
);
603 iris_setup_push_uniform_range(compiler
, prog_data
);
606 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
607 &vue_prog_data
->vue_map
);
609 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TES
, key
, program
, prog_data
,
612 ralloc_free(mem_ctx
);
617 * Update the current tessellation evaluation shader variant.
619 * Fill out the key, look in the cache, compile and bind if needed.
622 iris_update_compiled_tes(struct iris_context
*ice
)
624 struct iris_uncompiled_shader
*ish
=
625 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
627 struct brw_tes_prog_key key
= { .program_string_id
= ish
->program_id
};
628 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
629 ice
->vtbl
.populate_tes_key(ice
, &key
);
631 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TES
, &key
))
634 UNUSED
bool success
= iris_compile_tes(ice
, ish
, &key
);
638 * Compile a geometry shader, and upload the assembly.
641 iris_compile_gs(struct iris_context
*ice
,
642 struct iris_uncompiled_shader
*ish
,
643 const struct brw_gs_prog_key
*key
)
645 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
646 const struct brw_compiler
*compiler
= screen
->compiler
;
647 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
648 void *mem_ctx
= ralloc_context(NULL
);
649 struct brw_gs_prog_data
*gs_prog_data
=
650 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
651 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
652 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
654 nir_shader
*nir
= ish
->nir
;
656 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
658 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
660 brw_compute_vue_map(devinfo
,
661 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
662 nir
->info
.separate_shader
);
664 char *error_str
= NULL
;
665 const unsigned *program
=
666 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
667 NULL
, -1, &error_str
);
668 if (program
== NULL
) {
669 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
670 ralloc_free(mem_ctx
);
674 iris_setup_push_uniform_range(compiler
, prog_data
);
677 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
678 &vue_prog_data
->vue_map
);
680 iris_upload_and_bind_shader(ice
, IRIS_CACHE_GS
, key
, program
, prog_data
,
683 ralloc_free(mem_ctx
);
688 * Update the current geometry shader variant.
690 * Fill out the key, look in the cache, compile and bind if needed.
693 iris_update_compiled_gs(struct iris_context
*ice
)
695 struct iris_uncompiled_shader
*ish
=
696 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
699 iris_unbind_shader(ice
, IRIS_CACHE_GS
);
703 struct brw_gs_prog_key key
= { .program_string_id
= ish
->program_id
};
704 ice
->vtbl
.populate_gs_key(ice
, &key
);
706 if (iris_bind_cached_shader(ice
, IRIS_CACHE_GS
, &key
))
709 UNUSED
bool success
= iris_compile_gs(ice
, ish
, &key
);
713 * Compile a fragment (pixel) shader, and upload the assembly.
716 iris_compile_fs(struct iris_context
*ice
,
717 struct iris_uncompiled_shader
*ish
,
718 const struct brw_wm_prog_key
*key
,
719 struct brw_vue_map
*vue_map
)
721 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
722 const struct brw_compiler
*compiler
= screen
->compiler
;
723 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
724 void *mem_ctx
= ralloc_context(NULL
);
725 struct brw_wm_prog_data
*fs_prog_data
=
726 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
727 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
729 nir_shader
*nir
= ish
->nir
;
732 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
733 MAX2(key
->nr_color_regions
, 1));
735 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
737 char *error_str
= NULL
;
738 const unsigned *program
=
739 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
740 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
741 if (program
== NULL
) {
742 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
743 ralloc_free(mem_ctx
);
747 //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
749 iris_setup_push_uniform_range(compiler
, prog_data
);
751 iris_upload_and_bind_shader(ice
, IRIS_CACHE_FS
, key
, program
, prog_data
,
754 ralloc_free(mem_ctx
);
759 * Update the current fragment shader variant.
761 * Fill out the key, look in the cache, compile and bind if needed.
764 iris_update_compiled_fs(struct iris_context
*ice
)
766 struct iris_uncompiled_shader
*ish
=
767 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
768 struct brw_wm_prog_key key
= { .program_string_id
= ish
->program_id
};
769 ice
->vtbl
.populate_fs_key(ice
, &key
);
771 if (ish
->nos
& IRIS_NOS_LAST_VUE_MAP
)
772 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
774 if (iris_bind_cached_shader(ice
, IRIS_CACHE_FS
, &key
))
777 UNUSED
bool success
=
778 iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
782 * Get the compiled shader for the last enabled geometry stage.
784 * This stage is the one which will feed stream output and the rasterizer.
786 static struct iris_compiled_shader
*
787 last_vue_shader(struct iris_context
*ice
)
789 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
790 return ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
792 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
793 return ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
795 return ice
->shaders
.prog
[MESA_SHADER_VERTEX
];
799 * Update the last enabled stage's VUE map.
801 * When the shader feeding the rasterizer's output interface changes, we
802 * need to re-emit various packets.
805 update_last_vue_map(struct iris_context
*ice
,
806 struct brw_stage_prog_data
*prog_data
)
808 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
809 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
810 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
811 const uint64_t changed_slots
=
812 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
814 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
815 // XXX: could use ctx->Const.MaxViewports for old API efficiency
816 ice
->state
.num_viewports
=
817 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
818 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
819 IRIS_DIRTY_SF_CL_VIEWPORT
|
820 IRIS_DIRTY_SCISSOR_RECT
|
821 IRIS_DIRTY_UNCOMPILED_FS
|
822 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
826 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
827 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
830 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
834 * Get the prog_data for a given stage, or NULL if the stage is disabled.
836 static struct brw_vue_prog_data
*
837 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
839 if (!ice
->shaders
.prog
[stage
])
842 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
846 * Update the current shader variants for the given state.
848 * This should be called on every draw call to ensure that the correct
849 * shaders are bound. It will also flag any dirty state triggered by
850 * swapping out those shaders.
853 iris_update_compiled_shaders(struct iris_context
*ice
)
855 const uint64_t dirty
= ice
->state
.dirty
;
857 struct brw_vue_prog_data
*old_prog_datas
[4];
858 if (!(dirty
& IRIS_DIRTY_URB
)) {
859 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
860 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
863 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
864 struct iris_uncompiled_shader
*tes
=
865 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
867 iris_update_compiled_tcs(ice
);
868 iris_update_compiled_tes(ice
);
870 iris_unbind_shader(ice
, IRIS_CACHE_TCS
);
871 iris_unbind_shader(ice
, IRIS_CACHE_TES
);
875 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
876 iris_update_compiled_vs(ice
);
877 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
878 iris_update_compiled_gs(ice
);
880 struct iris_compiled_shader
*shader
= last_vue_shader(ice
);
881 update_last_vue_map(ice
, shader
->prog_data
);
882 if (ice
->state
.streamout
!= shader
->streamout
) {
883 ice
->state
.streamout
= shader
->streamout
;
884 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
887 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
888 iris_update_compiled_fs(ice
);
891 /* Changing shader interfaces may require a URB configuration. */
892 if (!(dirty
& IRIS_DIRTY_URB
)) {
893 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
894 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
895 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
896 if (!!old
!= !!new ||
897 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
898 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
906 iris_init_program_functions(struct pipe_context
*ctx
)
908 ctx
->create_vs_state
= iris_create_shader_state
;
909 ctx
->create_tcs_state
= iris_create_shader_state
;
910 ctx
->create_tes_state
= iris_create_shader_state
;
911 ctx
->create_gs_state
= iris_create_shader_state
;
912 ctx
->create_fs_state
= iris_create_shader_state
;
913 ctx
->create_compute_state
= iris_create_compute_state
;
915 ctx
->delete_vs_state
= iris_delete_shader_state
;
916 ctx
->delete_tcs_state
= iris_delete_shader_state
;
917 ctx
->delete_tes_state
= iris_delete_shader_state
;
918 ctx
->delete_gs_state
= iris_delete_shader_state
;
919 ctx
->delete_fs_state
= iris_delete_shader_state
;
920 ctx
->delete_compute_state
= iris_delete_shader_state
;
922 ctx
->bind_vs_state
= iris_bind_vs_state
;
923 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
924 ctx
->bind_tes_state
= iris_bind_tes_state
;
925 ctx
->bind_gs_state
= iris_bind_gs_state
;
926 ctx
->bind_fs_state
= iris_bind_fs_state
;
927 ctx
->bind_compute_state
= iris_bind_cs_state
;