src/gallium/drivers/iris/iris_program.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_atomic.h"
  30 #include "compiler/nir/nir.h"
  31 #include "compiler/nir/nir_builder.h"
  32 #include "intel/compiler/brw_compiler.h"
  33 #include "intel/compiler/brw_nir.h"
  34 #include "iris_context.h"
  35
  36 static unsigned
  37 get_new_program_id(struct iris_screen *screen)
  38 {
  39    return p_atomic_inc_return(&screen->program_id);
  40 }
  41
  42 struct iris_uncompiled_shader {
  43    struct pipe_shader_state base;
  44    unsigned program_id;
  45 };
  46
  47 // XXX: need unify_interfaces() at link time...
  48
  49 static void *
  50 iris_create_shader_state(struct pipe_context *ctx,
  51                          const struct pipe_shader_state *state)
  52 {
  53    //struct iris_context *ice = (struct iris_context *)ctx;
  54    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
  55
  56    assert(state->type == PIPE_SHADER_IR_NIR);
  57
  58    nir_shader *nir = state->ir.nir;
  59
  60    struct iris_uncompiled_shader *ish =
  61       calloc(1, sizeof(struct iris_uncompiled_shader));
  62    if (!ish)
  63       return NULL;
  64
  65    nir = brw_preprocess_nir(screen->compiler, nir);
  66
  67 #if 0
  68    /* Reassign uniform locations using type_size_scalar_bytes instead of
  69     * the slot based calculation that st_nir uses.
  70     */
  71    nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
  72                             type_size_scalar_bytes);
  73    nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes, 0);
  74 #endif
  75    nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes, 0);
  76
  77    ish->program_id = get_new_program_id(screen);
  78    ish->base.type = PIPE_SHADER_IR_NIR;
  79    ish->base.ir.nir = nir;
  80
  81    return ish;
  82 }
  83
  84 static void
  85 iris_delete_shader_state(struct pipe_context *ctx, void *hwcso)
  86 {
  87    struct iris_uncompiled_shader *ish = hwcso;
  88
  89    ralloc_free(ish->base.ir.nir);
  90    free(ish);
  91 }
  92
  93 static void
  94 iris_bind_vs_state(struct pipe_context *ctx, void *hwcso)
  95 {
  96    struct iris_context *ice = (struct iris_context *)ctx;
  97
  98    ice->shaders.uncompiled[MESA_SHADER_VERTEX] = hwcso;
  99    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_VS;
 100 }
 101
 102 static void
 103 iris_bind_tcs_state(struct pipe_context *ctx, void *hwcso)
 104 {
 105    struct iris_context *ice = (struct iris_context *)ctx;
 106
 107    ice->shaders.uncompiled[MESA_SHADER_TESS_CTRL] = hwcso;
 108    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TCS;
 109 }
 110
 111 static void
 112 iris_bind_tes_state(struct pipe_context *ctx, void *hwcso)
 113 {
 114    struct iris_context *ice = (struct iris_context *)ctx;
 115
 116    if (!!hwcso != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
 117       ice->state.dirty |= IRIS_DIRTY_URB;
 118
 119    ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL] = hwcso;
 120    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TES;
 121 }
 122
 123 static void
 124 iris_bind_gs_state(struct pipe_context *ctx, void *hwcso)
 125 {
 126    struct iris_context *ice = (struct iris_context *)ctx;
 127
 128    if (!!hwcso != !!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
 129       ice->state.dirty |= IRIS_DIRTY_URB;
 130
 131    ice->shaders.uncompiled[MESA_SHADER_GEOMETRY] = hwcso;
 132    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_GS;
 133 }
 134
 135 static void
 136 iris_bind_fs_state(struct pipe_context *ctx, void *hwcso)
 137 {
 138    struct iris_context *ice = (struct iris_context *)ctx;
 139
 140    ice->shaders.uncompiled[MESA_SHADER_FRAGMENT] = hwcso;
 141    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_FS;
 142 }
 143
 144 /**
 145  * Sets up the starting offsets for the groups of binding table entries
 146  * common to all pipeline stages.
 147  *
 148  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 149  * unused but also make sure that addition of small offsets to them will
 150  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 151  */
 152 static uint32_t
 153 assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
 154                                     const struct shader_info *info,
 155                                     struct brw_stage_prog_data *prog_data,
 156                                     uint32_t next_binding_table_offset)
 157 {
 158    if (info->num_textures) {
 159       prog_data->binding_table.texture_start = next_binding_table_offset;
 160       prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 161       next_binding_table_offset += info->num_textures;
 162    } else {
 163       prog_data->binding_table.texture_start = 0xd0d0d0d0;
 164       prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
 165    }
 166
 167    if (info->num_ubos) {
 168       //assert(info->num_ubos <= BRW_MAX_UBO);
 169       prog_data->binding_table.ubo_start = next_binding_table_offset;
 170       next_binding_table_offset += info->num_ubos;
 171    } else {
 172       prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 173    }
 174
 175    if (info->num_ssbos || info->num_abos) {
 176       //assert(info->num_abos <= BRW_MAX_ABO);
 177       //assert(info->num_ssbos <= BRW_MAX_SSBO);
 178       prog_data->binding_table.ssbo_start = next_binding_table_offset;
 179       next_binding_table_offset += info->num_abos + info->num_ssbos;
 180    } else {
 181       prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
 182    }
 183
 184    prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 185
 186    if (info->num_images) {
 187       prog_data->binding_table.image_start = next_binding_table_offset;
 188       next_binding_table_offset += info->num_images;
 189    } else {
 190       prog_data->binding_table.image_start = 0xd0d0d0d0;
 191    }
 192
 193    /* This may or may not be used depending on how the compile goes. */
 194    prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 195    next_binding_table_offset++;
 196
 197    /* Plane 0 is just the regular texture section */
 198    prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
 199
 200    prog_data->binding_table.plane_start[1] = next_binding_table_offset;
 201    next_binding_table_offset += info->num_textures;
 202
 203    prog_data->binding_table.plane_start[2] = next_binding_table_offset;
 204    next_binding_table_offset += info->num_textures;
 205
 206    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 207
 208    //assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 209    return next_binding_table_offset;
 210 }
 211
 212 static void
 213 iris_setup_uniforms(void *mem_ctx,
 214                     nir_shader *nir,
 215                     struct brw_stage_prog_data *prog_data)
 216 {
 217    prog_data->nr_params = nir->num_uniforms * 4;
 218    prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
 219
 220    nir->num_uniforms *= 16;
 221
 222    nir_foreach_variable(var, &nir->uniforms) {
 223       /* UBO's, atomics and samplers don't take up space */
 224       //if (var->interface_type != NULL || var->type->contains_atomic())
 225          //continue;
 226
 227       const unsigned components = glsl_get_components(var->type);
 228
 229       for (unsigned i = 0; i < 4; i++) {
 230          prog_data->param[var->data.driver_location] =
 231             i < components ? BRW_PARAM_PARAMETER(var->data.driver_location, i)
 232                            : BRW_PARAM_BUILTIN_ZERO;
 233       }
 234    }
 235 }
 236
 237 static bool
 238 iris_compile_vs(struct iris_context *ice,
 239                 struct iris_uncompiled_shader *ish,
 240                 const struct brw_vs_prog_key *key)
 241 {
 242    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 243    const struct brw_compiler *compiler = screen->compiler;
 244    const struct gen_device_info *devinfo = &screen->devinfo;
 245    void *mem_ctx = ralloc_context(NULL);
 246    struct brw_vs_prog_data *vs_prog_data =
 247       rzalloc(mem_ctx, struct brw_vs_prog_data);
 248    struct brw_vue_prog_data *vue_prog_data = &vs_prog_data->base;
 249    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 250
 251    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 252
 253    nir_shader *nir = ish->base.ir.nir;
 254
 255    // XXX: alt mode
 256    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data, 0);
 257    brw_compute_vue_map(devinfo,
 258                        &vue_prog_data->vue_map, nir->info.outputs_written,
 259                        nir->info.separate_shader);
 260
 261    char *error_str = NULL;
 262    const unsigned *program =
 263       brw_compile_vs(compiler, &ice->dbg, mem_ctx, key, vs_prog_data,
 264                      nir, -1, &error_str);
 265    if (program == NULL) {
 266       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 267       ralloc_free(mem_ctx);
 268       return false;
 269    }
 270
 271    iris_upload_and_bind_shader(ice, IRIS_CACHE_VS, key, program, prog_data);
 272
 273    ralloc_free(mem_ctx);
 274    return true;
 275 }
 276
 277 static void
 278 iris_update_compiled_vs(struct iris_context *ice)
 279 {
 280    struct brw_vs_prog_key key;
 281    ice->state.populate_vs_key(ice, &key);
 282
 283    if (iris_bind_cached_shader(ice, IRIS_CACHE_VS, &key))
 284       return;
 285
 286    UNUSED bool success =
 287       iris_compile_vs(ice, ice->shaders.uncompiled[MESA_SHADER_VERTEX], &key);
 288 }
 289
 290 static void
 291 iris_update_compiled_tcs(struct iris_context *ice)
 292 {
 293    // XXX: TCS
 294 }
 295
 296 static bool
 297 iris_compile_tes(struct iris_context *ice,
 298                  struct iris_uncompiled_shader *ish,
 299                  const struct brw_tes_prog_key *key)
 300 {
 301    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 302    const struct brw_compiler *compiler = screen->compiler;
 303    const struct gen_device_info *devinfo = &screen->devinfo;
 304    void *mem_ctx = ralloc_context(NULL);
 305    struct brw_tes_prog_data *tes_prog_data =
 306       rzalloc(mem_ctx, struct brw_tes_prog_data);
 307    struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
 308    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 309
 310    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 311
 312    nir_shader *nir = ish->base.ir.nir;
 313
 314    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data, 0);
 315
 316    struct brw_vue_map input_vue_map;
 317    brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
 318                             key->patch_inputs_read);
 319
 320    char *error_str = NULL;
 321    const unsigned *program =
 322       brw_compile_tes(compiler, &ice->dbg, mem_ctx, key, &input_vue_map,
 323                       tes_prog_data, nir, NULL, -1, &error_str);
 324    if (program == NULL) {
 325       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 326       ralloc_free(mem_ctx);
 327       return false;
 328    }
 329
 330    iris_upload_and_bind_shader(ice, IRIS_CACHE_TES, key, program, prog_data);
 331
 332    ralloc_free(mem_ctx);
 333    return true;
 334 }
 335
 336
 337 static void
 338 iris_update_compiled_tes(struct iris_context *ice)
 339 {
 340    struct iris_uncompiled_shader *ish =
 341       ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
 342
 343    if (!ish)
 344       return;
 345
 346    struct brw_tes_prog_key key;
 347    ice->state.populate_tes_key(ice, &key);
 348
 349    if (iris_bind_cached_shader(ice, IRIS_CACHE_TES, &key))
 350       return;
 351
 352    UNUSED bool success = iris_compile_tes(ice, ish, &key);
 353 }
 354
 355 static void
 356 iris_update_compiled_gs(struct iris_context *ice)
 357 {
 358    // XXX: GS
 359 }
 360
 361 static bool
 362 iris_compile_fs(struct iris_context *ice,
 363                 struct iris_uncompiled_shader *ish,
 364                 const struct brw_wm_prog_key *key,
 365                 struct brw_vue_map *vue_map)
 366 {
 367    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 368    const struct brw_compiler *compiler = screen->compiler;
 369    const struct gen_device_info *devinfo = &screen->devinfo;
 370    void *mem_ctx = ralloc_context(NULL);
 371    struct brw_wm_prog_data *fs_prog_data =
 372       rzalloc(mem_ctx, struct brw_wm_prog_data);
 373    struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
 374
 375    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 376
 377    nir_shader *nir = ish->base.ir.nir;
 378
 379    // XXX: alt mode
 380    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data,
 381                                        MAX2(key->nr_color_regions, 1));
 382
 383    iris_setup_uniforms(mem_ctx, nir, prog_data);
 384
 385    char *error_str = NULL;
 386    const unsigned *program =
 387       brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, fs_prog_data,
 388                      nir, NULL, -1, -1, -1, true, false, vue_map, &error_str);
 389    if (program == NULL) {
 390       dbg_printf("Failed to compile fragment shader: %s\n", error_str);
 391       ralloc_free(mem_ctx);
 392       return false;
 393    }
 394
 395    //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
 396
 397    iris_upload_and_bind_shader(ice, IRIS_CACHE_FS, key, program, prog_data);
 398
 399    ralloc_free(mem_ctx);
 400    return true;
 401 }
 402
 403 static void
 404 iris_update_compiled_fs(struct iris_context *ice)
 405 {
 406    struct brw_wm_prog_key key;
 407    ice->state.populate_fs_key(ice, &key);
 408
 409    if (iris_bind_cached_shader(ice, IRIS_CACHE_FS, &key))
 410       return;
 411
 412    UNUSED bool success =
 413       iris_compile_fs(ice, ice->shaders.uncompiled[MESA_SHADER_FRAGMENT], &key,
 414                       ice->shaders.last_vue_map);
 415 }
 416
 417 static void
 418 update_last_vue_map(struct iris_context *ice)
 419 {
 420    struct brw_stage_prog_data *prog_data;
 421
 422    if (ice->shaders.prog[MESA_SHADER_GEOMETRY])
 423       prog_data = ice->shaders.prog[MESA_SHADER_GEOMETRY]->prog_data;
 424    else if (ice->shaders.prog[MESA_SHADER_TESS_EVAL])
 425       prog_data = ice->shaders.prog[MESA_SHADER_TESS_EVAL]->prog_data;
 426    else
 427       prog_data = ice->shaders.prog[MESA_SHADER_VERTEX]->prog_data;
 428
 429    struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
 430    ice->shaders.last_vue_map = &vue_prog_data->vue_map;
 431 }
 432
 433 static struct brw_vue_prog_data *
 434 get_vue_prog_data(struct iris_context *ice, gl_shader_stage stage)
 435 {
 436    if (!ice->shaders.prog[stage])
 437       return NULL;
 438
 439    return (void *) ice->shaders.prog[stage]->prog_data;
 440 }
 441
 442 void
 443 iris_update_compiled_shaders(struct iris_context *ice)
 444 {
 445    struct brw_vue_prog_data *old_prog_datas[4];
 446    if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
 447       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++)
 448          old_prog_datas[i] = get_vue_prog_data(ice, i);
 449    }
 450
 451    iris_update_compiled_vs(ice);
 452    iris_update_compiled_tcs(ice);
 453    iris_update_compiled_tes(ice);
 454    iris_update_compiled_gs(ice);
 455    update_last_vue_map(ice);
 456    iris_update_compiled_fs(ice);
 457    // ...
 458
 459    if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
 460       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 461          struct brw_vue_prog_data *old = old_prog_datas[i];
 462          struct brw_vue_prog_data *new = get_vue_prog_data(ice, i);
 463          if (!!old != !!new ||
 464              (new && new->urb_entry_size != old->urb_entry_size)) {
 465             ice->state.dirty |= IRIS_DIRTY_URB;
 466             break;
 467          }
 468       }
 469    }
 470 }
 471
 472 void
 473 iris_init_program_functions(struct pipe_context *ctx)
 474 {
 475    ctx->create_vs_state  = iris_create_shader_state;
 476    ctx->create_tcs_state = iris_create_shader_state;
 477    ctx->create_tes_state = iris_create_shader_state;
 478    ctx->create_gs_state  = iris_create_shader_state;
 479    ctx->create_fs_state  = iris_create_shader_state;
 480
 481    ctx->delete_vs_state  = iris_delete_shader_state;
 482    ctx->delete_tcs_state = iris_delete_shader_state;
 483    ctx->delete_tes_state = iris_delete_shader_state;
 484    ctx->delete_gs_state  = iris_delete_shader_state;
 485    ctx->delete_fs_state  = iris_delete_shader_state;
 486
 487    ctx->bind_vs_state  = iris_bind_vs_state;
 488    ctx->bind_tcs_state = iris_bind_tcs_state;
 489    ctx->bind_tes_state = iris_bind_tes_state;
 490    ctx->bind_gs_state  = iris_bind_gs_state;
 491    ctx->bind_fs_state  = iris_bind_fs_state;
 492 }