src/gallium/drivers/iris/iris_program.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_program.c
  25  *
  26  * This file contains the driver interface for compiling shaders.
  27  *
  28  * See iris_program_cache.c for the in-memory program cache where the
  29  * compiled shaders are stored.
  30  */
  31
  32 #include <stdio.h>
  33 #include <errno.h>
  34 #include "pipe/p_defines.h"
  35 #include "pipe/p_state.h"
  36 #include "pipe/p_context.h"
  37 #include "pipe/p_screen.h"
  38 #include "util/u_atomic.h"
  39 #include "compiler/nir/nir.h"
  40 #include "compiler/nir/nir_builder.h"
  41 #include "intel/compiler/brw_compiler.h"
  42 #include "intel/compiler/brw_nir.h"
  43 #include "iris_context.h"
  44
  45 static unsigned
  46 get_new_program_id(struct iris_screen *screen)
  47 {
  48    return p_atomic_inc_return(&screen->program_id);
  49 }
  50
  51 /**
  52  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
  53  * It primarily contains the NIR for the shader.
  54  *
  55  * Each API-facing shader can be compiled into multiple shader variants,
  56  * based on non-orthogonal state dependencies, recorded in the shader key.
  57  *
  58  * See iris_compiled_shader, which represents a compiled shader variant.
  59  */
  60 struct iris_uncompiled_shader {
  61    nir_shader *nir;
  62
  63    struct pipe_stream_output_info stream_output;
  64
  65    unsigned program_id;
  66
  67    /** Bitfield of (1 << IRIS_NOS_*) flags. */
  68    unsigned nos;
  69 };
  70
  71 // XXX: need unify_interfaces() at link time...
  72
  73 /**
  74  * The pipe->create_[stage]_state() driver hooks.
  75  *
  76  * Performs basic NIR preprocessing, records any state dependencies, and
  77  * returns an iris_uncompiled_shader as the Gallium CSO.
  78  *
  79  * Actual shader compilation to assembly happens later, at first use.
  80  */
  81 static void *
  82 iris_create_shader_state(struct pipe_context *ctx,
  83                          const struct pipe_shader_state *state)
  84 {
  85    //struct iris_context *ice = (struct iris_context *)ctx;
  86    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
  87
  88    assert(state->type == PIPE_SHADER_IR_NIR);
  89
  90    nir_shader *nir = state->ir.nir;
  91
  92    struct iris_uncompiled_shader *ish =
  93       calloc(1, sizeof(struct iris_uncompiled_shader));
  94    if (!ish)
  95       return NULL;
  96
  97    nir = brw_preprocess_nir(screen->compiler, nir);
  98
  99    ish->program_id = get_new_program_id(screen);
 100    ish->nir = nir;
 101    memcpy(&ish->stream_output, &state->stream_output,
 102           sizeof(struct pipe_stream_output_info));
 103
 104    switch (nir->info.stage) {
 105    case MESA_SHADER_VERTEX:
 106       // XXX: NOS
 107       break;
 108    case MESA_SHADER_TESS_CTRL:
 109       // XXX: NOS
 110       break;
 111    case MESA_SHADER_TESS_EVAL:
 112       // XXX: NOS
 113       break;
 114    case MESA_SHADER_GEOMETRY:
 115       // XXX: NOS
 116       break;
 117    case MESA_SHADER_FRAGMENT:
 118       ish->nos |= IRIS_NOS_FRAMEBUFFER |
 119                   IRIS_NOS_DEPTH_STENCIL_ALPHA |
 120                   IRIS_NOS_RASTERIZER |
 121                   IRIS_NOS_BLEND;
 122
 123       /* The program key needs the VUE map if there are > 16 inputs */
 124       if (util_bitcount64(ish->nir->info.inputs_read &
 125                           BRW_FS_VARYING_INPUT_MASK) > 16) {
 126          ish->nos |= IRIS_NOS_LAST_VUE_MAP;
 127       }
 128       break;
 129    case MESA_SHADER_COMPUTE:
 130       // XXX: NOS
 131       break;
 132    default:
 133       break;
 134    }
 135
 136    // XXX: precompile!
 137
 138    return ish;
 139 }
 140
 141 /**
 142  * The pipe->delete_[stage]_state() driver hooks.
 143  *
 144  * Frees the iris_uncompiled_shader.
 145  */
 146 static void
 147 iris_delete_shader_state(struct pipe_context *ctx, void *state)
 148 {
 149    struct iris_uncompiled_shader *ish = state;
 150
 151    ralloc_free(ish->nir);
 152    free(ish);
 153 }
 154
 155 /**
 156  * The pipe->bind_[stage]_state() driver hook.
 157  *
 158  * Binds an uncompiled shader as the current one for a particular stage.
 159  * Updates dirty tracking to account for the shader's NOS.
 160  */
 161 static void
 162 bind_state(struct iris_context *ice,
 163            struct iris_uncompiled_shader *ish,
 164            gl_shader_stage stage)
 165 {
 166    uint64_t dirty_bit = IRIS_DIRTY_UNCOMPILED_VS << stage;
 167    const uint64_t nos = ish ? ish->nos : 0;
 168
 169    ice->shaders.uncompiled[stage] = ish;
 170    ice->state.dirty |= dirty_bit;
 171
 172    /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
 173     * (or that they no longer need to do so).
 174     */
 175    for (int i = 0; i < IRIS_NOS_COUNT; i++) {
 176       if (nos & (1 << i))
 177          ice->state.dirty_for_nos[i] |= dirty_bit;
 178       else
 179          ice->state.dirty_for_nos[i] &= ~dirty_bit;
 180    }
 181 }
 182
 183 static void
 184 iris_bind_vs_state(struct pipe_context *ctx, void *state)
 185 {
 186    bind_state((void *) ctx, state, MESA_SHADER_VERTEX);
 187 }
 188
 189 static void
 190 iris_bind_tcs_state(struct pipe_context *ctx, void *state)
 191 {
 192    bind_state((void *) ctx, state, MESA_SHADER_TESS_CTRL);
 193 }
 194
 195 static void
 196 iris_bind_tes_state(struct pipe_context *ctx, void *state)
 197 {
 198    struct iris_context *ice = (struct iris_context *)ctx;
 199
 200    /* Enabling/disabling optional stages requires a URB reconfiguration. */
 201    if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
 202       ice->state.dirty |= IRIS_DIRTY_URB;
 203
 204    bind_state((void *) ctx, state, MESA_SHADER_TESS_EVAL);
 205 }
 206
 207 static void
 208 iris_bind_gs_state(struct pipe_context *ctx, void *state)
 209 {
 210    struct iris_context *ice = (struct iris_context *)ctx;
 211
 212    /* Enabling/disabling optional stages requires a URB reconfiguration. */
 213    if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
 214       ice->state.dirty |= IRIS_DIRTY_URB;
 215
 216    bind_state((void *) ctx, state, MESA_SHADER_GEOMETRY);
 217 }
 218
 219 static void
 220 iris_bind_fs_state(struct pipe_context *ctx, void *state)
 221 {
 222    bind_state((void *) ctx, state, MESA_SHADER_FRAGMENT);
 223 }
 224
 225 /**
 226  * Sets up the starting offsets for the groups of binding table entries
 227  * common to all pipeline stages.
 228  *
 229  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 230  * unused but also make sure that addition of small offsets to them will
 231  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 232  */
 233 static uint32_t
 234 assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
 235                                     const struct nir_shader *nir,
 236                                     struct brw_stage_prog_data *prog_data,
 237                                     uint32_t next_binding_table_offset)
 238 {
 239    const struct shader_info *info = &nir->info;
 240
 241    if (info->num_textures) {
 242       prog_data->binding_table.texture_start = next_binding_table_offset;
 243       prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 244       next_binding_table_offset += info->num_textures;
 245    } else {
 246       prog_data->binding_table.texture_start = 0xd0d0d0d0;
 247       prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
 248    }
 249
 250    int num_ubos = info->num_ubos + (nir->num_uniforms > 0 ? 1 : 0);
 251
 252    if (num_ubos) {
 253       //assert(info->num_ubos <= BRW_MAX_UBO);
 254       prog_data->binding_table.ubo_start = next_binding_table_offset;
 255       next_binding_table_offset += num_ubos;
 256    } else {
 257       prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 258    }
 259
 260    if (info->num_ssbos || info->num_abos) {
 261       //assert(info->num_abos <= BRW_MAX_ABO);
 262       //assert(info->num_ssbos <= BRW_MAX_SSBO);
 263       prog_data->binding_table.ssbo_start = next_binding_table_offset;
 264       next_binding_table_offset += info->num_abos + info->num_ssbos;
 265    } else {
 266       prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
 267    }
 268
 269    prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 270
 271    if (info->num_images) {
 272       prog_data->binding_table.image_start = next_binding_table_offset;
 273       next_binding_table_offset += info->num_images;
 274    } else {
 275       prog_data->binding_table.image_start = 0xd0d0d0d0;
 276    }
 277
 278    /* This may or may not be used depending on how the compile goes. */
 279    prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 280    next_binding_table_offset++;
 281
 282    /* Plane 0 is just the regular texture section */
 283    prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
 284
 285    prog_data->binding_table.plane_start[1] = next_binding_table_offset;
 286    next_binding_table_offset += info->num_textures;
 287
 288    prog_data->binding_table.plane_start[2] = next_binding_table_offset;
 289    next_binding_table_offset += info->num_textures;
 290
 291    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 292
 293    //assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 294    return next_binding_table_offset;
 295 }
 296
 297 /**
 298  * Associate NIR uniform variables with the prog_data->param[] mechanism
 299  * used by the backend.  Also, decide which UBOs we'd like to push in an
 300  * ideal situation (though the backend can reduce this).
 301  */
 302 static void
 303 iris_setup_uniforms(const struct brw_compiler *compiler,
 304                     void *mem_ctx,
 305                     nir_shader *nir,
 306                     struct brw_stage_prog_data *prog_data)
 307 {
 308    prog_data->nr_params = nir->num_uniforms;
 309    prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
 310
 311    nir_foreach_variable(var, &nir->uniforms) {
 312       const unsigned components = glsl_get_components(var->type);
 313
 314       for (unsigned i = 0; i < components; i++) {
 315          prog_data->param[var->data.driver_location] =
 316             var->data.driver_location;
 317       }
 318    }
 319
 320    // XXX: vs clip planes?
 321    brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
 322 }
 323
 324 /**
 325  * If we still have regular uniforms as push constants after the backend
 326  * compilation, set up a UBO range for them.  This will be used to fill
 327  * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
 328  */
 329 static void
 330 iris_setup_push_uniform_range(const struct brw_compiler *compiler,
 331                               struct brw_stage_prog_data *prog_data)
 332 {
 333    if (prog_data->nr_params) {
 334       for (int i = 3; i > 0; i--)
 335          prog_data->ubo_ranges[i] = prog_data->ubo_ranges[i - 1];
 336
 337       prog_data->ubo_ranges[0] = (struct brw_ubo_range) {
 338          .block = 0,
 339          .start = 0,
 340          .length = DIV_ROUND_UP(prog_data->nr_params, 8),
 341       };
 342    }
 343 }
 344
 345 /**
 346  * Compile a vertex shader, and upload the assembly.
 347  */
 348 static bool
 349 iris_compile_vs(struct iris_context *ice,
 350                 struct iris_uncompiled_shader *ish,
 351                 const struct brw_vs_prog_key *key)
 352 {
 353    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 354    const struct brw_compiler *compiler = screen->compiler;
 355    const struct gen_device_info *devinfo = &screen->devinfo;
 356    void *mem_ctx = ralloc_context(NULL);
 357    struct brw_vs_prog_data *vs_prog_data =
 358       rzalloc(mem_ctx, struct brw_vs_prog_data);
 359    struct brw_vue_prog_data *vue_prog_data = &vs_prog_data->base;
 360    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 361
 362    nir_shader *nir = ish->nir;
 363
 364    // XXX: alt mode
 365    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 366
 367    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 368
 369    brw_compute_vue_map(devinfo,
 370                        &vue_prog_data->vue_map, nir->info.outputs_written,
 371                        nir->info.separate_shader);
 372
 373    char *error_str = NULL;
 374    const unsigned *program =
 375       brw_compile_vs(compiler, &ice->dbg, mem_ctx, key, vs_prog_data,
 376                      nir, -1, &error_str);
 377    if (program == NULL) {
 378       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 379       ralloc_free(mem_ctx);
 380       return false;
 381    }
 382
 383    iris_setup_push_uniform_range(compiler, prog_data);
 384
 385    uint32_t *so_decls =
 386       ice->vtbl.create_so_decl_list(&ish->stream_output,
 387                                     &vue_prog_data->vue_map);
 388
 389    iris_upload_and_bind_shader(ice, IRIS_CACHE_VS, key, program, prog_data,
 390                                so_decls);
 391
 392    ralloc_free(mem_ctx);
 393    return true;
 394 }
 395
 396 /**
 397  * Update the current vertex shader variant.
 398  *
 399  * Fill out the key, look in the cache, compile and bind if needed.
 400  */
 401 static void
 402 iris_update_compiled_vs(struct iris_context *ice)
 403 {
 404    struct iris_uncompiled_shader *ish =
 405       ice->shaders.uncompiled[MESA_SHADER_VERTEX];
 406
 407    struct brw_vs_prog_key key = { .program_string_id = ish->program_id };
 408    ice->vtbl.populate_vs_key(ice, &key);
 409
 410    if (iris_bind_cached_shader(ice, IRIS_CACHE_VS, &key))
 411       return;
 412
 413    UNUSED bool success = iris_compile_vs(ice, ish, &key);
 414 }
 415
 416 /**
 417  * Get the shader_info for a given stage, or NULL if the stage is disabled.
 418  */
 419 const struct shader_info *
 420 iris_get_shader_info(const struct iris_context *ice, gl_shader_stage stage)
 421 {
 422    const struct iris_uncompiled_shader *ish = ice->shaders.uncompiled[stage];
 423
 424    if (!ish)
 425       return NULL;
 426
 427    const nir_shader *nir = ish->nir;
 428    return &nir->info;
 429 }
 430
 431 /**
 432  * Get the union of TCS output and TES input slots.
 433  *
 434  * TCS and TES need to agree on a common URB entry layout.  In particular,
 435  * the data for all patch vertices is stored in a single URB entry (unlike
 436  * GS which has one entry per input vertex).  This means that per-vertex
 437  * array indexing needs a stride.
 438  *
 439  * SSO requires locations to match, but doesn't require the number of
 440  * outputs/inputs to match (in fact, the TCS often has extra outputs).
 441  * So, we need to take the extra step of unifying these on the fly.
 442  */
 443 static void
 444 get_unified_tess_slots(const struct iris_context *ice,
 445                        uint64_t *per_vertex_slots,
 446                        uint32_t *per_patch_slots)
 447 {
 448    const struct shader_info *tcs =
 449       iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL);
 450    const struct shader_info *tes =
 451       iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
 452
 453    *per_vertex_slots = tes->inputs_read;
 454    *per_patch_slots = tes->patch_inputs_read;
 455
 456    if (tcs) {
 457       *per_vertex_slots |= tcs->inputs_read;
 458       *per_patch_slots |= tcs->patch_inputs_read;
 459    }
 460 }
 461
 462 /**
 463  * Compile a tessellation control shader, and upload the assembly.
 464  */
 465 static bool
 466 iris_compile_tcs(struct iris_context *ice,
 467                  struct iris_uncompiled_shader *ish,
 468                  const struct brw_tcs_prog_key *key)
 469 {
 470    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 471    const struct brw_compiler *compiler = screen->compiler;
 472    const struct gen_device_info *devinfo = &screen->devinfo;
 473    void *mem_ctx = ralloc_context(NULL);
 474    struct brw_tcs_prog_data *tcs_prog_data =
 475       rzalloc(mem_ctx, struct brw_tcs_prog_data);
 476    struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
 477    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 478
 479    nir_shader *nir = ish->nir;
 480
 481    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 482
 483    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 484
 485    char *error_str = NULL;
 486    const unsigned *program =
 487       brw_compile_tcs(compiler, &ice->dbg, mem_ctx, key, tcs_prog_data, nir,
 488                       -1, &error_str);
 489    if (program == NULL) {
 490       dbg_printf("Failed to compile evaluation shader: %s\n", error_str);
 491       ralloc_free(mem_ctx);
 492       return false;
 493    }
 494
 495    iris_setup_push_uniform_range(compiler, prog_data);
 496
 497    iris_upload_and_bind_shader(ice, IRIS_CACHE_TCS, key, program, prog_data,
 498                                NULL);
 499
 500    ralloc_free(mem_ctx);
 501    return true;
 502 }
 503
 504 /**
 505  * Update the current tessellation control shader variant.
 506  *
 507  * Fill out the key, look in the cache, compile and bind if needed.
 508  */
 509 static void
 510 iris_update_compiled_tcs(struct iris_context *ice)
 511 {
 512    struct iris_uncompiled_shader *tcs =
 513       ice->shaders.uncompiled[MESA_SHADER_TESS_CTRL];
 514    struct iris_uncompiled_shader *tes =
 515       ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
 516
 517    assert(!(tes && !tcs));
 518
 519    if (!tcs) {
 520       iris_unbind_shader(ice, IRIS_CACHE_TCS);
 521       return;
 522    }
 523
 524    const struct shader_info *tes_info =
 525       iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
 526    struct brw_tcs_prog_key key = {
 527       .program_string_id = tcs->program_id,
 528       .tes_primitive_mode = tes_info->tess.primitive_mode,
 529    };
 530    get_unified_tess_slots(ice, &key.outputs_written,
 531                           &key.patch_outputs_written);
 532    ice->vtbl.populate_tcs_key(ice, &key);
 533
 534    if (iris_bind_cached_shader(ice, IRIS_CACHE_TCS, &key))
 535       return;
 536
 537    UNUSED bool success = iris_compile_tcs(ice, tcs, &key);
 538 }
 539
 540 /**
 541  * Compile a tessellation evaluation shader, and upload the assembly.
 542  */
 543 static bool
 544 iris_compile_tes(struct iris_context *ice,
 545                  struct iris_uncompiled_shader *ish,
 546                  const struct brw_tes_prog_key *key)
 547 {
 548    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 549    const struct brw_compiler *compiler = screen->compiler;
 550    const struct gen_device_info *devinfo = &screen->devinfo;
 551    void *mem_ctx = ralloc_context(NULL);
 552    struct brw_tes_prog_data *tes_prog_data =
 553       rzalloc(mem_ctx, struct brw_tes_prog_data);
 554    struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
 555    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 556
 557    nir_shader *nir = ish->nir;
 558
 559    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 560
 561    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 562
 563    struct brw_vue_map input_vue_map;
 564    brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
 565                             key->patch_inputs_read);
 566
 567    char *error_str = NULL;
 568    const unsigned *program =
 569       brw_compile_tes(compiler, &ice->dbg, mem_ctx, key, &input_vue_map,
 570                       tes_prog_data, nir, NULL, -1, &error_str);
 571    if (program == NULL) {
 572       dbg_printf("Failed to compile evaluation shader: %s\n", error_str);
 573       ralloc_free(mem_ctx);
 574       return false;
 575    }
 576
 577    iris_setup_push_uniform_range(compiler, prog_data);
 578
 579    uint32_t *so_decls =
 580       ice->vtbl.create_so_decl_list(&ish->stream_output,
 581                                     &vue_prog_data->vue_map);
 582
 583    iris_upload_and_bind_shader(ice, IRIS_CACHE_TES, key, program, prog_data,
 584                                so_decls);
 585
 586    ralloc_free(mem_ctx);
 587    return true;
 588 }
 589
 590 /**
 591  * Update the current tessellation evaluation shader variant.
 592  *
 593  * Fill out the key, look in the cache, compile and bind if needed.
 594  */
 595 static void
 596 iris_update_compiled_tes(struct iris_context *ice)
 597 {
 598    struct iris_uncompiled_shader *ish =
 599       ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
 600
 601    if (!ish) {
 602       iris_unbind_shader(ice, IRIS_CACHE_TES);
 603       return;
 604    }
 605
 606    struct brw_tes_prog_key key = { .program_string_id = ish->program_id };
 607    get_unified_tess_slots(ice, &key.inputs_read, &key.patch_inputs_read);
 608    ice->vtbl.populate_tes_key(ice, &key);
 609
 610    if (iris_bind_cached_shader(ice, IRIS_CACHE_TES, &key))
 611       return;
 612
 613    UNUSED bool success = iris_compile_tes(ice, ish, &key);
 614 }
 615
 616 /**
 617  * Compile a geometry shader, and upload the assembly.
 618  */
 619 static bool
 620 iris_compile_gs(struct iris_context *ice,
 621                 struct iris_uncompiled_shader *ish,
 622                 const struct brw_gs_prog_key *key)
 623 {
 624    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 625    const struct brw_compiler *compiler = screen->compiler;
 626    const struct gen_device_info *devinfo = &screen->devinfo;
 627    void *mem_ctx = ralloc_context(NULL);
 628    struct brw_gs_prog_data *gs_prog_data =
 629       rzalloc(mem_ctx, struct brw_gs_prog_data);
 630    struct brw_vue_prog_data *vue_prog_data = &gs_prog_data->base;
 631    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 632
 633    nir_shader *nir = ish->nir;
 634
 635    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 636
 637    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 638
 639    brw_compute_vue_map(devinfo,
 640                        &vue_prog_data->vue_map, nir->info.outputs_written,
 641                        nir->info.separate_shader);
 642
 643    char *error_str = NULL;
 644    const unsigned *program =
 645       brw_compile_gs(compiler, &ice->dbg, mem_ctx, key, gs_prog_data, nir,
 646                      NULL, -1, &error_str);
 647    if (program == NULL) {
 648       dbg_printf("Failed to compile geometry shader: %s\n", error_str);
 649       ralloc_free(mem_ctx);
 650       return false;
 651    }
 652
 653    iris_setup_push_uniform_range(compiler, prog_data);
 654
 655    uint32_t *so_decls =
 656       ice->vtbl.create_so_decl_list(&ish->stream_output,
 657                                     &vue_prog_data->vue_map);
 658
 659    iris_upload_and_bind_shader(ice, IRIS_CACHE_GS, key, program, prog_data,
 660                                so_decls);
 661
 662    ralloc_free(mem_ctx);
 663    return true;
 664 }
 665
 666 /**
 667  * Update the current geometry shader variant.
 668  *
 669  * Fill out the key, look in the cache, compile and bind if needed.
 670  */
 671 static void
 672 iris_update_compiled_gs(struct iris_context *ice)
 673 {
 674    struct iris_uncompiled_shader *ish =
 675       ice->shaders.uncompiled[MESA_SHADER_GEOMETRY];
 676
 677    if (!ish) {
 678       iris_unbind_shader(ice, IRIS_CACHE_GS);
 679       return;
 680    }
 681
 682    struct brw_gs_prog_key key = { .program_string_id = ish->program_id };
 683    ice->vtbl.populate_gs_key(ice, &key);
 684
 685    if (iris_bind_cached_shader(ice, IRIS_CACHE_GS, &key))
 686       return;
 687
 688    UNUSED bool success = iris_compile_gs(ice, ish, &key);
 689 }
 690
 691 /**
 692  * Compile a fragment (pixel) shader, and upload the assembly.
 693  */
 694 static bool
 695 iris_compile_fs(struct iris_context *ice,
 696                 struct iris_uncompiled_shader *ish,
 697                 const struct brw_wm_prog_key *key,
 698                 struct brw_vue_map *vue_map)
 699 {
 700    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 701    const struct brw_compiler *compiler = screen->compiler;
 702    const struct gen_device_info *devinfo = &screen->devinfo;
 703    void *mem_ctx = ralloc_context(NULL);
 704    struct brw_wm_prog_data *fs_prog_data =
 705       rzalloc(mem_ctx, struct brw_wm_prog_data);
 706    struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
 707
 708    nir_shader *nir = ish->nir;
 709
 710    // XXX: alt mode
 711    assign_common_binding_table_offsets(devinfo, nir, prog_data,
 712                                        MAX2(key->nr_color_regions, 1));
 713
 714    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 715
 716    char *error_str = NULL;
 717    const unsigned *program =
 718       brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, fs_prog_data,
 719                      nir, NULL, -1, -1, -1, true, false, vue_map, &error_str);
 720    if (program == NULL) {
 721       dbg_printf("Failed to compile fragment shader: %s\n", error_str);
 722       ralloc_free(mem_ctx);
 723       return false;
 724    }
 725
 726    //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
 727
 728    iris_setup_push_uniform_range(compiler, prog_data);
 729
 730    iris_upload_and_bind_shader(ice, IRIS_CACHE_FS, key, program, prog_data,
 731                                NULL);
 732
 733    ralloc_free(mem_ctx);
 734    return true;
 735 }
 736
 737 /**
 738  * Update the current fragment shader variant.
 739  *
 740  * Fill out the key, look in the cache, compile and bind if needed.
 741  */
 742 static void
 743 iris_update_compiled_fs(struct iris_context *ice)
 744 {
 745    struct iris_uncompiled_shader *ish =
 746       ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
 747    struct brw_wm_prog_key key = { .program_string_id = ish->program_id };
 748    ice->vtbl.populate_fs_key(ice, &key);
 749
 750    if (ish->nos & IRIS_NOS_LAST_VUE_MAP)
 751       key.input_slots_valid = ice->shaders.last_vue_map->slots_valid;
 752
 753    if (iris_bind_cached_shader(ice, IRIS_CACHE_FS, &key))
 754       return;
 755
 756    UNUSED bool success =
 757       iris_compile_fs(ice, ish, &key, ice->shaders.last_vue_map);
 758 }
 759
 760 /**
 761  * Get the compiled shader for the last enabled geometry stage.
 762  *
 763  * This stage is the one which will feed stream output and the rasterizer.
 764  */
 765 static struct iris_compiled_shader *
 766 last_vue_shader(struct iris_context *ice)
 767 {
 768    if (ice->shaders.prog[MESA_SHADER_GEOMETRY])
 769       return ice->shaders.prog[MESA_SHADER_GEOMETRY];
 770
 771    if (ice->shaders.prog[MESA_SHADER_TESS_EVAL])
 772       return ice->shaders.prog[MESA_SHADER_TESS_EVAL];
 773
 774    return ice->shaders.prog[MESA_SHADER_VERTEX];
 775 }
 776
 777 /**
 778  * Update the last enabled stage's VUE map.
 779  *
 780  * When the shader feeding the rasterizer's output interface changes, we
 781  * need to re-emit various packets.
 782  */
 783 static void
 784 update_last_vue_map(struct iris_context *ice,
 785                     struct brw_stage_prog_data *prog_data)
 786 {
 787    struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
 788    struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
 789    struct brw_vue_map *old_map = ice->shaders.last_vue_map;
 790    const uint64_t changed_slots =
 791       (old_map ? old_map->slots_valid : 0ull) ^ vue_map->slots_valid;
 792
 793    if (changed_slots & VARYING_BIT_VIEWPORT) {
 794       // XXX: could use ctx->Const.MaxViewports for old API efficiency
 795       ice->state.num_viewports =
 796          (vue_map->slots_valid & VARYING_BIT_VIEWPORT) ? IRIS_MAX_VIEWPORTS : 1;
 797       ice->state.dirty |= IRIS_DIRTY_CLIP |
 798                           IRIS_DIRTY_SF_CL_VIEWPORT |
 799                           IRIS_DIRTY_SCISSOR_RECT |
 800                           IRIS_DIRTY_UNCOMPILED_FS |
 801                           ice->state.dirty_for_nos[IRIS_NOS_LAST_VUE_MAP];
 802       // XXX: CC_VIEWPORT?
 803    }
 804
 805    if (changed_slots || (old_map && old_map->separate != vue_map->separate)) {
 806       ice->state.dirty |= IRIS_DIRTY_SBE;
 807    }
 808
 809    ice->shaders.last_vue_map = &vue_prog_data->vue_map;
 810 }
 811
 812 /**
 813  * Get the prog_data for a given stage, or NULL if the stage is disabled.
 814  */
 815 static struct brw_vue_prog_data *
 816 get_vue_prog_data(struct iris_context *ice, gl_shader_stage stage)
 817 {
 818    if (!ice->shaders.prog[stage])
 819       return NULL;
 820
 821    return (void *) ice->shaders.prog[stage]->prog_data;
 822 }
 823
 824 /**
 825  * Update the current shader variants for the given state.
 826  *
 827  * This should be called on every draw call to ensure that the correct
 828  * shaders are bound.  It will also flag any dirty state triggered by
 829  * swapping out those shaders.
 830  */
 831 void
 832 iris_update_compiled_shaders(struct iris_context *ice)
 833 {
 834    const uint64_t dirty = ice->state.dirty;
 835
 836    struct brw_vue_prog_data *old_prog_datas[4];
 837    if (!(dirty & IRIS_DIRTY_URB)) {
 838       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++)
 839          old_prog_datas[i] = get_vue_prog_data(ice, i);
 840    }
 841
 842    if (dirty & IRIS_DIRTY_UNCOMPILED_VS)
 843       iris_update_compiled_vs(ice);
 844    if (dirty & IRIS_DIRTY_UNCOMPILED_TCS)
 845       iris_update_compiled_tcs(ice);
 846    if (dirty & IRIS_DIRTY_UNCOMPILED_TES)
 847       iris_update_compiled_tes(ice);
 848    if (dirty & IRIS_DIRTY_UNCOMPILED_GS)
 849       iris_update_compiled_gs(ice);
 850
 851    struct iris_compiled_shader *shader = last_vue_shader(ice);
 852    update_last_vue_map(ice, shader->prog_data);
 853    if (ice->state.streamout != shader->streamout) {
 854       ice->state.streamout = shader->streamout;
 855       ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST | IRIS_DIRTY_STREAMOUT;
 856    }
 857
 858    if (dirty & IRIS_DIRTY_UNCOMPILED_FS)
 859       iris_update_compiled_fs(ice);
 860    // ...
 861
 862    /* Changing shader interfaces may require a URB configuration. */
 863    if (!(dirty & IRIS_DIRTY_URB)) {
 864       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 865          struct brw_vue_prog_data *old = old_prog_datas[i];
 866          struct brw_vue_prog_data *new = get_vue_prog_data(ice, i);
 867          if (!!old != !!new ||
 868              (new && new->urb_entry_size != old->urb_entry_size)) {
 869             ice->state.dirty |= IRIS_DIRTY_URB;
 870             break;
 871          }
 872       }
 873    }
 874 }
 875
 876 void
 877 iris_init_program_functions(struct pipe_context *ctx)
 878 {
 879    ctx->create_vs_state  = iris_create_shader_state;
 880    ctx->create_tcs_state = iris_create_shader_state;
 881    ctx->create_tes_state = iris_create_shader_state;
 882    ctx->create_gs_state  = iris_create_shader_state;
 883    ctx->create_fs_state  = iris_create_shader_state;
 884
 885    ctx->delete_vs_state  = iris_delete_shader_state;
 886    ctx->delete_tcs_state = iris_delete_shader_state;
 887    ctx->delete_tes_state = iris_delete_shader_state;
 888    ctx->delete_gs_state  = iris_delete_shader_state;
 889    ctx->delete_fs_state  = iris_delete_shader_state;
 890
 891    ctx->bind_vs_state  = iris_bind_vs_state;
 892    ctx->bind_tcs_state = iris_bind_tcs_state;
 893    ctx->bind_tes_state = iris_bind_tes_state;
 894    ctx->bind_gs_state  = iris_bind_gs_state;
 895    ctx->bind_fs_state  = iris_bind_fs_state;
 896 }