2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
44 #include "nir/tgsi_to_nir.h"
46 #define KEY_INIT_NO_ID(gen) \
47 .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
48 .tex.compressed_multisample_layout_mask = ~0, \
49 .tex.msaa_16 = (gen >= 9 ? ~0 : 0)
50 #define KEY_INIT(gen) .program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
53 get_new_program_id(struct iris_screen
*screen
)
55 return p_atomic_inc_return(&screen
->program_id
);
59 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
60 * It primarily contains the NIR for the shader.
62 * Each API-facing shader can be compiled into multiple shader variants,
63 * based on non-orthogonal state dependencies, recorded in the shader key.
65 * See iris_compiled_shader, which represents a compiled shader variant.
67 struct iris_uncompiled_shader
{
70 struct pipe_stream_output_info stream_output
;
74 /** Bitfield of (1 << IRIS_NOS_*) flags. */
77 /** Have any shader variants been compiled yet? */
82 get_aoa_deref_offset(nir_builder
*b
,
83 nir_deref_instr
*deref
,
86 unsigned array_size
= elem_size
;
87 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
89 while (deref
->deref_type
!= nir_deref_type_var
) {
90 assert(deref
->deref_type
== nir_deref_type_array
);
92 /* This level's element size is the previous level's array size */
93 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
94 assert(deref
->arr
.index
.ssa
);
95 offset
= nir_iadd(b
, offset
,
96 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
98 deref
= nir_deref_instr_parent(deref
);
99 assert(glsl_type_is_array(deref
->type
));
100 array_size
*= glsl_get_length(deref
->type
);
103 /* Accessing an invalid surface index with the dataport can result in a
104 * hang. According to the spec "if the index used to select an individual
105 * element is negative or greater than or equal to the size of the array,
106 * the results of the operation are undefined but may not lead to
107 * termination" -- which is one of the possible outcomes of the hang.
108 * Clamp the index to prevent access outside of the array bounds.
110 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
114 iris_lower_storage_image_derefs(nir_shader
*nir
)
116 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
119 nir_builder_init(&b
, impl
);
121 nir_foreach_block(block
, impl
) {
122 nir_foreach_instr_safe(instr
, block
) {
123 if (instr
->type
!= nir_instr_type_intrinsic
)
126 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
127 switch (intrin
->intrinsic
) {
128 case nir_intrinsic_image_deref_load
:
129 case nir_intrinsic_image_deref_store
:
130 case nir_intrinsic_image_deref_atomic_add
:
131 case nir_intrinsic_image_deref_atomic_min
:
132 case nir_intrinsic_image_deref_atomic_max
:
133 case nir_intrinsic_image_deref_atomic_and
:
134 case nir_intrinsic_image_deref_atomic_or
:
135 case nir_intrinsic_image_deref_atomic_xor
:
136 case nir_intrinsic_image_deref_atomic_exchange
:
137 case nir_intrinsic_image_deref_atomic_comp_swap
:
138 case nir_intrinsic_image_deref_size
:
139 case nir_intrinsic_image_deref_samples
:
140 case nir_intrinsic_image_deref_load_raw_intel
:
141 case nir_intrinsic_image_deref_store_raw_intel
: {
142 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
143 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
145 b
.cursor
= nir_before_instr(&intrin
->instr
);
147 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
148 get_aoa_deref_offset(&b
, deref
, 1));
149 nir_rewrite_image_intrinsic(intrin
, index
, false);
160 // XXX: need unify_interfaces() at link time...
163 * Fix an uncompiled shader's stream output info.
165 * Core Gallium stores output->register_index as a "slot" number, where
166 * slots are assigned consecutively to all outputs in info->outputs_written.
167 * This naive packing of outputs doesn't work for us - we too have slots,
168 * but the layout is defined by the VUE map, which we won't have until we
169 * compile a specific shader variant. So, we remap these and simply store
170 * VARYING_SLOT_* in our copy's output->register_index fields.
172 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
173 * components of our VUE header. See brw_vue_map.c for the layout.
176 update_so_info(struct pipe_stream_output_info
*so_info
,
177 uint64_t outputs_written
)
179 uint8_t reverse_map
[64] = {};
181 while (outputs_written
) {
182 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
185 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
186 struct pipe_stream_output
*output
= &so_info
->output
[i
];
188 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
189 output
->register_index
= reverse_map
[output
->register_index
];
191 /* The VUE header contains three scalar fields packed together:
192 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
193 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
194 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
196 switch (output
->register_index
) {
197 case VARYING_SLOT_LAYER
:
198 assert(output
->num_components
== 1);
199 output
->register_index
= VARYING_SLOT_PSIZ
;
200 output
->start_component
= 1;
202 case VARYING_SLOT_VIEWPORT
:
203 assert(output
->num_components
== 1);
204 output
->register_index
= VARYING_SLOT_PSIZ
;
205 output
->start_component
= 2;
207 case VARYING_SLOT_PSIZ
:
208 assert(output
->num_components
== 1);
209 output
->start_component
= 3;
213 //info->outputs_written |= 1ull << output->register_index;
218 * Sets up the starting offsets for the groups of binding table entries
219 * common to all pipeline stages.
221 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
222 * unused but also make sure that addition of small offsets to them will
223 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
226 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
227 const struct nir_shader
*nir
,
228 struct brw_stage_prog_data
*prog_data
,
229 uint32_t next_binding_table_offset
,
230 unsigned num_system_values
,
233 const struct shader_info
*info
= &nir
->info
;
235 unsigned num_textures
= util_last_bit(info
->textures_used
);
238 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
239 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
240 next_binding_table_offset
+= num_textures
;
242 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
243 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
246 if (info
->num_images
) {
247 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
248 next_binding_table_offset
+= info
->num_images
;
250 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
254 //assert(info->num_ubos <= BRW_MAX_UBO);
255 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
256 next_binding_table_offset
+= num_cbufs
;
258 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
261 if (info
->num_ssbos
|| info
->num_abos
) {
262 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
263 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
264 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
266 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
269 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
271 /* Plane 0 is just the regular texture section */
272 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
274 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
275 next_binding_table_offset
+= num_textures
;
277 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
278 next_binding_table_offset
+= num_textures
;
280 /* Set the binding table size */
281 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
283 return next_binding_table_offset
;
287 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
288 unsigned offset
, unsigned n
)
290 assert(offset
% sizeof(uint32_t) == 0);
292 for (unsigned i
= 0; i
< n
; ++i
)
293 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
295 for (unsigned i
= n
; i
< 4; ++i
)
296 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
300 * Associate NIR uniform variables with the prog_data->param[] mechanism
301 * used by the backend. Also, decide which UBOs we'd like to push in an
302 * ideal situation (though the backend can reduce this).
305 iris_setup_uniforms(const struct brw_compiler
*compiler
,
308 struct brw_stage_prog_data
*prog_data
,
309 enum brw_param_builtin
**out_system_values
,
310 unsigned *out_num_system_values
,
311 unsigned *out_num_cbufs
)
313 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
315 /* The intel compiler assumes that num_uniforms is in bytes. For
316 * scalar that means 4 bytes per uniform slot.
318 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
320 nir
->num_uniforms
*= 4;
322 const unsigned IRIS_MAX_SYSTEM_VALUES
=
323 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
324 enum brw_param_builtin
*system_values
=
325 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
326 unsigned num_system_values
= 0;
328 unsigned patch_vert_idx
= -1;
329 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
330 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
331 memset(ucp_idx
, -1, sizeof(ucp_idx
));
332 memset(img_idx
, -1, sizeof(img_idx
));
334 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
337 nir_builder_init(&b
, impl
);
339 b
.cursor
= nir_before_block(nir_start_block(impl
));
340 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
342 /* Turn system value intrinsics into uniforms */
343 nir_foreach_block(block
, impl
) {
344 nir_foreach_instr_safe(instr
, block
) {
345 if (instr
->type
!= nir_instr_type_intrinsic
)
348 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
351 switch (intrin
->intrinsic
) {
352 case nir_intrinsic_load_user_clip_plane
: {
353 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
355 if (ucp_idx
[ucp
] == -1) {
356 ucp_idx
[ucp
] = num_system_values
;
357 num_system_values
+= 4;
360 for (int i
= 0; i
< 4; i
++) {
361 system_values
[ucp_idx
[ucp
] + i
] =
362 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
365 b
.cursor
= nir_before_instr(instr
);
366 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
369 case nir_intrinsic_load_patch_vertices_in
:
370 if (patch_vert_idx
== -1)
371 patch_vert_idx
= num_system_values
++;
373 system_values
[patch_vert_idx
] =
374 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
376 b
.cursor
= nir_before_instr(instr
);
377 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
379 case nir_intrinsic_image_deref_load_param_intel
: {
380 assert(devinfo
->gen
< 9);
381 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
382 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
384 /* XXX: var->data.binding is not set properly. We need to run
385 * some form of gl_nir_lower_samplers_as_deref() to get it.
386 * This breaks tests which use more than one image.
388 if (img_idx
[var
->data
.binding
] == -1) {
389 /* GL only allows arrays of arrays of images. */
390 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
391 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
393 for (int i
= 0; i
< num_images
; i
++) {
394 const unsigned img
= var
->data
.binding
+ i
;
396 img_idx
[img
] = num_system_values
;
397 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
399 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
401 setup_vec4_image_sysval(
402 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
403 offsetof(struct brw_image_param
, offset
), 2);
404 setup_vec4_image_sysval(
405 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
406 offsetof(struct brw_image_param
, size
), 3);
407 setup_vec4_image_sysval(
408 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
409 offsetof(struct brw_image_param
, stride
), 4);
410 setup_vec4_image_sysval(
411 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
412 offsetof(struct brw_image_param
, tiling
), 3);
413 setup_vec4_image_sysval(
414 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
415 offsetof(struct brw_image_param
, swizzling
), 2);
419 b
.cursor
= nir_before_instr(instr
);
420 offset
= nir_iadd(&b
,
421 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
422 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
423 nir_intrinsic_base(intrin
) * 16));
430 unsigned comps
= nir_intrinsic_dest_components(intrin
);
432 nir_intrinsic_instr
*load
=
433 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
434 load
->num_components
= comps
;
435 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
436 load
->src
[1] = nir_src_for_ssa(offset
);
437 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
438 nir_builder_instr_insert(&b
, &load
->instr
);
439 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
440 nir_src_for_ssa(&load
->dest
.ssa
));
441 nir_instr_remove(instr
);
445 nir_validate_shader(nir
, "before remapping");
447 /* Place the new params at the front of constant buffer 0. */
448 if (num_system_values
> 0) {
449 nir
->num_uniforms
+= num_system_values
* sizeof(uint32_t);
451 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
454 nir_foreach_block(block
, impl
) {
455 nir_foreach_instr_safe(instr
, block
) {
456 if (instr
->type
!= nir_instr_type_intrinsic
)
459 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
461 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
464 b
.cursor
= nir_before_instr(instr
);
466 assert(load
->src
[0].is_ssa
);
468 if (load
->src
[0].ssa
== temp_ubo_name
) {
469 nir_instr_rewrite_src(instr
, &load
->src
[0],
470 nir_src_for_ssa(nir_imm_int(&b
, 0)));
471 } else if (nir_src_as_uint(load
->src
[0]) == 0) {
472 nir_ssa_def
*offset
=
473 nir_iadd(&b
, load
->src
[1].ssa
,
474 nir_imm_int(&b
, 4 * num_system_values
));
475 nir_instr_rewrite_src(instr
, &load
->src
[1],
476 nir_src_for_ssa(offset
));
481 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
482 nir_opt_constant_folding(nir
);
484 ralloc_free(system_values
);
485 system_values
= NULL
;
488 nir_validate_shader(nir
, "after remap");
490 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
491 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
493 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
494 * about it for compute shaders, so go ahead and make some fake ones
495 * which the backend will dead code eliminate.
497 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
498 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
500 /* System values and uniforms are stored in constant buffer 0, the
501 * user-facing UBOs are indexed by one. So if any constant buffer is
502 * needed, the constant buffer 0 will be needed, so account for it.
504 unsigned num_cbufs
= nir
->info
.num_ubos
;
505 if (num_cbufs
|| num_system_values
|| nir
->num_uniforms
)
508 *out_system_values
= system_values
;
509 *out_num_system_values
= num_system_values
;
510 *out_num_cbufs
= num_cbufs
;
514 iris_debug_recompile(struct iris_context
*ice
,
515 struct shader_info
*info
,
516 unsigned program_string_id
,
519 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
520 const struct brw_compiler
*c
= screen
->compiler
;
525 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
526 _mesa_shader_stage_to_string(info
->stage
),
527 info
->name
? info
->name
: "(no identifier)",
528 info
->label
? info
->label
: "");
530 const void *old_key
=
531 iris_find_previous_compile(ice
, info
->stage
, program_string_id
);
533 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
538 * Compile a vertex shader, and upload the assembly.
540 static struct iris_compiled_shader
*
541 iris_compile_vs(struct iris_context
*ice
,
542 struct iris_uncompiled_shader
*ish
,
543 const struct brw_vs_prog_key
*key
)
545 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
546 const struct brw_compiler
*compiler
= screen
->compiler
;
547 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
548 void *mem_ctx
= ralloc_context(NULL
);
549 struct brw_vs_prog_data
*vs_prog_data
=
550 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
551 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
552 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
553 enum brw_param_builtin
*system_values
;
554 unsigned num_system_values
;
557 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
559 if (key
->nr_userclip_plane_consts
) {
560 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
561 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
562 nir_lower_io_to_temporaries(nir
, impl
, true, false);
563 nir_lower_global_vars_to_local(nir
);
564 nir_lower_vars_to_ssa(nir
);
565 nir_shader_gather_info(nir
, impl
);
568 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
569 prog_data
->use_alt_mode
= true;
571 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
572 &num_system_values
, &num_cbufs
);
574 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
575 num_system_values
, num_cbufs
);
577 brw_compute_vue_map(devinfo
,
578 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
579 nir
->info
.separate_shader
);
581 /* Don't tell the backend about our clip plane constants, we've already
582 * lowered them in NIR and we don't want it doing it again.
584 struct brw_vs_prog_key key_no_ucp
= *key
;
585 key_no_ucp
.nr_userclip_plane_consts
= 0;
587 char *error_str
= NULL
;
588 const unsigned *program
=
589 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
590 nir
, -1, &error_str
);
591 if (program
== NULL
) {
592 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
593 ralloc_free(mem_ctx
);
597 if (ish
->compiled_once
) {
598 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
600 ish
->compiled_once
= true;
604 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
605 &vue_prog_data
->vue_map
);
607 struct iris_compiled_shader
*shader
=
608 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
609 prog_data
, so_decls
, system_values
, num_system_values
,
612 ralloc_free(mem_ctx
);
617 * Update the current vertex shader variant.
619 * Fill out the key, look in the cache, compile and bind if needed.
622 iris_update_compiled_vs(struct iris_context
*ice
)
624 struct iris_uncompiled_shader
*ish
=
625 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
626 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
627 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
629 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
630 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
632 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
633 struct iris_compiled_shader
*shader
=
634 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
637 shader
= iris_compile_vs(ice
, ish
, &key
);
640 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
641 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
642 IRIS_DIRTY_BINDINGS_VS
|
643 IRIS_DIRTY_CONSTANTS_VS
|
645 const struct brw_vs_prog_data
*vs_prog_data
=
646 (void *) shader
->prog_data
;
647 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
648 vs_prog_data
->uses_baseinstance
;
649 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
650 vs_prog_data
->uses_is_indexed_draw
;
651 const bool needs_sgvs_element
= uses_draw_params
||
652 vs_prog_data
->uses_instanceid
||
653 vs_prog_data
->uses_vertexid
;
654 bool needs_edge_flag
= false;
655 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
656 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
657 needs_edge_flag
= true;
660 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
661 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
662 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
663 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
664 IRIS_DIRTY_VERTEX_ELEMENTS
;
666 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
667 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
668 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
669 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
674 * Get the shader_info for a given stage, or NULL if the stage is disabled.
676 const struct shader_info
*
677 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
679 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
684 const nir_shader
*nir
= ish
->nir
;
689 * Get the union of TCS output and TES input slots.
691 * TCS and TES need to agree on a common URB entry layout. In particular,
692 * the data for all patch vertices is stored in a single URB entry (unlike
693 * GS which has one entry per input vertex). This means that per-vertex
694 * array indexing needs a stride.
696 * SSO requires locations to match, but doesn't require the number of
697 * outputs/inputs to match (in fact, the TCS often has extra outputs).
698 * So, we need to take the extra step of unifying these on the fly.
701 get_unified_tess_slots(const struct iris_context
*ice
,
702 uint64_t *per_vertex_slots
,
703 uint32_t *per_patch_slots
)
705 const struct shader_info
*tcs
=
706 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
707 const struct shader_info
*tes
=
708 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
710 *per_vertex_slots
= tes
->inputs_read
;
711 *per_patch_slots
= tes
->patch_inputs_read
;
714 *per_vertex_slots
|= tcs
->outputs_written
;
715 *per_patch_slots
|= tcs
->patch_outputs_written
;
720 * Compile a tessellation control shader, and upload the assembly.
722 static struct iris_compiled_shader
*
723 iris_compile_tcs(struct iris_context
*ice
,
724 struct iris_uncompiled_shader
*ish
,
725 const struct brw_tcs_prog_key
*key
)
727 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
728 const struct brw_compiler
*compiler
= screen
->compiler
;
729 const struct nir_shader_compiler_options
*options
=
730 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
731 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
732 void *mem_ctx
= ralloc_context(NULL
);
733 struct brw_tcs_prog_data
*tcs_prog_data
=
734 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
735 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
736 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
737 enum brw_param_builtin
*system_values
= NULL
;
738 unsigned num_system_values
= 0;
739 unsigned num_cbufs
= 0;
744 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
746 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
747 &num_system_values
, &num_cbufs
);
748 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
749 num_system_values
, num_cbufs
);
751 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
753 /* Reserve space for passing the default tess levels as constants. */
754 num_system_values
= 8;
756 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
757 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
758 prog_data
->nr_params
= num_system_values
;
760 if (key
->tes_primitive_mode
== GL_QUADS
) {
761 for (int i
= 0; i
< 4; i
++)
762 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
764 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
765 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
766 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
767 for (int i
= 0; i
< 3; i
++)
768 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
770 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
772 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
773 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
774 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
777 prog_data
->ubo_ranges
[0].length
= 1;
780 char *error_str
= NULL
;
781 const unsigned *program
=
782 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
784 if (program
== NULL
) {
785 dbg_printf("Failed to compile control shader: %s\n", error_str
);
786 ralloc_free(mem_ctx
);
791 if (ish
->compiled_once
) {
792 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
794 ish
->compiled_once
= true;
798 struct iris_compiled_shader
*shader
=
799 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
800 prog_data
, NULL
, system_values
, num_system_values
,
803 ralloc_free(mem_ctx
);
808 * Update the current tessellation control shader variant.
810 * Fill out the key, look in the cache, compile and bind if needed.
813 iris_update_compiled_tcs(struct iris_context
*ice
)
815 struct iris_uncompiled_shader
*tcs
=
816 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
817 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
818 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
820 const struct shader_info
*tes_info
=
821 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
822 struct brw_tcs_prog_key key
= {
823 KEY_INIT_NO_ID(devinfo
->gen
),
824 .program_string_id
= tcs
? tcs
->program_id
: 0,
825 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
826 .input_vertices
= ice
->state
.vertices_per_patch
,
828 get_unified_tess_slots(ice
, &key
.outputs_written
,
829 &key
.patch_outputs_written
);
830 ice
->vtbl
.populate_tcs_key(ice
, &key
);
832 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
833 struct iris_compiled_shader
*shader
=
834 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
837 shader
= iris_compile_tcs(ice
, tcs
, &key
);
840 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
841 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
842 IRIS_DIRTY_BINDINGS_TCS
|
843 IRIS_DIRTY_CONSTANTS_TCS
;
848 * Compile a tessellation evaluation shader, and upload the assembly.
850 static struct iris_compiled_shader
*
851 iris_compile_tes(struct iris_context
*ice
,
852 struct iris_uncompiled_shader
*ish
,
853 const struct brw_tes_prog_key
*key
)
855 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
856 const struct brw_compiler
*compiler
= screen
->compiler
;
857 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
858 void *mem_ctx
= ralloc_context(NULL
);
859 struct brw_tes_prog_data
*tes_prog_data
=
860 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
861 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
862 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
863 enum brw_param_builtin
*system_values
;
864 unsigned num_system_values
;
867 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
869 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
870 &num_system_values
, &num_cbufs
);
872 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
873 num_system_values
, num_cbufs
);
875 struct brw_vue_map input_vue_map
;
876 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
877 key
->patch_inputs_read
);
879 char *error_str
= NULL
;
880 const unsigned *program
=
881 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
882 tes_prog_data
, nir
, NULL
, -1, &error_str
);
883 if (program
== NULL
) {
884 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
885 ralloc_free(mem_ctx
);
889 if (ish
->compiled_once
) {
890 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
892 ish
->compiled_once
= true;
896 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
897 &vue_prog_data
->vue_map
);
900 struct iris_compiled_shader
*shader
=
901 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
902 prog_data
, so_decls
, system_values
, num_system_values
,
905 ralloc_free(mem_ctx
);
910 * Update the current tessellation evaluation shader variant.
912 * Fill out the key, look in the cache, compile and bind if needed.
915 iris_update_compiled_tes(struct iris_context
*ice
)
917 struct iris_uncompiled_shader
*ish
=
918 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
919 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
920 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
922 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
923 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
924 ice
->vtbl
.populate_tes_key(ice
, &key
);
926 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
927 struct iris_compiled_shader
*shader
=
928 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
931 shader
= iris_compile_tes(ice
, ish
, &key
);
934 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
935 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
936 IRIS_DIRTY_BINDINGS_TES
|
937 IRIS_DIRTY_CONSTANTS_TES
;
940 /* TODO: Could compare and avoid flagging this. */
941 const struct shader_info
*tes_info
= &ish
->nir
->info
;
942 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
943 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
944 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].cbuf0_needs_upload
= true;
949 * Compile a geometry shader, and upload the assembly.
951 static struct iris_compiled_shader
*
952 iris_compile_gs(struct iris_context
*ice
,
953 struct iris_uncompiled_shader
*ish
,
954 const struct brw_gs_prog_key
*key
)
956 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
957 const struct brw_compiler
*compiler
= screen
->compiler
;
958 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
959 void *mem_ctx
= ralloc_context(NULL
);
960 struct brw_gs_prog_data
*gs_prog_data
=
961 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
962 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
963 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
964 enum brw_param_builtin
*system_values
;
965 unsigned num_system_values
;
968 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
970 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
971 &num_system_values
, &num_cbufs
);
973 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
974 num_system_values
, num_cbufs
);
976 brw_compute_vue_map(devinfo
,
977 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
978 nir
->info
.separate_shader
);
980 char *error_str
= NULL
;
981 const unsigned *program
=
982 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
983 NULL
, -1, &error_str
);
984 if (program
== NULL
) {
985 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
986 ralloc_free(mem_ctx
);
990 if (ish
->compiled_once
) {
991 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
993 ish
->compiled_once
= true;
997 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
998 &vue_prog_data
->vue_map
);
1000 struct iris_compiled_shader
*shader
=
1001 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1002 prog_data
, so_decls
, system_values
, num_system_values
,
1005 ralloc_free(mem_ctx
);
1010 * Update the current geometry shader variant.
1012 * Fill out the key, look in the cache, compile and bind if needed.
1015 iris_update_compiled_gs(struct iris_context
*ice
)
1017 struct iris_uncompiled_shader
*ish
=
1018 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1019 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1020 struct iris_compiled_shader
*shader
= NULL
;
1023 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1024 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1025 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1026 ice
->vtbl
.populate_gs_key(ice
, &key
);
1029 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1032 shader
= iris_compile_gs(ice
, ish
, &key
);
1035 if (old
!= shader
) {
1036 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1037 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1038 IRIS_DIRTY_BINDINGS_GS
|
1039 IRIS_DIRTY_CONSTANTS_GS
;
1044 * Compile a fragment (pixel) shader, and upload the assembly.
1046 static struct iris_compiled_shader
*
1047 iris_compile_fs(struct iris_context
*ice
,
1048 struct iris_uncompiled_shader
*ish
,
1049 const struct brw_wm_prog_key
*key
,
1050 struct brw_vue_map
*vue_map
)
1052 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1053 const struct brw_compiler
*compiler
= screen
->compiler
;
1054 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1055 void *mem_ctx
= ralloc_context(NULL
);
1056 struct brw_wm_prog_data
*fs_prog_data
=
1057 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1058 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1059 enum brw_param_builtin
*system_values
;
1060 unsigned num_system_values
;
1063 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1065 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1066 prog_data
->use_alt_mode
= true;
1068 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1069 &num_system_values
, &num_cbufs
);
1071 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
1072 MAX2(key
->nr_color_regions
, 1),
1073 num_system_values
, num_cbufs
);
1074 char *error_str
= NULL
;
1075 const unsigned *program
=
1076 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1077 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1078 if (program
== NULL
) {
1079 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1080 ralloc_free(mem_ctx
);
1084 if (ish
->compiled_once
) {
1085 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1087 ish
->compiled_once
= true;
1090 struct iris_compiled_shader
*shader
=
1091 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1092 prog_data
, NULL
, system_values
, num_system_values
,
1095 ralloc_free(mem_ctx
);
1100 * Update the current fragment shader variant.
1102 * Fill out the key, look in the cache, compile and bind if needed.
1105 iris_update_compiled_fs(struct iris_context
*ice
)
1107 struct iris_uncompiled_shader
*ish
=
1108 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1109 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1110 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1111 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1112 ice
->vtbl
.populate_fs_key(ice
, &key
);
1114 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1115 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1117 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1118 struct iris_compiled_shader
*shader
=
1119 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1122 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1124 if (old
!= shader
) {
1125 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1126 // toggles. might be able to avoid flagging SBE too.
1127 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1128 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1129 IRIS_DIRTY_BINDINGS_FS
|
1130 IRIS_DIRTY_CONSTANTS_FS
|
1138 * Get the compiled shader for the last enabled geometry stage.
1140 * This stage is the one which will feed stream output and the rasterizer.
1142 static gl_shader_stage
1143 last_vue_stage(struct iris_context
*ice
)
1145 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
1146 return MESA_SHADER_GEOMETRY
;
1148 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
1149 return MESA_SHADER_TESS_EVAL
;
1151 return MESA_SHADER_VERTEX
;
1155 * Update the last enabled stage's VUE map.
1157 * When the shader feeding the rasterizer's output interface changes, we
1158 * need to re-emit various packets.
1161 update_last_vue_map(struct iris_context
*ice
,
1162 struct brw_stage_prog_data
*prog_data
)
1164 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1165 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1166 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1167 const uint64_t changed_slots
=
1168 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1170 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1171 // XXX: could use ctx->Const.MaxViewports for old API efficiency
1172 ice
->state
.num_viewports
=
1173 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1174 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1175 IRIS_DIRTY_SF_CL_VIEWPORT
|
1176 IRIS_DIRTY_CC_VIEWPORT
|
1177 IRIS_DIRTY_SCISSOR_RECT
|
1178 IRIS_DIRTY_UNCOMPILED_FS
|
1179 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1180 // XXX: CC_VIEWPORT?
1183 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1184 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1187 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1191 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1193 static struct brw_vue_prog_data
*
1194 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1196 if (!ice
->shaders
.prog
[stage
])
1199 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1202 // XXX: iris_compiled_shaders are space-leaking :(
1203 // XXX: do remember to unbind them if deleting them.
1206 * Update the current shader variants for the given state.
1208 * This should be called on every draw call to ensure that the correct
1209 * shaders are bound. It will also flag any dirty state triggered by
1210 * swapping out those shaders.
1213 iris_update_compiled_shaders(struct iris_context
*ice
)
1215 const uint64_t dirty
= ice
->state
.dirty
;
1217 struct brw_vue_prog_data
*old_prog_datas
[4];
1218 if (!(dirty
& IRIS_DIRTY_URB
)) {
1219 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1220 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1223 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1224 struct iris_uncompiled_shader
*tes
=
1225 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1227 iris_update_compiled_tcs(ice
);
1228 iris_update_compiled_tes(ice
);
1230 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1231 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1233 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1234 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1235 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1239 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1240 iris_update_compiled_vs(ice
);
1241 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1242 iris_update_compiled_gs(ice
);
1244 gl_shader_stage last_stage
= last_vue_stage(ice
);
1245 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1246 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1247 update_last_vue_map(ice
, shader
->prog_data
);
1248 if (ice
->state
.streamout
!= shader
->streamout
) {
1249 ice
->state
.streamout
= shader
->streamout
;
1250 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1253 if (ice
->state
.streamout_active
) {
1254 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1255 struct iris_stream_output_target
*so
=
1256 (void *) ice
->state
.so_target
[i
];
1258 so
->stride
= ish
->stream_output
.stride
[i
];
1262 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1263 iris_update_compiled_fs(ice
);
1266 /* Changing shader interfaces may require a URB configuration. */
1267 if (!(dirty
& IRIS_DIRTY_URB
)) {
1268 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1269 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1270 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1271 if (!!old
!= !!new ||
1272 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1273 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1280 static struct iris_compiled_shader
*
1281 iris_compile_cs(struct iris_context
*ice
,
1282 struct iris_uncompiled_shader
*ish
,
1283 const struct brw_cs_prog_key
*key
)
1285 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1286 const struct brw_compiler
*compiler
= screen
->compiler
;
1287 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1288 void *mem_ctx
= ralloc_context(NULL
);
1289 struct brw_cs_prog_data
*cs_prog_data
=
1290 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1291 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1292 enum brw_param_builtin
*system_values
;
1293 unsigned num_system_values
;
1296 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1298 cs_prog_data
->binding_table
.work_groups_start
= 0;
1300 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1302 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1303 &num_system_values
, &num_cbufs
);
1305 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1,
1306 num_system_values
, num_cbufs
);
1308 char *error_str
= NULL
;
1309 const unsigned *program
=
1310 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1311 nir
, -1, &error_str
);
1312 if (program
== NULL
) {
1313 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1314 ralloc_free(mem_ctx
);
1318 if (ish
->compiled_once
) {
1319 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1321 ish
->compiled_once
= true;
1324 struct iris_compiled_shader
*shader
=
1325 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1326 prog_data
, NULL
, system_values
, num_system_values
,
1329 ralloc_free(mem_ctx
);
1334 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1336 struct iris_uncompiled_shader
*ish
=
1337 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1339 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1340 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1341 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1342 ice
->vtbl
.populate_cs_key(ice
, &key
);
1344 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1345 struct iris_compiled_shader
*shader
=
1346 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1349 shader
= iris_compile_cs(ice
, ish
, &key
);
1351 if (old
!= shader
) {
1352 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1353 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1354 IRIS_DIRTY_BINDINGS_CS
|
1355 IRIS_DIRTY_CONSTANTS_CS
;
1360 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1363 assert(cs_prog_data
->push
.total
.size
> 0);
1364 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1365 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1366 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1367 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1372 * Allocate scratch BOs as needed for the given per-thread size and stage.
1375 iris_get_scratch_space(struct iris_context
*ice
,
1376 unsigned per_thread_scratch
,
1377 gl_shader_stage stage
)
1379 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1380 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1381 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1383 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1384 assert(encoded_size
< (1 << 16));
1386 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1388 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1390 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1391 * must allocate scratch space enough so that each slice has 4
1394 * According to the other driver team, this applies to compute shaders
1395 * as well. This is not currently documented at all.
1397 * This hack is no longer necessary on Gen11+.
1399 unsigned subslice_total
= screen
->subslice_total
;
1400 if (devinfo
->gen
< 11)
1401 subslice_total
= 4 * devinfo
->num_slices
;
1402 assert(subslice_total
>= screen
->subslice_total
);
1405 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1406 uint32_t max_threads
[] = {
1407 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1408 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1409 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1410 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1411 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1412 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1415 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1417 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1423 /* ------------------------------------------------------------------- */
1426 * The pipe->create_[stage]_state() driver hooks.
1428 * Performs basic NIR preprocessing, records any state dependencies, and
1429 * returns an iris_uncompiled_shader as the Gallium CSO.
1431 * Actual shader compilation to assembly happens later, at first use.
1434 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1436 const struct pipe_stream_output_info
*so_info
)
1438 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1439 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1441 struct iris_uncompiled_shader
*ish
=
1442 calloc(1, sizeof(struct iris_uncompiled_shader
));
1446 nir
= brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1448 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1449 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1451 ish
->program_id
= get_new_program_id(screen
);
1454 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1455 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1461 static struct iris_uncompiled_shader
*
1462 iris_create_shader_state(struct pipe_context
*ctx
,
1463 const struct pipe_shader_state
*state
)
1465 struct nir_shader
*nir
;
1467 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1468 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1470 nir
= state
->ir
.nir
;
1472 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1476 iris_create_vs_state(struct pipe_context
*ctx
,
1477 const struct pipe_shader_state
*state
)
1479 struct iris_context
*ice
= (void *) ctx
;
1480 struct iris_screen
*screen
= (void *) ctx
->screen
;
1481 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1483 /* User clip planes */
1484 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1485 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
1487 if (screen
->precompile
) {
1488 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1489 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1491 iris_compile_vs(ice
, ish
, &key
);
1498 iris_create_tcs_state(struct pipe_context
*ctx
,
1499 const struct pipe_shader_state
*state
)
1501 struct iris_context
*ice
= (void *) ctx
;
1502 struct iris_screen
*screen
= (void *) ctx
->screen
;
1503 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1504 struct shader_info
*info
= &ish
->nir
->info
;
1508 if (screen
->precompile
) {
1509 const unsigned _GL_TRIANGLES
= 0x0004;
1510 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1511 struct brw_tcs_prog_key key
= {
1512 KEY_INIT(devinfo
->gen
),
1513 // XXX: make sure the linker fills this out from the TES...
1514 .tes_primitive_mode
=
1515 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
1517 .outputs_written
= info
->outputs_written
,
1518 .patch_outputs_written
= info
->patch_outputs_written
,
1521 iris_compile_tcs(ice
, ish
, &key
);
1528 iris_create_tes_state(struct pipe_context
*ctx
,
1529 const struct pipe_shader_state
*state
)
1531 struct iris_context
*ice
= (void *) ctx
;
1532 struct iris_screen
*screen
= (void *) ctx
->screen
;
1533 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1534 struct shader_info
*info
= &ish
->nir
->info
;
1538 if (screen
->precompile
) {
1539 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1540 struct brw_tes_prog_key key
= {
1541 KEY_INIT(devinfo
->gen
),
1542 // XXX: not ideal, need TCS output/TES input unification
1543 .inputs_read
= info
->inputs_read
,
1544 .patch_inputs_read
= info
->patch_inputs_read
,
1547 iris_compile_tes(ice
, ish
, &key
);
1554 iris_create_gs_state(struct pipe_context
*ctx
,
1555 const struct pipe_shader_state
*state
)
1557 struct iris_context
*ice
= (void *) ctx
;
1558 struct iris_screen
*screen
= (void *) ctx
->screen
;
1559 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1563 if (screen
->precompile
) {
1564 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1565 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1567 iris_compile_gs(ice
, ish
, &key
);
1574 iris_create_fs_state(struct pipe_context
*ctx
,
1575 const struct pipe_shader_state
*state
)
1577 struct iris_context
*ice
= (void *) ctx
;
1578 struct iris_screen
*screen
= (void *) ctx
->screen
;
1579 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1580 struct shader_info
*info
= &ish
->nir
->info
;
1582 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
1583 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
1584 (1ull << IRIS_NOS_RASTERIZER
) |
1585 (1ull << IRIS_NOS_BLEND
);
1587 /* The program key needs the VUE map if there are > 16 inputs */
1588 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
1589 BRW_FS_VARYING_INPUT_MASK
) > 16) {
1590 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
1593 if (screen
->precompile
) {
1594 const uint64_t color_outputs
= info
->outputs_written
&
1595 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
1596 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
1597 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
1599 bool can_rearrange_varyings
=
1600 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
1602 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1603 struct brw_wm_prog_key key
= {
1604 KEY_INIT(devinfo
->gen
),
1605 .nr_color_regions
= util_bitcount(color_outputs
),
1606 .coherent_fb_fetch
= true,
1607 .input_slots_valid
=
1608 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
1611 iris_compile_fs(ice
, ish
, &key
, NULL
);
1618 iris_create_compute_state(struct pipe_context
*ctx
,
1619 const struct pipe_compute_state
*state
)
1621 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
1623 struct iris_context
*ice
= (void *) ctx
;
1624 struct iris_screen
*screen
= (void *) ctx
->screen
;
1625 struct iris_uncompiled_shader
*ish
=
1626 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
1628 // XXX: disallow more than 64KB of shared variables
1630 if (screen
->precompile
) {
1631 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1632 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1634 iris_compile_cs(ice
, ish
, &key
);
1641 * The pipe->delete_[stage]_state() driver hooks.
1643 * Frees the iris_uncompiled_shader.
1646 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
1648 struct iris_uncompiled_shader
*ish
= state
;
1649 struct iris_context
*ice
= (void *) ctx
;
1651 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
1652 ice
->shaders
.uncompiled
[stage
] = NULL
;
1653 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
1656 ralloc_free(ish
->nir
);
1661 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1663 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
1667 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1669 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
1673 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1675 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
1679 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1681 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
1685 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
1687 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
1691 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
1693 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
1697 * The pipe->bind_[stage]_state() driver hook.
1699 * Binds an uncompiled shader as the current one for a particular stage.
1700 * Updates dirty tracking to account for the shader's NOS.
1703 bind_state(struct iris_context
*ice
,
1704 struct iris_uncompiled_shader
*ish
,
1705 gl_shader_stage stage
)
1707 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
1708 const uint64_t nos
= ish
? ish
->nos
: 0;
1710 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
1711 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
1713 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
1714 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
1715 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1718 ice
->shaders
.uncompiled
[stage
] = ish
;
1719 ice
->state
.dirty
|= dirty_bit
;
1721 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
1722 * (or that they no longer need to do so).
1724 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
1726 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
1728 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
1733 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1735 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
1739 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1741 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
1745 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1747 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1749 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1750 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
1751 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1753 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
1757 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1759 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1761 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1762 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
1763 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1765 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
1769 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
1771 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1772 struct iris_uncompiled_shader
*old_ish
=
1773 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1774 struct iris_uncompiled_shader
*new_ish
= state
;
1776 const unsigned color_bits
=
1777 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
1778 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
1780 /* Fragment shader outputs influence HasWriteableRT */
1781 if (!old_ish
|| !new_ish
||
1782 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
1783 (new_ish
->nir
->info
.outputs_written
& color_bits
))
1784 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1786 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
1790 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
1792 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
1796 iris_init_program_functions(struct pipe_context
*ctx
)
1798 ctx
->create_vs_state
= iris_create_vs_state
;
1799 ctx
->create_tcs_state
= iris_create_tcs_state
;
1800 ctx
->create_tes_state
= iris_create_tes_state
;
1801 ctx
->create_gs_state
= iris_create_gs_state
;
1802 ctx
->create_fs_state
= iris_create_fs_state
;
1803 ctx
->create_compute_state
= iris_create_compute_state
;
1805 ctx
->delete_vs_state
= iris_delete_vs_state
;
1806 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
1807 ctx
->delete_tes_state
= iris_delete_tes_state
;
1808 ctx
->delete_gs_state
= iris_delete_gs_state
;
1809 ctx
->delete_fs_state
= iris_delete_fs_state
;
1810 ctx
->delete_compute_state
= iris_delete_cs_state
;
1812 ctx
->bind_vs_state
= iris_bind_vs_state
;
1813 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1814 ctx
->bind_tes_state
= iris_bind_tes_state
;
1815 ctx
->bind_gs_state
= iris_bind_gs_state
;
1816 ctx
->bind_fs_state
= iris_bind_fs_state
;
1817 ctx
->bind_compute_state
= iris_bind_cs_state
;