2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "compiler/nir/nir.h"
41 #include "compiler/nir/nir_builder.h"
42 #include "compiler/nir/nir_serialize.h"
43 #include "intel/compiler/brw_compiler.h"
44 #include "intel/compiler/brw_nir.h"
45 #include "iris_context.h"
46 #include "nir/tgsi_to_nir.h"
48 #define KEY_INIT_NO_ID(gen) \
49 .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
50 .tex.compressed_multisample_layout_mask = ~0, \
51 .tex.msaa_16 = (gen >= 9 ? ~0 : 0)
52 #define KEY_INIT(gen) .program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
55 get_new_program_id(struct iris_screen
*screen
)
57 return p_atomic_inc_return(&screen
->program_id
);
61 upload_state(struct u_upload_mgr
*uploader
,
62 struct iris_state_ref
*ref
,
67 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
72 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
73 struct pipe_shader_buffer
*buf
,
74 struct iris_state_ref
*surf_state
,
77 struct pipe_context
*ctx
= &ice
->ctx
;
78 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
80 // XXX: these are not retained forever, use a separate uploader?
82 upload_state(ice
->state
.surface_uploader
, surf_state
,
83 screen
->isl_dev
.ss
.size
, 64);
85 surf_state
->res
= NULL
;
89 struct iris_resource
*res
= (void *) buf
->buffer
;
90 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
91 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
93 isl_buffer_fill_state(&screen
->isl_dev
, map
,
94 .address
= res
->bo
->gtt_offset
+ res
->offset
+
96 .size_B
= buf
->buffer_size
- res
->offset
,
97 .format
= ssbo
? ISL_FORMAT_RAW
98 : ISL_FORMAT_R32G32B32A32_FLOAT
,
99 .swizzle
= ISL_SWIZZLE_IDENTITY
,
101 .mocs
= ice
->vtbl
.mocs(res
->bo
));
105 get_aoa_deref_offset(nir_builder
*b
,
106 nir_deref_instr
*deref
,
109 unsigned array_size
= elem_size
;
110 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
112 while (deref
->deref_type
!= nir_deref_type_var
) {
113 assert(deref
->deref_type
== nir_deref_type_array
);
115 /* This level's element size is the previous level's array size */
116 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
117 assert(deref
->arr
.index
.ssa
);
118 offset
= nir_iadd(b
, offset
,
119 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
121 deref
= nir_deref_instr_parent(deref
);
122 assert(glsl_type_is_array(deref
->type
));
123 array_size
*= glsl_get_length(deref
->type
);
126 /* Accessing an invalid surface index with the dataport can result in a
127 * hang. According to the spec "if the index used to select an individual
128 * element is negative or greater than or equal to the size of the array,
129 * the results of the operation are undefined but may not lead to
130 * termination" -- which is one of the possible outcomes of the hang.
131 * Clamp the index to prevent access outside of the array bounds.
133 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
137 iris_lower_storage_image_derefs(nir_shader
*nir
)
139 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
142 nir_builder_init(&b
, impl
);
144 nir_foreach_block(block
, impl
) {
145 nir_foreach_instr_safe(instr
, block
) {
146 if (instr
->type
!= nir_instr_type_intrinsic
)
149 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
150 switch (intrin
->intrinsic
) {
151 case nir_intrinsic_image_deref_load
:
152 case nir_intrinsic_image_deref_store
:
153 case nir_intrinsic_image_deref_atomic_add
:
154 case nir_intrinsic_image_deref_atomic_min
:
155 case nir_intrinsic_image_deref_atomic_max
:
156 case nir_intrinsic_image_deref_atomic_and
:
157 case nir_intrinsic_image_deref_atomic_or
:
158 case nir_intrinsic_image_deref_atomic_xor
:
159 case nir_intrinsic_image_deref_atomic_exchange
:
160 case nir_intrinsic_image_deref_atomic_comp_swap
:
161 case nir_intrinsic_image_deref_size
:
162 case nir_intrinsic_image_deref_samples
:
163 case nir_intrinsic_image_deref_load_raw_intel
:
164 case nir_intrinsic_image_deref_store_raw_intel
: {
165 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
166 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
168 b
.cursor
= nir_before_instr(&intrin
->instr
);
170 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
171 get_aoa_deref_offset(&b
, deref
, 1));
172 nir_rewrite_image_intrinsic(intrin
, index
, false);
183 // XXX: need unify_interfaces() at link time...
186 * Fix an uncompiled shader's stream output info.
188 * Core Gallium stores output->register_index as a "slot" number, where
189 * slots are assigned consecutively to all outputs in info->outputs_written.
190 * This naive packing of outputs doesn't work for us - we too have slots,
191 * but the layout is defined by the VUE map, which we won't have until we
192 * compile a specific shader variant. So, we remap these and simply store
193 * VARYING_SLOT_* in our copy's output->register_index fields.
195 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
196 * components of our VUE header. See brw_vue_map.c for the layout.
199 update_so_info(struct pipe_stream_output_info
*so_info
,
200 uint64_t outputs_written
)
202 uint8_t reverse_map
[64] = {};
204 while (outputs_written
) {
205 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
208 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
209 struct pipe_stream_output
*output
= &so_info
->output
[i
];
211 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
212 output
->register_index
= reverse_map
[output
->register_index
];
214 /* The VUE header contains three scalar fields packed together:
215 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
216 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
217 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
219 switch (output
->register_index
) {
220 case VARYING_SLOT_LAYER
:
221 assert(output
->num_components
== 1);
222 output
->register_index
= VARYING_SLOT_PSIZ
;
223 output
->start_component
= 1;
225 case VARYING_SLOT_VIEWPORT
:
226 assert(output
->num_components
== 1);
227 output
->register_index
= VARYING_SLOT_PSIZ
;
228 output
->start_component
= 2;
230 case VARYING_SLOT_PSIZ
:
231 assert(output
->num_components
== 1);
232 output
->start_component
= 3;
236 //info->outputs_written |= 1ull << output->register_index;
241 * Sets up the starting offsets for the groups of binding table entries
242 * common to all pipeline stages.
244 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
245 * unused but also make sure that addition of small offsets to them will
246 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
249 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
250 const struct nir_shader
*nir
,
251 struct brw_stage_prog_data
*prog_data
,
252 uint32_t next_binding_table_offset
,
253 unsigned num_system_values
,
256 const struct shader_info
*info
= &nir
->info
;
258 unsigned num_textures
= util_last_bit(info
->textures_used
);
261 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
262 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
263 next_binding_table_offset
+= num_textures
;
265 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
266 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
269 if (info
->num_images
) {
270 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
271 next_binding_table_offset
+= info
->num_images
;
273 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
276 /* Allocate a slot in the UBO section for NIR constants if present.
277 * We don't include them in iris_compiled_shader::num_cbufs because
278 * they are uploaded separately from shs->constbuf[], but from a shader
279 * point of view, they're another UBO (at the end of the section).
281 if (nir
->constant_data_size
> 0)
285 //assert(info->num_ubos <= BRW_MAX_UBO);
286 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
287 next_binding_table_offset
+= num_cbufs
;
289 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
292 if (info
->num_ssbos
|| info
->num_abos
) {
293 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
294 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
295 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
297 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
300 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
302 /* Plane 0 is just the regular texture section */
303 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
305 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
306 next_binding_table_offset
+= num_textures
;
308 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
309 next_binding_table_offset
+= num_textures
;
311 /* Set the binding table size */
312 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
314 return next_binding_table_offset
;
318 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
319 unsigned offset
, unsigned n
)
321 assert(offset
% sizeof(uint32_t) == 0);
323 for (unsigned i
= 0; i
< n
; ++i
)
324 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
326 for (unsigned i
= n
; i
< 4; ++i
)
327 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
331 * Associate NIR uniform variables with the prog_data->param[] mechanism
332 * used by the backend. Also, decide which UBOs we'd like to push in an
333 * ideal situation (though the backend can reduce this).
336 iris_setup_uniforms(const struct brw_compiler
*compiler
,
339 struct brw_stage_prog_data
*prog_data
,
340 enum brw_param_builtin
**out_system_values
,
341 unsigned *out_num_system_values
,
342 unsigned *out_num_cbufs
)
344 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
346 /* The intel compiler assumes that num_uniforms is in bytes. For
347 * scalar that means 4 bytes per uniform slot.
349 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
351 nir
->num_uniforms
*= 4;
353 const unsigned IRIS_MAX_SYSTEM_VALUES
=
354 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
355 enum brw_param_builtin
*system_values
=
356 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
357 unsigned num_system_values
= 0;
359 unsigned patch_vert_idx
= -1;
360 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
361 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
362 memset(ucp_idx
, -1, sizeof(ucp_idx
));
363 memset(img_idx
, -1, sizeof(img_idx
));
365 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
368 nir_builder_init(&b
, impl
);
370 b
.cursor
= nir_before_block(nir_start_block(impl
));
371 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
372 nir_ssa_def
*temp_const_ubo_name
= NULL
;
374 /* Turn system value intrinsics into uniforms */
375 nir_foreach_block(block
, impl
) {
376 nir_foreach_instr_safe(instr
, block
) {
377 if (instr
->type
!= nir_instr_type_intrinsic
)
380 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
383 switch (intrin
->intrinsic
) {
384 case nir_intrinsic_load_constant
: {
385 /* This one is special because it reads from the shader constant
386 * data and not cbuf0 which gallium uploads for us.
388 b
.cursor
= nir_before_instr(instr
);
389 nir_ssa_def
*offset
=
390 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
391 nir_intrinsic_base(intrin
));
393 if (temp_const_ubo_name
== NULL
)
394 temp_const_ubo_name
= nir_imm_int(&b
, 0);
396 nir_intrinsic_instr
*load_ubo
=
397 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
398 load_ubo
->num_components
= intrin
->num_components
;
399 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
400 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
401 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
402 intrin
->dest
.ssa
.num_components
,
403 intrin
->dest
.ssa
.bit_size
,
404 intrin
->dest
.ssa
.name
);
405 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
407 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
408 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
409 nir_instr_remove(&intrin
->instr
);
412 case nir_intrinsic_load_user_clip_plane
: {
413 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
415 if (ucp_idx
[ucp
] == -1) {
416 ucp_idx
[ucp
] = num_system_values
;
417 num_system_values
+= 4;
420 for (int i
= 0; i
< 4; i
++) {
421 system_values
[ucp_idx
[ucp
] + i
] =
422 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
425 b
.cursor
= nir_before_instr(instr
);
426 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
429 case nir_intrinsic_load_patch_vertices_in
:
430 if (patch_vert_idx
== -1)
431 patch_vert_idx
= num_system_values
++;
433 system_values
[patch_vert_idx
] =
434 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
436 b
.cursor
= nir_before_instr(instr
);
437 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
439 case nir_intrinsic_image_deref_load_param_intel
: {
440 assert(devinfo
->gen
< 9);
441 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
442 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
444 /* XXX: var->data.binding is not set properly. We need to run
445 * some form of gl_nir_lower_samplers_as_deref() to get it.
446 * This breaks tests which use more than one image.
448 if (img_idx
[var
->data
.binding
] == -1) {
449 /* GL only allows arrays of arrays of images. */
450 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
451 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
453 for (int i
= 0; i
< num_images
; i
++) {
454 const unsigned img
= var
->data
.binding
+ i
;
456 img_idx
[img
] = num_system_values
;
457 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
459 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
461 setup_vec4_image_sysval(
462 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
463 offsetof(struct brw_image_param
, offset
), 2);
464 setup_vec4_image_sysval(
465 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
466 offsetof(struct brw_image_param
, size
), 3);
467 setup_vec4_image_sysval(
468 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
469 offsetof(struct brw_image_param
, stride
), 4);
470 setup_vec4_image_sysval(
471 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
472 offsetof(struct brw_image_param
, tiling
), 3);
473 setup_vec4_image_sysval(
474 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
475 offsetof(struct brw_image_param
, swizzling
), 2);
479 b
.cursor
= nir_before_instr(instr
);
480 offset
= nir_iadd(&b
,
481 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
482 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
483 nir_intrinsic_base(intrin
) * 16));
490 unsigned comps
= nir_intrinsic_dest_components(intrin
);
492 nir_intrinsic_instr
*load
=
493 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
494 load
->num_components
= comps
;
495 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
496 load
->src
[1] = nir_src_for_ssa(offset
);
497 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
498 nir_builder_instr_insert(&b
, &load
->instr
);
499 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
500 nir_src_for_ssa(&load
->dest
.ssa
));
501 nir_instr_remove(instr
);
505 nir_validate_shader(nir
, "before remapping");
507 /* Place the new params at the front of constant buffer 0. */
508 if (num_system_values
> 0) {
509 nir
->num_uniforms
+= num_system_values
* sizeof(uint32_t);
511 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
514 nir_foreach_block(block
, impl
) {
515 nir_foreach_instr_safe(instr
, block
) {
516 if (instr
->type
!= nir_instr_type_intrinsic
)
519 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
521 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
524 b
.cursor
= nir_before_instr(instr
);
526 assert(load
->src
[0].is_ssa
);
528 if (load
->src
[0].ssa
== temp_ubo_name
) {
529 nir_instr_rewrite_src(instr
, &load
->src
[0],
530 nir_src_for_ssa(nir_imm_int(&b
, 0)));
531 } else if (nir_src_is_const(load
->src
[0]) &&
532 nir_src_as_uint(load
->src
[0]) == 0) {
533 nir_ssa_def
*offset
=
534 nir_iadd(&b
, load
->src
[1].ssa
,
535 nir_imm_int(&b
, 4 * num_system_values
));
536 nir_instr_rewrite_src(instr
, &load
->src
[1],
537 nir_src_for_ssa(offset
));
542 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
543 nir_opt_constant_folding(nir
);
545 ralloc_free(system_values
);
546 system_values
= NULL
;
549 nir_validate_shader(nir
, "after remap");
551 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
552 * about it for compute shaders, so go ahead and make some fake ones
553 * which the backend will dead code eliminate.
555 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
556 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
558 /* System values and uniforms are stored in constant buffer 0, the
559 * user-facing UBOs are indexed by one. So if any constant buffer is
560 * needed, the constant buffer 0 will be needed, so account for it.
562 unsigned num_cbufs
= nir
->info
.num_ubos
;
563 if (num_cbufs
|| num_system_values
|| nir
->num_uniforms
)
566 /* Constant loads (if any) need to go at the end of the constant buffers so
567 * we need to know num_cbufs before we can lower to them.
569 if (temp_const_ubo_name
!= NULL
) {
570 nir_load_const_instr
*const_ubo_index
=
571 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
572 assert(const_ubo_index
->def
.bit_size
== 32);
573 const_ubo_index
->value
[0].u32
= num_cbufs
;
576 *out_system_values
= system_values
;
577 *out_num_system_values
= num_system_values
;
578 *out_num_cbufs
= num_cbufs
;
582 iris_debug_recompile(struct iris_context
*ice
,
583 struct shader_info
*info
,
584 unsigned program_string_id
,
587 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
588 const struct brw_compiler
*c
= screen
->compiler
;
593 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
594 _mesa_shader_stage_to_string(info
->stage
),
595 info
->name
? info
->name
: "(no identifier)",
596 info
->label
? info
->label
: "");
598 const void *old_key
=
599 iris_find_previous_compile(ice
, info
->stage
, program_string_id
);
601 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
606 * Compile a vertex shader, and upload the assembly.
608 static struct iris_compiled_shader
*
609 iris_compile_vs(struct iris_context
*ice
,
610 struct iris_uncompiled_shader
*ish
,
611 const struct brw_vs_prog_key
*key
)
613 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
614 const struct brw_compiler
*compiler
= screen
->compiler
;
615 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
616 void *mem_ctx
= ralloc_context(NULL
);
617 struct brw_vs_prog_data
*vs_prog_data
=
618 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
619 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
620 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
621 enum brw_param_builtin
*system_values
;
622 unsigned num_system_values
;
625 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
627 if (key
->nr_userclip_plane_consts
) {
628 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
629 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
630 nir_lower_io_to_temporaries(nir
, impl
, true, false);
631 nir_lower_global_vars_to_local(nir
);
632 nir_lower_vars_to_ssa(nir
);
633 nir_shader_gather_info(nir
, impl
);
636 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
638 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
639 &num_system_values
, &num_cbufs
);
641 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
642 num_system_values
, num_cbufs
);
644 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
646 brw_compute_vue_map(devinfo
,
647 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
648 nir
->info
.separate_shader
);
650 /* Don't tell the backend about our clip plane constants, we've already
651 * lowered them in NIR and we don't want it doing it again.
653 struct brw_vs_prog_key key_no_ucp
= *key
;
654 key_no_ucp
.nr_userclip_plane_consts
= 0;
656 char *error_str
= NULL
;
657 const unsigned *program
=
658 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
659 nir
, -1, &error_str
);
660 if (program
== NULL
) {
661 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
662 ralloc_free(mem_ctx
);
666 if (ish
->compiled_once
) {
667 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
669 ish
->compiled_once
= true;
673 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
674 &vue_prog_data
->vue_map
);
676 struct iris_compiled_shader
*shader
=
677 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
678 prog_data
, so_decls
, system_values
, num_system_values
,
681 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
683 ralloc_free(mem_ctx
);
688 * Update the current vertex shader variant.
690 * Fill out the key, look in the cache, compile and bind if needed.
693 iris_update_compiled_vs(struct iris_context
*ice
)
695 struct iris_uncompiled_shader
*ish
=
696 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
697 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
698 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
700 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
701 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
703 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
704 struct iris_compiled_shader
*shader
=
705 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
708 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
711 shader
= iris_compile_vs(ice
, ish
, &key
);
714 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
715 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
716 IRIS_DIRTY_BINDINGS_VS
|
717 IRIS_DIRTY_CONSTANTS_VS
|
719 const struct brw_vs_prog_data
*vs_prog_data
=
720 (void *) shader
->prog_data
;
721 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
722 vs_prog_data
->uses_baseinstance
;
723 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
724 vs_prog_data
->uses_is_indexed_draw
;
725 const bool needs_sgvs_element
= uses_draw_params
||
726 vs_prog_data
->uses_instanceid
||
727 vs_prog_data
->uses_vertexid
;
728 bool needs_edge_flag
= false;
729 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
730 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
731 needs_edge_flag
= true;
734 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
735 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
736 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
737 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
738 IRIS_DIRTY_VERTEX_ELEMENTS
;
740 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
741 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
742 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
743 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
748 * Get the shader_info for a given stage, or NULL if the stage is disabled.
750 const struct shader_info
*
751 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
753 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
758 const nir_shader
*nir
= ish
->nir
;
763 * Get the union of TCS output and TES input slots.
765 * TCS and TES need to agree on a common URB entry layout. In particular,
766 * the data for all patch vertices is stored in a single URB entry (unlike
767 * GS which has one entry per input vertex). This means that per-vertex
768 * array indexing needs a stride.
770 * SSO requires locations to match, but doesn't require the number of
771 * outputs/inputs to match (in fact, the TCS often has extra outputs).
772 * So, we need to take the extra step of unifying these on the fly.
775 get_unified_tess_slots(const struct iris_context
*ice
,
776 uint64_t *per_vertex_slots
,
777 uint32_t *per_patch_slots
)
779 const struct shader_info
*tcs
=
780 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
781 const struct shader_info
*tes
=
782 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
784 *per_vertex_slots
= tes
->inputs_read
;
785 *per_patch_slots
= tes
->patch_inputs_read
;
788 *per_vertex_slots
|= tcs
->outputs_written
;
789 *per_patch_slots
|= tcs
->patch_outputs_written
;
794 * Compile a tessellation control shader, and upload the assembly.
796 static struct iris_compiled_shader
*
797 iris_compile_tcs(struct iris_context
*ice
,
798 struct iris_uncompiled_shader
*ish
,
799 const struct brw_tcs_prog_key
*key
)
801 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
802 const struct brw_compiler
*compiler
= screen
->compiler
;
803 const struct nir_shader_compiler_options
*options
=
804 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
805 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
806 void *mem_ctx
= ralloc_context(NULL
);
807 struct brw_tcs_prog_data
*tcs_prog_data
=
808 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
809 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
810 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
811 enum brw_param_builtin
*system_values
= NULL
;
812 unsigned num_system_values
= 0;
813 unsigned num_cbufs
= 0;
818 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
820 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
821 &num_system_values
, &num_cbufs
);
822 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
823 num_system_values
, num_cbufs
);
824 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
826 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
828 /* Reserve space for passing the default tess levels as constants. */
829 num_system_values
= 8;
831 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
832 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
833 prog_data
->nr_params
= num_system_values
;
835 if (key
->tes_primitive_mode
== GL_QUADS
) {
836 for (int i
= 0; i
< 4; i
++)
837 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
839 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
840 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
841 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
842 for (int i
= 0; i
< 3; i
++)
843 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
845 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
847 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
848 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
849 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
852 prog_data
->ubo_ranges
[0].length
= 1;
855 char *error_str
= NULL
;
856 const unsigned *program
=
857 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
859 if (program
== NULL
) {
860 dbg_printf("Failed to compile control shader: %s\n", error_str
);
861 ralloc_free(mem_ctx
);
866 if (ish
->compiled_once
) {
867 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
869 ish
->compiled_once
= true;
873 struct iris_compiled_shader
*shader
=
874 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
875 prog_data
, NULL
, system_values
, num_system_values
,
879 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
881 ralloc_free(mem_ctx
);
886 * Update the current tessellation control shader variant.
888 * Fill out the key, look in the cache, compile and bind if needed.
891 iris_update_compiled_tcs(struct iris_context
*ice
)
893 struct iris_uncompiled_shader
*tcs
=
894 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
895 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
896 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
898 const struct shader_info
*tes_info
=
899 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
900 struct brw_tcs_prog_key key
= {
901 KEY_INIT_NO_ID(devinfo
->gen
),
902 .program_string_id
= tcs
? tcs
->program_id
: 0,
903 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
904 .input_vertices
= ice
->state
.vertices_per_patch
,
906 get_unified_tess_slots(ice
, &key
.outputs_written
,
907 &key
.patch_outputs_written
);
908 ice
->vtbl
.populate_tcs_key(ice
, &key
);
910 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
911 struct iris_compiled_shader
*shader
=
912 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
915 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
918 shader
= iris_compile_tcs(ice
, tcs
, &key
);
921 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
922 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
923 IRIS_DIRTY_BINDINGS_TCS
|
924 IRIS_DIRTY_CONSTANTS_TCS
;
929 * Compile a tessellation evaluation shader, and upload the assembly.
931 static struct iris_compiled_shader
*
932 iris_compile_tes(struct iris_context
*ice
,
933 struct iris_uncompiled_shader
*ish
,
934 const struct brw_tes_prog_key
*key
)
936 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
937 const struct brw_compiler
*compiler
= screen
->compiler
;
938 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
939 void *mem_ctx
= ralloc_context(NULL
);
940 struct brw_tes_prog_data
*tes_prog_data
=
941 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
942 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
943 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
944 enum brw_param_builtin
*system_values
;
945 unsigned num_system_values
;
948 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
950 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
951 &num_system_values
, &num_cbufs
);
953 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
954 num_system_values
, num_cbufs
);
956 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
958 struct brw_vue_map input_vue_map
;
959 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
960 key
->patch_inputs_read
);
962 char *error_str
= NULL
;
963 const unsigned *program
=
964 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
965 tes_prog_data
, nir
, NULL
, -1, &error_str
);
966 if (program
== NULL
) {
967 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
968 ralloc_free(mem_ctx
);
972 if (ish
->compiled_once
) {
973 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
975 ish
->compiled_once
= true;
979 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
980 &vue_prog_data
->vue_map
);
983 struct iris_compiled_shader
*shader
=
984 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
985 prog_data
, so_decls
, system_values
, num_system_values
,
988 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
990 ralloc_free(mem_ctx
);
995 * Update the current tessellation evaluation shader variant.
997 * Fill out the key, look in the cache, compile and bind if needed.
1000 iris_update_compiled_tes(struct iris_context
*ice
)
1002 struct iris_uncompiled_shader
*ish
=
1003 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1004 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1005 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1007 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1008 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1009 ice
->vtbl
.populate_tes_key(ice
, &key
);
1011 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1012 struct iris_compiled_shader
*shader
=
1013 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1016 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1019 shader
= iris_compile_tes(ice
, ish
, &key
);
1021 if (old
!= shader
) {
1022 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1023 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1024 IRIS_DIRTY_BINDINGS_TES
|
1025 IRIS_DIRTY_CONSTANTS_TES
;
1028 /* TODO: Could compare and avoid flagging this. */
1029 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1030 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1031 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1032 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].cbuf0_needs_upload
= true;
1037 * Compile a geometry shader, and upload the assembly.
1039 static struct iris_compiled_shader
*
1040 iris_compile_gs(struct iris_context
*ice
,
1041 struct iris_uncompiled_shader
*ish
,
1042 const struct brw_gs_prog_key
*key
)
1044 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1045 const struct brw_compiler
*compiler
= screen
->compiler
;
1046 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1047 void *mem_ctx
= ralloc_context(NULL
);
1048 struct brw_gs_prog_data
*gs_prog_data
=
1049 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1050 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1051 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1052 enum brw_param_builtin
*system_values
;
1053 unsigned num_system_values
;
1056 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1058 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1059 &num_system_values
, &num_cbufs
);
1061 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
1062 num_system_values
, num_cbufs
);
1064 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1066 brw_compute_vue_map(devinfo
,
1067 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1068 nir
->info
.separate_shader
);
1070 char *error_str
= NULL
;
1071 const unsigned *program
=
1072 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1073 NULL
, -1, &error_str
);
1074 if (program
== NULL
) {
1075 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1076 ralloc_free(mem_ctx
);
1080 if (ish
->compiled_once
) {
1081 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1083 ish
->compiled_once
= true;
1086 uint32_t *so_decls
=
1087 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1088 &vue_prog_data
->vue_map
);
1090 struct iris_compiled_shader
*shader
=
1091 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1092 prog_data
, so_decls
, system_values
, num_system_values
,
1095 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1097 ralloc_free(mem_ctx
);
1102 * Update the current geometry shader variant.
1104 * Fill out the key, look in the cache, compile and bind if needed.
1107 iris_update_compiled_gs(struct iris_context
*ice
)
1109 struct iris_uncompiled_shader
*ish
=
1110 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1111 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1112 struct iris_compiled_shader
*shader
= NULL
;
1115 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1116 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1117 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1118 ice
->vtbl
.populate_gs_key(ice
, &key
);
1121 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1124 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1127 shader
= iris_compile_gs(ice
, ish
, &key
);
1130 if (old
!= shader
) {
1131 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1132 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1133 IRIS_DIRTY_BINDINGS_GS
|
1134 IRIS_DIRTY_CONSTANTS_GS
;
1139 * Compile a fragment (pixel) shader, and upload the assembly.
1141 static struct iris_compiled_shader
*
1142 iris_compile_fs(struct iris_context
*ice
,
1143 struct iris_uncompiled_shader
*ish
,
1144 const struct brw_wm_prog_key
*key
,
1145 struct brw_vue_map
*vue_map
)
1147 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1148 const struct brw_compiler
*compiler
= screen
->compiler
;
1149 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1150 void *mem_ctx
= ralloc_context(NULL
);
1151 struct brw_wm_prog_data
*fs_prog_data
=
1152 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1153 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1154 enum brw_param_builtin
*system_values
;
1155 unsigned num_system_values
;
1158 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1160 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1162 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1163 &num_system_values
, &num_cbufs
);
1165 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
1166 MAX2(key
->nr_color_regions
, 1),
1167 num_system_values
, num_cbufs
);
1169 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1171 char *error_str
= NULL
;
1172 const unsigned *program
=
1173 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1174 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1175 if (program
== NULL
) {
1176 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1177 ralloc_free(mem_ctx
);
1181 if (ish
->compiled_once
) {
1182 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1184 ish
->compiled_once
= true;
1187 struct iris_compiled_shader
*shader
=
1188 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1189 prog_data
, NULL
, system_values
, num_system_values
,
1192 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1194 ralloc_free(mem_ctx
);
1199 * Update the current fragment shader variant.
1201 * Fill out the key, look in the cache, compile and bind if needed.
1204 iris_update_compiled_fs(struct iris_context
*ice
)
1206 struct iris_uncompiled_shader
*ish
=
1207 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1208 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1209 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1210 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1211 ice
->vtbl
.populate_fs_key(ice
, &key
);
1213 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1214 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1216 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1217 struct iris_compiled_shader
*shader
=
1218 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1221 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1224 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1226 if (old
!= shader
) {
1227 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1228 // toggles. might be able to avoid flagging SBE too.
1229 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1230 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1231 IRIS_DIRTY_BINDINGS_FS
|
1232 IRIS_DIRTY_CONSTANTS_FS
|
1240 * Get the compiled shader for the last enabled geometry stage.
1242 * This stage is the one which will feed stream output and the rasterizer.
1244 static gl_shader_stage
1245 last_vue_stage(struct iris_context
*ice
)
1247 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
1248 return MESA_SHADER_GEOMETRY
;
1250 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
1251 return MESA_SHADER_TESS_EVAL
;
1253 return MESA_SHADER_VERTEX
;
1257 * Update the last enabled stage's VUE map.
1259 * When the shader feeding the rasterizer's output interface changes, we
1260 * need to re-emit various packets.
1263 update_last_vue_map(struct iris_context
*ice
,
1264 struct brw_stage_prog_data
*prog_data
)
1266 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1267 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1268 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1269 const uint64_t changed_slots
=
1270 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1272 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1273 // XXX: could use ctx->Const.MaxViewports for old API efficiency
1274 ice
->state
.num_viewports
=
1275 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1276 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1277 IRIS_DIRTY_SF_CL_VIEWPORT
|
1278 IRIS_DIRTY_CC_VIEWPORT
|
1279 IRIS_DIRTY_SCISSOR_RECT
|
1280 IRIS_DIRTY_UNCOMPILED_FS
|
1281 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1282 // XXX: CC_VIEWPORT?
1285 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1286 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1289 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1293 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1295 static struct brw_vue_prog_data
*
1296 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1298 if (!ice
->shaders
.prog
[stage
])
1301 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1304 // XXX: iris_compiled_shaders are space-leaking :(
1305 // XXX: do remember to unbind them if deleting them.
1308 * Update the current shader variants for the given state.
1310 * This should be called on every draw call to ensure that the correct
1311 * shaders are bound. It will also flag any dirty state triggered by
1312 * swapping out those shaders.
1315 iris_update_compiled_shaders(struct iris_context
*ice
)
1317 const uint64_t dirty
= ice
->state
.dirty
;
1319 struct brw_vue_prog_data
*old_prog_datas
[4];
1320 if (!(dirty
& IRIS_DIRTY_URB
)) {
1321 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1322 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1325 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1326 struct iris_uncompiled_shader
*tes
=
1327 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1329 iris_update_compiled_tcs(ice
);
1330 iris_update_compiled_tes(ice
);
1332 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1333 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1335 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1336 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1337 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1341 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1342 iris_update_compiled_vs(ice
);
1343 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1344 iris_update_compiled_gs(ice
);
1346 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1347 const struct iris_compiled_shader
*gs
=
1348 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1349 const struct iris_compiled_shader
*tes
=
1350 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1352 bool points_or_lines
= false;
1355 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1357 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1358 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1360 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1362 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1363 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1366 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1367 /* Outbound to XY Clip enables */
1368 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1369 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1373 gl_shader_stage last_stage
= last_vue_stage(ice
);
1374 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1375 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1376 update_last_vue_map(ice
, shader
->prog_data
);
1377 if (ice
->state
.streamout
!= shader
->streamout
) {
1378 ice
->state
.streamout
= shader
->streamout
;
1379 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1382 if (ice
->state
.streamout_active
) {
1383 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1384 struct iris_stream_output_target
*so
=
1385 (void *) ice
->state
.so_target
[i
];
1387 so
->stride
= ish
->stream_output
.stride
[i
];
1391 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1392 iris_update_compiled_fs(ice
);
1394 /* Changing shader interfaces may require a URB configuration. */
1395 if (!(dirty
& IRIS_DIRTY_URB
)) {
1396 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1397 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1398 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1399 if (!!old
!= !!new ||
1400 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1401 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1408 static struct iris_compiled_shader
*
1409 iris_compile_cs(struct iris_context
*ice
,
1410 struct iris_uncompiled_shader
*ish
,
1411 const struct brw_cs_prog_key
*key
)
1413 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1414 const struct brw_compiler
*compiler
= screen
->compiler
;
1415 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1416 void *mem_ctx
= ralloc_context(NULL
);
1417 struct brw_cs_prog_data
*cs_prog_data
=
1418 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1419 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1420 enum brw_param_builtin
*system_values
;
1421 unsigned num_system_values
;
1424 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1426 cs_prog_data
->binding_table
.work_groups_start
= 0;
1428 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1430 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1431 &num_system_values
, &num_cbufs
);
1433 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1,
1434 num_system_values
, num_cbufs
);
1436 char *error_str
= NULL
;
1437 const unsigned *program
=
1438 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1439 nir
, -1, &error_str
);
1440 if (program
== NULL
) {
1441 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1442 ralloc_free(mem_ctx
);
1446 if (ish
->compiled_once
) {
1447 iris_debug_recompile(ice
, &nir
->info
, key
->program_string_id
, key
);
1449 ish
->compiled_once
= true;
1452 struct iris_compiled_shader
*shader
=
1453 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1454 prog_data
, NULL
, system_values
, num_system_values
,
1457 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1459 ralloc_free(mem_ctx
);
1464 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1466 struct iris_uncompiled_shader
*ish
=
1467 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1469 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1470 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1471 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1472 ice
->vtbl
.populate_cs_key(ice
, &key
);
1474 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1475 struct iris_compiled_shader
*shader
=
1476 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1479 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1482 shader
= iris_compile_cs(ice
, ish
, &key
);
1484 if (old
!= shader
) {
1485 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1486 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1487 IRIS_DIRTY_BINDINGS_CS
|
1488 IRIS_DIRTY_CONSTANTS_CS
;
1493 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1496 assert(cs_prog_data
->push
.total
.size
> 0);
1497 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1498 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1499 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1500 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1505 * Allocate scratch BOs as needed for the given per-thread size and stage.
1508 iris_get_scratch_space(struct iris_context
*ice
,
1509 unsigned per_thread_scratch
,
1510 gl_shader_stage stage
)
1512 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1513 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1514 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1516 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1517 assert(encoded_size
< (1 << 16));
1519 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1521 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1523 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1524 * must allocate scratch space enough so that each slice has 4
1527 * According to the other driver team, this applies to compute shaders
1528 * as well. This is not currently documented at all.
1530 * This hack is no longer necessary on Gen11+.
1532 unsigned subslice_total
= screen
->subslice_total
;
1533 if (devinfo
->gen
< 11)
1534 subslice_total
= 4 * devinfo
->num_slices
;
1535 assert(subslice_total
>= screen
->subslice_total
);
1538 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1539 uint32_t max_threads
[] = {
1540 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1541 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1542 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1543 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1544 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1545 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1548 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1550 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1556 /* ------------------------------------------------------------------- */
1559 * The pipe->create_[stage]_state() driver hooks.
1561 * Performs basic NIR preprocessing, records any state dependencies, and
1562 * returns an iris_uncompiled_shader as the Gallium CSO.
1564 * Actual shader compilation to assembly happens later, at first use.
1567 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1569 const struct pipe_stream_output_info
*so_info
)
1571 struct iris_context
*ice
= (void *)ctx
;
1572 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1573 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1575 struct iris_uncompiled_shader
*ish
=
1576 calloc(1, sizeof(struct iris_uncompiled_shader
));
1580 nir
= brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1582 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1583 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1585 if (nir
->constant_data_size
> 0) {
1586 unsigned data_offset
;
1587 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
1588 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
1590 struct pipe_shader_buffer psb
= {
1591 .buffer
= ish
->const_data
,
1592 .buffer_offset
= data_offset
,
1593 .buffer_size
= nir
->constant_data_size
,
1595 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
1598 ish
->program_id
= get_new_program_id(screen
);
1601 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1602 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1605 /* Save this now before potentially dropping nir->info.name */
1606 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1607 ish
->use_alt_mode
= true;
1609 if (screen
->disk_cache
) {
1610 /* Serialize the NIR to a binary blob that we can hash for the disk
1611 * cache. First, drop unnecessary information (like variable names)
1612 * so the serialized NIR is smaller, and also to let us detect more
1613 * isomorphic shaders when hashing, increasing cache hits. We clone
1614 * the NIR before stripping away this info because it can be useful
1615 * when inspecting and debugging shaders.
1617 nir_shader
*clone
= nir_shader_clone(NULL
, nir
);
1622 nir_serialize(&blob
, clone
);
1623 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
1632 static struct iris_uncompiled_shader
*
1633 iris_create_shader_state(struct pipe_context
*ctx
,
1634 const struct pipe_shader_state
*state
)
1636 struct nir_shader
*nir
;
1638 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1639 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1641 nir
= state
->ir
.nir
;
1643 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1647 iris_create_vs_state(struct pipe_context
*ctx
,
1648 const struct pipe_shader_state
*state
)
1650 struct iris_context
*ice
= (void *) ctx
;
1651 struct iris_screen
*screen
= (void *) ctx
->screen
;
1652 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1654 /* User clip planes */
1655 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1656 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
1658 if (screen
->precompile
) {
1659 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1660 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1662 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1663 iris_compile_vs(ice
, ish
, &key
);
1670 iris_create_tcs_state(struct pipe_context
*ctx
,
1671 const struct pipe_shader_state
*state
)
1673 struct iris_context
*ice
= (void *) ctx
;
1674 struct iris_screen
*screen
= (void *) ctx
->screen
;
1675 const struct brw_compiler
*compiler
= screen
->compiler
;
1676 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1677 struct shader_info
*info
= &ish
->nir
->info
;
1681 if (screen
->precompile
) {
1682 const unsigned _GL_TRIANGLES
= 0x0004;
1683 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1684 struct brw_tcs_prog_key key
= {
1685 KEY_INIT(devinfo
->gen
),
1686 // XXX: make sure the linker fills this out from the TES...
1687 .tes_primitive_mode
=
1688 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
1690 .outputs_written
= info
->outputs_written
,
1691 .patch_outputs_written
= info
->patch_outputs_written
,
1694 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
1695 * We don't have that information, so we randomly guess that the input
1696 * and output patches are the same size. This is a bad guess, but we
1697 * can't do much better.
1699 if (compiler
->use_tcs_8_patch
)
1700 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
1702 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1703 iris_compile_tcs(ice
, ish
, &key
);
1710 iris_create_tes_state(struct pipe_context
*ctx
,
1711 const struct pipe_shader_state
*state
)
1713 struct iris_context
*ice
= (void *) ctx
;
1714 struct iris_screen
*screen
= (void *) ctx
->screen
;
1715 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1716 struct shader_info
*info
= &ish
->nir
->info
;
1720 if (screen
->precompile
) {
1721 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1722 struct brw_tes_prog_key key
= {
1723 KEY_INIT(devinfo
->gen
),
1724 // XXX: not ideal, need TCS output/TES input unification
1725 .inputs_read
= info
->inputs_read
,
1726 .patch_inputs_read
= info
->patch_inputs_read
,
1729 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1730 iris_compile_tes(ice
, ish
, &key
);
1737 iris_create_gs_state(struct pipe_context
*ctx
,
1738 const struct pipe_shader_state
*state
)
1740 struct iris_context
*ice
= (void *) ctx
;
1741 struct iris_screen
*screen
= (void *) ctx
->screen
;
1742 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1746 if (screen
->precompile
) {
1747 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1748 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1750 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1751 iris_compile_gs(ice
, ish
, &key
);
1758 iris_create_fs_state(struct pipe_context
*ctx
,
1759 const struct pipe_shader_state
*state
)
1761 struct iris_context
*ice
= (void *) ctx
;
1762 struct iris_screen
*screen
= (void *) ctx
->screen
;
1763 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1764 struct shader_info
*info
= &ish
->nir
->info
;
1766 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
1767 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
1768 (1ull << IRIS_NOS_RASTERIZER
) |
1769 (1ull << IRIS_NOS_BLEND
);
1771 /* The program key needs the VUE map if there are > 16 inputs */
1772 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
1773 BRW_FS_VARYING_INPUT_MASK
) > 16) {
1774 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
1777 if (screen
->precompile
) {
1778 const uint64_t color_outputs
= info
->outputs_written
&
1779 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
1780 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
1781 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
1783 bool can_rearrange_varyings
=
1784 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
1786 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1787 struct brw_wm_prog_key key
= {
1788 KEY_INIT(devinfo
->gen
),
1789 .nr_color_regions
= util_bitcount(color_outputs
),
1790 .coherent_fb_fetch
= true,
1791 .input_slots_valid
=
1792 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
1795 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1796 iris_compile_fs(ice
, ish
, &key
, NULL
);
1803 iris_create_compute_state(struct pipe_context
*ctx
,
1804 const struct pipe_compute_state
*state
)
1806 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
1808 struct iris_context
*ice
= (void *) ctx
;
1809 struct iris_screen
*screen
= (void *) ctx
->screen
;
1810 struct iris_uncompiled_shader
*ish
=
1811 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
1813 // XXX: disallow more than 64KB of shared variables
1815 if (screen
->precompile
) {
1816 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1817 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1819 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1820 iris_compile_cs(ice
, ish
, &key
);
1827 * The pipe->delete_[stage]_state() driver hooks.
1829 * Frees the iris_uncompiled_shader.
1832 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
1834 struct iris_uncompiled_shader
*ish
= state
;
1835 struct iris_context
*ice
= (void *) ctx
;
1837 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
1838 ice
->shaders
.uncompiled
[stage
] = NULL
;
1839 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
1842 if (ish
->const_data
) {
1843 pipe_resource_reference(&ish
->const_data
, NULL
);
1844 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
1847 ralloc_free(ish
->nir
);
1852 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1854 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
1858 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1860 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
1864 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1866 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
1870 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1872 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
1876 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
1878 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
1882 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
1884 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
1888 * The pipe->bind_[stage]_state() driver hook.
1890 * Binds an uncompiled shader as the current one for a particular stage.
1891 * Updates dirty tracking to account for the shader's NOS.
1894 bind_state(struct iris_context
*ice
,
1895 struct iris_uncompiled_shader
*ish
,
1896 gl_shader_stage stage
)
1898 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
1899 const uint64_t nos
= ish
? ish
->nos
: 0;
1901 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
1902 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
1904 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
1905 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
1906 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1909 ice
->shaders
.uncompiled
[stage
] = ish
;
1910 ice
->state
.dirty
|= dirty_bit
;
1912 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
1913 * (or that they no longer need to do so).
1915 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
1917 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
1919 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
1924 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1926 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
1930 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1932 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
1936 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1938 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1940 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1941 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
1942 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1944 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
1948 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1950 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1952 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1953 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
1954 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1956 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
1960 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
1962 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1963 struct iris_uncompiled_shader
*old_ish
=
1964 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1965 struct iris_uncompiled_shader
*new_ish
= state
;
1967 const unsigned color_bits
=
1968 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
1969 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
1971 /* Fragment shader outputs influence HasWriteableRT */
1972 if (!old_ish
|| !new_ish
||
1973 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
1974 (new_ish
->nir
->info
.outputs_written
& color_bits
))
1975 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1977 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
1981 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
1983 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
1987 iris_init_program_functions(struct pipe_context
*ctx
)
1989 ctx
->create_vs_state
= iris_create_vs_state
;
1990 ctx
->create_tcs_state
= iris_create_tcs_state
;
1991 ctx
->create_tes_state
= iris_create_tes_state
;
1992 ctx
->create_gs_state
= iris_create_gs_state
;
1993 ctx
->create_fs_state
= iris_create_fs_state
;
1994 ctx
->create_compute_state
= iris_create_compute_state
;
1996 ctx
->delete_vs_state
= iris_delete_vs_state
;
1997 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
1998 ctx
->delete_tes_state
= iris_delete_tes_state
;
1999 ctx
->delete_gs_state
= iris_delete_gs_state
;
2000 ctx
->delete_fs_state
= iris_delete_fs_state
;
2001 ctx
->delete_compute_state
= iris_delete_cs_state
;
2003 ctx
->bind_vs_state
= iris_bind_vs_state
;
2004 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2005 ctx
->bind_tes_state
= iris_bind_tes_state
;
2006 ctx
->bind_gs_state
= iris_bind_gs_state
;
2007 ctx
->bind_fs_state
= iris_bind_fs_state
;
2008 ctx
->bind_compute_state
= iris_bind_cs_state
;