src/gallium/drivers/iris/iris_program.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_atomic.h"
  30 #include "compiler/nir/nir.h"
  31 #include "compiler/nir/nir_builder.h"
  32 #include "intel/compiler/brw_compiler.h"
  33 #include "intel/compiler/brw_nir.h"
  34 #include "iris_context.h"
  35
  36 static unsigned
  37 get_new_program_id(struct iris_screen *screen)
  38 {
  39    return p_atomic_inc_return(&screen->program_id);
  40 }
  41
  42 struct iris_uncompiled_shader {
  43    struct pipe_shader_state base;
  44    unsigned program_id;
  45 };
  46
  47 // XXX: need unify_interfaces() at link time...
  48
  49 static void *
  50 iris_create_shader_state(struct pipe_context *ctx,
  51                          const struct pipe_shader_state *state)
  52 {
  53    //struct iris_context *ice = (struct iris_context *)ctx;
  54    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
  55
  56    assert(state->type == PIPE_SHADER_IR_NIR);
  57
  58    nir_shader *nir = state->ir.nir;
  59
  60    struct iris_uncompiled_shader *ish =
  61       calloc(1, sizeof(struct iris_uncompiled_shader));
  62    if (!ish)
  63       return NULL;
  64
  65    nir = brw_preprocess_nir(screen->compiler, nir);
  66
  67    nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
  68                             type_size_scalar_bytes);
  69    nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes, 0);
  70    //NIR_PASS_V(nir, brw_nir_lower_uniforms, true);
  71
  72    ish->program_id = get_new_program_id(screen);
  73    ish->base.type = PIPE_SHADER_IR_NIR;
  74    ish->base.ir.nir = nir;
  75
  76    return ish;
  77 }
  78
  79 static void
  80 iris_delete_shader_state(struct pipe_context *ctx, void *hwcso)
  81 {
  82    struct iris_uncompiled_shader *ish = hwcso;
  83
  84    ralloc_free(ish->base.ir.nir);
  85    free(ish);
  86 }
  87
  88 static void
  89 iris_bind_vs_state(struct pipe_context *ctx, void *hwcso)
  90 {
  91    struct iris_context *ice = (struct iris_context *)ctx;
  92
  93    ice->shaders.progs[MESA_SHADER_VERTEX] = hwcso;
  94    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_VS;
  95 }
  96
  97 static void
  98 iris_bind_tcs_state(struct pipe_context *ctx, void *hwcso)
  99 {
 100    struct iris_context *ice = (struct iris_context *)ctx;
 101
 102    ice->shaders.progs[MESA_SHADER_TESS_CTRL] = hwcso;
 103    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TCS;
 104 }
 105
 106 static void
 107 iris_bind_tes_state(struct pipe_context *ctx, void *hwcso)
 108 {
 109    struct iris_context *ice = (struct iris_context *)ctx;
 110
 111    if (!!hwcso != !!ice->shaders.progs[MESA_SHADER_TESS_EVAL])
 112       ice->state.dirty |= IRIS_DIRTY_URB;
 113
 114    ice->shaders.progs[MESA_SHADER_TESS_EVAL] = hwcso;
 115    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TES;
 116 }
 117
 118 static void
 119 iris_bind_gs_state(struct pipe_context *ctx, void *hwcso)
 120 {
 121    struct iris_context *ice = (struct iris_context *)ctx;
 122
 123    if (!!hwcso != !!ice->shaders.progs[MESA_SHADER_GEOMETRY])
 124       ice->state.dirty |= IRIS_DIRTY_URB;
 125
 126    ice->shaders.progs[MESA_SHADER_GEOMETRY] = hwcso;
 127    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_GS;
 128 }
 129
 130 static void
 131 iris_bind_fs_state(struct pipe_context *ctx, void *hwcso)
 132 {
 133    struct iris_context *ice = (struct iris_context *)ctx;
 134
 135    ice->shaders.progs[MESA_SHADER_FRAGMENT] = hwcso;
 136    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_FS;
 137 }
 138
 139 /**
 140  * Sets up the starting offsets for the groups of binding table entries
 141  * common to all pipeline stages.
 142  *
 143  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 144  * unused but also make sure that addition of small offsets to them will
 145  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 146  */
 147 static uint32_t
 148 assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
 149                                     const struct shader_info *info,
 150                                     struct brw_stage_prog_data *prog_data,
 151                                     uint32_t next_binding_table_offset)
 152 {
 153    prog_data->binding_table.texture_start = next_binding_table_offset;
 154    prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 155    next_binding_table_offset += info->num_textures;
 156
 157    if (info->num_ubos) {
 158       //assert(info->num_ubos <= BRW_MAX_UBO);
 159       prog_data->binding_table.ubo_start = next_binding_table_offset;
 160       next_binding_table_offset += info->num_ubos;
 161    } else {
 162       prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 163    }
 164
 165    if (info->num_ssbos || info->num_abos) {
 166       //assert(info->num_abos <= BRW_MAX_ABO);
 167       //assert(info->num_ssbos <= BRW_MAX_SSBO);
 168       prog_data->binding_table.ssbo_start = next_binding_table_offset;
 169       next_binding_table_offset += info->num_abos + info->num_ssbos;
 170    } else {
 171       prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
 172    }
 173
 174    prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 175
 176    if (info->num_images) {
 177       prog_data->binding_table.image_start = next_binding_table_offset;
 178       next_binding_table_offset += info->num_images;
 179    } else {
 180       prog_data->binding_table.image_start = 0xd0d0d0d0;
 181    }
 182
 183    /* This may or may not be used depending on how the compile goes. */
 184    prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 185    next_binding_table_offset++;
 186
 187    /* Plane 0 is just the regular texture section */
 188    prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
 189
 190    prog_data->binding_table.plane_start[1] = next_binding_table_offset;
 191    next_binding_table_offset += info->num_textures;
 192
 193    prog_data->binding_table.plane_start[2] = next_binding_table_offset;
 194    next_binding_table_offset += info->num_textures;
 195
 196    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 197
 198    //assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 199    return next_binding_table_offset;
 200 }
 201
 202 static bool
 203 iris_compile_vs(struct iris_context *ice,
 204                 struct iris_uncompiled_shader *ish,
 205                 const struct brw_vs_prog_key *key)
 206 {
 207    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 208    const struct brw_compiler *compiler = screen->compiler;
 209    const struct gen_device_info *devinfo = &screen->devinfo;
 210    const unsigned *program;
 211    struct brw_vs_prog_data vs_prog_data;
 212    struct brw_stage_prog_data *prog_data = &vs_prog_data.base.base;
 213    void *mem_ctx = ralloc_context(NULL);
 214
 215    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 216
 217    nir_shader *nir = ish->base.ir.nir;
 218
 219    memset(&vs_prog_data, 0, sizeof(vs_prog_data));
 220
 221    // XXX: alt mode
 222    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data, 0);
 223    brw_compute_vue_map(devinfo,
 224                        &vs_prog_data.base.vue_map, nir->info.outputs_written,
 225                        nir->info.separate_shader);
 226
 227    char *error_str = NULL;
 228    program = brw_compile_vs(compiler, &ice->dbg, mem_ctx, key, &vs_prog_data,
 229                             nir, -1, &error_str);
 230    if (program == NULL) {
 231       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 232
 233       ralloc_free(mem_ctx);
 234       return false;
 235    }
 236
 237    /* The param and pull_param arrays will be freed by the shader cache. */
 238    ralloc_steal(NULL, prog_data->param);
 239    ralloc_steal(NULL, prog_data->pull_param);
 240    iris_upload_cache(ice, IRIS_CACHE_VS, key, sizeof(*key), program,
 241                      prog_data->program_size, prog_data, sizeof(vs_prog_data),
 242                      &ice->shaders.prog_offset[MESA_SHADER_VERTEX],
 243                      &ice->shaders.prog_data[MESA_SHADER_VERTEX]);
 244    ralloc_free(mem_ctx);
 245
 246    return true;
 247 }
 248
 249 static void
 250 iris_populate_vs_key(struct iris_context *ice, struct brw_vs_prog_key *key)
 251 {
 252    memset(key, 0, sizeof(*key));
 253 }
 254
 255 static void
 256 iris_update_compiled_vs(struct iris_context *ice)
 257 {
 258    struct brw_vs_prog_key key;
 259    iris_populate_vs_key(ice, &key);
 260
 261    if (iris_search_cache(ice, IRIS_CACHE_VS, &key, sizeof(key), IRIS_DIRTY_VS,
 262                          &ice->shaders.prog_offset[MESA_SHADER_VERTEX],
 263                          &ice->shaders.prog_data[MESA_SHADER_VERTEX]))
 264       return;
 265
 266    UNUSED bool success =
 267       iris_compile_vs(ice, ice->shaders.progs[MESA_SHADER_VERTEX], &key);
 268 }
 269
 270 static void
 271 iris_update_compiled_tcs(struct iris_context *ice)
 272 {
 273    // XXX: TCS
 274 }
 275
 276 static void
 277 iris_update_compiled_tes(struct iris_context *ice)
 278 {
 279    // XXX: TES
 280 }
 281
 282 static void
 283 iris_update_compiled_gs(struct iris_context *ice)
 284 {
 285    // XXX: GS
 286 }
 287
 288 static bool
 289 iris_compile_fs(struct iris_context *ice,
 290                 struct iris_uncompiled_shader *ish,
 291                 const struct brw_wm_prog_key *key,
 292                 struct brw_vue_map *vue_map)
 293 {
 294    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 295    const struct brw_compiler *compiler = screen->compiler;
 296    const struct gen_device_info *devinfo = &screen->devinfo;
 297    const unsigned *program;
 298    struct brw_wm_prog_data fs_prog_data;
 299    struct brw_stage_prog_data *prog_data = &fs_prog_data.base;
 300    void *mem_ctx = ralloc_context(NULL);
 301
 302    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 303
 304    nir_shader *nir = ish->base.ir.nir;
 305
 306    memset(&fs_prog_data, 0, sizeof(fs_prog_data));
 307
 308    // XXX: alt mode
 309    assign_common_binding_table_offsets(devinfo, &nir->info, prog_data,
 310                                        MAX2(key->nr_color_regions, 1));
 311
 312    char *error_str = NULL;
 313    program = brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, &fs_prog_data,
 314                             nir, NULL, -1, -1, -1, true, false, vue_map,
 315                             &error_str);
 316    if (program == NULL) {
 317       dbg_printf("Failed to compile fragment shader: %s\n", error_str);
 318
 319       ralloc_free(mem_ctx);
 320       return false;
 321    }
 322
 323    //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
 324
 325    /* The param and pull_param arrays will be freed by the shader cache. */
 326    ralloc_steal(NULL, prog_data->param);
 327    ralloc_steal(NULL, prog_data->pull_param);
 328    #if 0
 329    brw_upload_cache(&brw->cache, BRW_CACHE_FS_PROG,
 330                     key, sizeof(struct brw_wm_prog_key),
 331                     program, prog_data.base.program_size,
 332                     &prog_data, sizeof(prog_data),
 333                     &brw->wm.base.prog_offset, &brw->wm.base.prog_data);
 334    #endif
 335
 336    ralloc_free(mem_ctx);
 337
 338    return true;
 339 }
 340
 341 static void
 342 iris_populate_fs_key(struct iris_context *ice, struct brw_wm_prog_key *key)
 343 {
 344    memset(key, 0, sizeof(*key));
 345
 346    /* XXX: dirty flags? */
 347    struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
 348    //struct iris_depth_stencil_alpha_state *zsa = ice->state.framebuffer;
 349    // XXX: can't access iris structs outside iris_state.c :(
 350    // XXX: maybe just move these to iris_state.c, honestly...they're more
 351    // about state than programs...
 352
 353    key->nr_color_regions = fb->nr_cbufs;
 354
 355    // key->force_dual_color_blend for unigine
 356 #if 0
 357    //key->replicate_alpha = fb->nr_cbufs > 1 && alpha test or alpha to coverage
 358    if (cso_rast->multisample) {
 359       key->persample_interp =
 360          ctx->Multisample.SampleShading &&
 361          (ctx->Multisample.MinSampleShadingValue *
 362           _mesa_geometric_samples(ctx->DrawBuffer) > 1);
 363
 364       key->multisample_fbo = fb->samples > 1;
 365    }
 366 #endif
 367
 368    key->coherent_fb_fetch = true;
 369 }
 370
 371 static void
 372 iris_update_compiled_fs(struct iris_context *ice)
 373 {
 374    struct brw_wm_prog_key key;
 375    iris_populate_fs_key(ice, &key);
 376
 377    if (iris_search_cache(ice, IRIS_CACHE_FS, &key, sizeof(key), IRIS_DIRTY_FS,
 378                          &ice->shaders.prog_offset[MESA_SHADER_FRAGMENT],
 379                          &ice->shaders.prog_data[MESA_SHADER_FRAGMENT]))
 380       return;
 381
 382    UNUSED bool success =
 383       iris_compile_fs(ice, ice->shaders.progs[MESA_SHADER_FRAGMENT], &key,
 384                       ice->shaders.last_vue_map);
 385 }
 386
 387 static void
 388 update_last_vue_map(struct iris_context *ice)
 389 {
 390    struct brw_stage_prog_data *prog_data;
 391
 392    if (ice->shaders.progs[MESA_SHADER_GEOMETRY])
 393       prog_data = ice->shaders.prog_data[MESA_SHADER_GEOMETRY];
 394    else if (ice->shaders.progs[MESA_SHADER_TESS_EVAL])
 395       prog_data = ice->shaders.prog_data[MESA_SHADER_TESS_EVAL];
 396    else
 397       prog_data = ice->shaders.prog_data[MESA_SHADER_VERTEX];
 398
 399    struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
 400    ice->shaders.last_vue_map = &vue_prog_data->vue_map;
 401 }
 402
 403 void
 404 iris_update_compiled_shaders(struct iris_context *ice)
 405 {
 406    struct brw_vue_prog_data *old_prog_datas[4];
 407    if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
 408       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++)
 409          old_prog_datas[i] = (void *) ice->shaders.prog_data[i];
 410    }
 411
 412    iris_update_compiled_vs(ice);
 413    iris_update_compiled_tcs(ice);
 414    iris_update_compiled_tes(ice);
 415    iris_update_compiled_gs(ice);
 416    update_last_vue_map(ice);
 417    iris_update_compiled_fs(ice);
 418    // ...
 419
 420    if (!(ice->state.dirty & IRIS_DIRTY_URB)) {
 421       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 422          struct brw_vue_prog_data *old = old_prog_datas[i];
 423          struct brw_vue_prog_data *new = (void *) ice->shaders.prog_data[i];
 424          if (!!old != !!new ||
 425              (new && new->urb_entry_size != old->urb_entry_size)) {
 426             ice->state.dirty |= IRIS_DIRTY_URB;
 427             break;
 428          }
 429       }
 430    }
 431
 432    if (ice->state.dirty & IRIS_DIRTY_URB) {
 433       // ... back to the state module :/
 434    }
 435 }
 436
 437 void
 438 iris_init_program_functions(struct pipe_context *ctx)
 439 {
 440    ctx->create_vs_state  = iris_create_shader_state;
 441    ctx->create_tcs_state = iris_create_shader_state;
 442    ctx->create_tes_state = iris_create_shader_state;
 443    ctx->create_gs_state  = iris_create_shader_state;
 444    ctx->create_fs_state  = iris_create_shader_state;
 445
 446    ctx->delete_vs_state  = iris_delete_shader_state;
 447    ctx->delete_tcs_state = iris_delete_shader_state;
 448    ctx->delete_tes_state = iris_delete_shader_state;
 449    ctx->delete_gs_state  = iris_delete_shader_state;
 450    ctx->delete_fs_state  = iris_delete_shader_state;
 451
 452    ctx->bind_vs_state  = iris_bind_vs_state;
 453    ctx->bind_tcs_state = iris_bind_tcs_state;
 454    ctx->bind_tes_state = iris_bind_tes_state;
 455    ctx->bind_gs_state  = iris_bind_gs_state;
 456    ctx->bind_fs_state  = iris_bind_fs_state;
 457 }