2 * Copyright © 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/debug.h"
41 #include "compiler/nir/nir.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "compiler/nir/nir_serialize.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/compiler/brw_nir.h"
46 #include "iris_context.h"
47 #include "nir/tgsi_to_nir.h"
49 #define KEY_INIT_NO_ID(gen) \
50 .base.subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM, \
51 .base.tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
52 .base.tex.compressed_multisample_layout_mask = ~0, \
53 .base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
54 #define KEY_INIT(gen) .base.program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
57 get_new_program_id(struct iris_screen
*screen
)
59 return p_atomic_inc_return(&screen
->program_id
);
63 upload_state(struct u_upload_mgr
*uploader
,
64 struct iris_state_ref
*ref
,
69 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
74 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
75 struct pipe_shader_buffer
*buf
,
76 struct iris_state_ref
*surf_state
,
79 struct pipe_context
*ctx
= &ice
->ctx
;
80 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
83 upload_state(ice
->state
.surface_uploader
, surf_state
,
84 screen
->isl_dev
.ss
.size
, 64);
86 surf_state
->res
= NULL
;
90 struct iris_resource
*res
= (void *) buf
->buffer
;
91 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
92 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
94 isl_buffer_fill_state(&screen
->isl_dev
, map
,
95 .address
= res
->bo
->gtt_offset
+ res
->offset
+
97 .size_B
= buf
->buffer_size
- res
->offset
,
98 .format
= ssbo
? ISL_FORMAT_RAW
99 : ISL_FORMAT_R32G32B32A32_FLOAT
,
100 .swizzle
= ISL_SWIZZLE_IDENTITY
,
102 .mocs
= ice
->vtbl
.mocs(res
->bo
));
106 get_aoa_deref_offset(nir_builder
*b
,
107 nir_deref_instr
*deref
,
110 unsigned array_size
= elem_size
;
111 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
113 while (deref
->deref_type
!= nir_deref_type_var
) {
114 assert(deref
->deref_type
== nir_deref_type_array
);
116 /* This level's element size is the previous level's array size */
117 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
118 assert(deref
->arr
.index
.ssa
);
119 offset
= nir_iadd(b
, offset
,
120 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
122 deref
= nir_deref_instr_parent(deref
);
123 assert(glsl_type_is_array(deref
->type
));
124 array_size
*= glsl_get_length(deref
->type
);
127 /* Accessing an invalid surface index with the dataport can result in a
128 * hang. According to the spec "if the index used to select an individual
129 * element is negative or greater than or equal to the size of the array,
130 * the results of the operation are undefined but may not lead to
131 * termination" -- which is one of the possible outcomes of the hang.
132 * Clamp the index to prevent access outside of the array bounds.
134 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
138 iris_lower_storage_image_derefs(nir_shader
*nir
)
140 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
143 nir_builder_init(&b
, impl
);
145 nir_foreach_block(block
, impl
) {
146 nir_foreach_instr_safe(instr
, block
) {
147 if (instr
->type
!= nir_instr_type_intrinsic
)
150 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
151 switch (intrin
->intrinsic
) {
152 case nir_intrinsic_image_deref_load
:
153 case nir_intrinsic_image_deref_store
:
154 case nir_intrinsic_image_deref_atomic_add
:
155 case nir_intrinsic_image_deref_atomic_min
:
156 case nir_intrinsic_image_deref_atomic_max
:
157 case nir_intrinsic_image_deref_atomic_and
:
158 case nir_intrinsic_image_deref_atomic_or
:
159 case nir_intrinsic_image_deref_atomic_xor
:
160 case nir_intrinsic_image_deref_atomic_exchange
:
161 case nir_intrinsic_image_deref_atomic_comp_swap
:
162 case nir_intrinsic_image_deref_size
:
163 case nir_intrinsic_image_deref_samples
:
164 case nir_intrinsic_image_deref_load_raw_intel
:
165 case nir_intrinsic_image_deref_store_raw_intel
: {
166 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
167 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
169 b
.cursor
= nir_before_instr(&intrin
->instr
);
171 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
172 get_aoa_deref_offset(&b
, deref
, 1));
173 nir_rewrite_image_intrinsic(intrin
, index
, false);
184 // XXX: need unify_interfaces() at link time...
187 * Fix an uncompiled shader's stream output info.
189 * Core Gallium stores output->register_index as a "slot" number, where
190 * slots are assigned consecutively to all outputs in info->outputs_written.
191 * This naive packing of outputs doesn't work for us - we too have slots,
192 * but the layout is defined by the VUE map, which we won't have until we
193 * compile a specific shader variant. So, we remap these and simply store
194 * VARYING_SLOT_* in our copy's output->register_index fields.
196 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
197 * components of our VUE header. See brw_vue_map.c for the layout.
200 update_so_info(struct pipe_stream_output_info
*so_info
,
201 uint64_t outputs_written
)
203 uint8_t reverse_map
[64] = {};
205 while (outputs_written
) {
206 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
209 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
210 struct pipe_stream_output
*output
= &so_info
->output
[i
];
212 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
213 output
->register_index
= reverse_map
[output
->register_index
];
215 /* The VUE header contains three scalar fields packed together:
216 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
217 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
218 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
220 switch (output
->register_index
) {
221 case VARYING_SLOT_LAYER
:
222 assert(output
->num_components
== 1);
223 output
->register_index
= VARYING_SLOT_PSIZ
;
224 output
->start_component
= 1;
226 case VARYING_SLOT_VIEWPORT
:
227 assert(output
->num_components
== 1);
228 output
->register_index
= VARYING_SLOT_PSIZ
;
229 output
->start_component
= 2;
231 case VARYING_SLOT_PSIZ
:
232 assert(output
->num_components
== 1);
233 output
->start_component
= 3;
237 //info->outputs_written |= 1ull << output->register_index;
242 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
243 unsigned offset
, unsigned n
)
245 assert(offset
% sizeof(uint32_t) == 0);
247 for (unsigned i
= 0; i
< n
; ++i
)
248 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
250 for (unsigned i
= n
; i
< 4; ++i
)
251 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
255 * Associate NIR uniform variables with the prog_data->param[] mechanism
256 * used by the backend. Also, decide which UBOs we'd like to push in an
257 * ideal situation (though the backend can reduce this).
260 iris_setup_uniforms(const struct brw_compiler
*compiler
,
263 struct brw_stage_prog_data
*prog_data
,
264 enum brw_param_builtin
**out_system_values
,
265 unsigned *out_num_system_values
,
266 unsigned *out_num_cbufs
)
268 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
270 /* The intel compiler assumes that num_uniforms is in bytes. For
271 * scalar that means 4 bytes per uniform slot.
273 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
275 nir
->num_uniforms
*= 4;
277 const unsigned IRIS_MAX_SYSTEM_VALUES
=
278 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
279 enum brw_param_builtin
*system_values
=
280 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
281 unsigned num_system_values
= 0;
283 unsigned patch_vert_idx
= -1;
284 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
285 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
286 memset(ucp_idx
, -1, sizeof(ucp_idx
));
287 memset(img_idx
, -1, sizeof(img_idx
));
289 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
292 nir_builder_init(&b
, impl
);
294 b
.cursor
= nir_before_block(nir_start_block(impl
));
295 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
296 nir_ssa_def
*temp_const_ubo_name
= NULL
;
298 /* Turn system value intrinsics into uniforms */
299 nir_foreach_block(block
, impl
) {
300 nir_foreach_instr_safe(instr
, block
) {
301 if (instr
->type
!= nir_instr_type_intrinsic
)
304 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
307 switch (intrin
->intrinsic
) {
308 case nir_intrinsic_load_constant
: {
309 /* This one is special because it reads from the shader constant
310 * data and not cbuf0 which gallium uploads for us.
312 b
.cursor
= nir_before_instr(instr
);
313 nir_ssa_def
*offset
=
314 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
315 nir_intrinsic_base(intrin
));
317 if (temp_const_ubo_name
== NULL
)
318 temp_const_ubo_name
= nir_imm_int(&b
, 0);
320 nir_intrinsic_instr
*load_ubo
=
321 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
322 load_ubo
->num_components
= intrin
->num_components
;
323 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
324 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
325 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
326 intrin
->dest
.ssa
.num_components
,
327 intrin
->dest
.ssa
.bit_size
,
328 intrin
->dest
.ssa
.name
);
329 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
331 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
332 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
333 nir_instr_remove(&intrin
->instr
);
336 case nir_intrinsic_load_user_clip_plane
: {
337 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
339 if (ucp_idx
[ucp
] == -1) {
340 ucp_idx
[ucp
] = num_system_values
;
341 num_system_values
+= 4;
344 for (int i
= 0; i
< 4; i
++) {
345 system_values
[ucp_idx
[ucp
] + i
] =
346 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
349 b
.cursor
= nir_before_instr(instr
);
350 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
353 case nir_intrinsic_load_patch_vertices_in
:
354 if (patch_vert_idx
== -1)
355 patch_vert_idx
= num_system_values
++;
357 system_values
[patch_vert_idx
] =
358 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
360 b
.cursor
= nir_before_instr(instr
);
361 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
363 case nir_intrinsic_image_deref_load_param_intel
: {
364 assert(devinfo
->gen
< 9);
365 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
366 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
368 if (img_idx
[var
->data
.binding
] == -1) {
369 /* GL only allows arrays of arrays of images. */
370 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
371 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
373 for (int i
= 0; i
< num_images
; i
++) {
374 const unsigned img
= var
->data
.binding
+ i
;
376 img_idx
[img
] = num_system_values
;
377 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
379 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
381 setup_vec4_image_sysval(
382 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
383 offsetof(struct brw_image_param
, offset
), 2);
384 setup_vec4_image_sysval(
385 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
386 offsetof(struct brw_image_param
, size
), 3);
387 setup_vec4_image_sysval(
388 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
389 offsetof(struct brw_image_param
, stride
), 4);
390 setup_vec4_image_sysval(
391 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
392 offsetof(struct brw_image_param
, tiling
), 3);
393 setup_vec4_image_sysval(
394 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
395 offsetof(struct brw_image_param
, swizzling
), 2);
399 b
.cursor
= nir_before_instr(instr
);
400 offset
= nir_iadd(&b
,
401 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
402 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
403 nir_intrinsic_base(intrin
) * 16));
410 unsigned comps
= nir_intrinsic_dest_components(intrin
);
412 nir_intrinsic_instr
*load
=
413 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
414 load
->num_components
= comps
;
415 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
416 load
->src
[1] = nir_src_for_ssa(offset
);
417 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
418 nir_builder_instr_insert(&b
, &load
->instr
);
419 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
420 nir_src_for_ssa(&load
->dest
.ssa
));
421 nir_instr_remove(instr
);
425 nir_validate_shader(nir
, "before remapping");
427 /* Uniforms are stored in constant buffer 0, the
428 * user-facing UBOs are indexed by one. So if any constant buffer is
429 * needed, the constant buffer 0 will be needed, so account for it.
431 unsigned num_cbufs
= nir
->info
.num_ubos
;
432 if (num_cbufs
|| nir
->num_uniforms
)
435 /* Place the new params in a new cbuf. */
436 if (num_system_values
> 0) {
437 unsigned sysval_cbuf_index
= num_cbufs
;
440 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
443 nir_foreach_block(block
, impl
) {
444 nir_foreach_instr_safe(instr
, block
) {
445 if (instr
->type
!= nir_instr_type_intrinsic
)
448 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
450 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
453 b
.cursor
= nir_before_instr(instr
);
455 assert(load
->src
[0].is_ssa
);
457 if (load
->src
[0].ssa
== temp_ubo_name
) {
458 nir_ssa_def
*imm
= nir_imm_int(&b
, sysval_cbuf_index
);
459 nir_instr_rewrite_src(instr
, &load
->src
[0],
460 nir_src_for_ssa(imm
));
465 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
466 nir_opt_constant_folding(nir
);
468 ralloc_free(system_values
);
469 system_values
= NULL
;
472 assert(num_cbufs
< PIPE_MAX_CONSTANT_BUFFERS
);
473 nir_validate_shader(nir
, "after remap");
475 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
476 * about it for compute shaders, so go ahead and make some fake ones
477 * which the backend will dead code eliminate.
479 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
480 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
482 /* Constant loads (if any) need to go at the end of the constant buffers so
483 * we need to know num_cbufs before we can lower to them.
485 if (temp_const_ubo_name
!= NULL
) {
486 nir_load_const_instr
*const_ubo_index
=
487 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
488 assert(const_ubo_index
->def
.bit_size
== 32);
489 const_ubo_index
->value
[0].u32
= num_cbufs
;
492 *out_system_values
= system_values
;
493 *out_num_system_values
= num_system_values
;
494 *out_num_cbufs
= num_cbufs
;
497 static const char *surface_group_names
[] = {
498 [IRIS_SURFACE_GROUP_RENDER_TARGET
] = "render target",
499 [IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = "non-coherent render target read",
500 [IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = "CS work groups",
501 [IRIS_SURFACE_GROUP_TEXTURE
] = "texture",
502 [IRIS_SURFACE_GROUP_UBO
] = "ubo",
503 [IRIS_SURFACE_GROUP_SSBO
] = "ssbo",
504 [IRIS_SURFACE_GROUP_IMAGE
] = "image",
508 iris_print_binding_table(FILE *fp
, const char *name
,
509 const struct iris_binding_table
*bt
)
511 STATIC_ASSERT(ARRAY_SIZE(surface_group_names
) == IRIS_SURFACE_GROUP_COUNT
);
514 uint32_t compacted
= 0;
516 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
517 uint32_t size
= bt
->sizes
[i
];
520 compacted
+= util_bitcount64(bt
->used_mask
[i
]);
524 fprintf(fp
, "Binding table for %s is empty\n\n", name
);
528 if (total
!= compacted
) {
529 fprintf(fp
, "Binding table for %s "
530 "(compacted to %u entries from %u entries)\n",
531 name
, compacted
, total
);
533 fprintf(fp
, "Binding table for %s (%u entries)\n", name
, total
);
537 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
538 uint64_t mask
= bt
->used_mask
[i
];
540 int index
= u_bit_scan64(&mask
);
541 fprintf(fp
, " [%u] %s #%d\n", entry
++, surface_group_names
[i
], index
);
548 /* Max elements in a surface group. */
549 SURFACE_GROUP_MAX_ELEMENTS
= 64,
553 * Map a <group, index> pair to a binding table index.
555 * For example: <UBO, 5> => binding table index 12
558 iris_group_index_to_bti(const struct iris_binding_table
*bt
,
559 enum iris_surface_group group
, uint32_t index
)
561 assert(index
< bt
->sizes
[group
]);
562 uint64_t mask
= bt
->used_mask
[group
];
563 uint64_t bit
= 1ull << index
;
565 return bt
->offsets
[group
] + util_bitcount64((bit
- 1) & mask
);
567 return IRIS_SURFACE_NOT_USED
;
572 * Map a binding table index back to a <group, index> pair.
574 * For example: binding table index 12 => <UBO, 5>
577 iris_bti_to_group_index(const struct iris_binding_table
*bt
,
578 enum iris_surface_group group
, uint32_t bti
)
580 uint64_t used_mask
= bt
->used_mask
[group
];
581 assert(bti
>= bt
->offsets
[group
]);
583 uint32_t c
= bti
- bt
->offsets
[group
];
585 int i
= u_bit_scan64(&used_mask
);
591 return IRIS_SURFACE_NOT_USED
;
595 rewrite_src_with_bti(nir_builder
*b
, struct iris_binding_table
*bt
,
596 nir_instr
*instr
, nir_src
*src
,
597 enum iris_surface_group group
)
599 assert(bt
->sizes
[group
] > 0);
601 b
->cursor
= nir_before_instr(instr
);
603 if (nir_src_is_const(*src
)) {
604 uint32_t index
= nir_src_as_uint(*src
);
605 bti
= nir_imm_intN_t(b
, iris_group_index_to_bti(bt
, group
, index
),
608 /* Indirect usage makes all the surfaces of the group to be available,
609 * so we can just add the base.
611 assert(bt
->used_mask
[group
] == BITFIELD64_MASK(bt
->sizes
[group
]));
612 bti
= nir_iadd_imm(b
, src
->ssa
, bt
->offsets
[group
]);
614 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(bti
));
618 mark_used_with_src(struct iris_binding_table
*bt
, nir_src
*src
,
619 enum iris_surface_group group
)
621 assert(bt
->sizes
[group
] > 0);
623 if (nir_src_is_const(*src
)) {
624 uint64_t index
= nir_src_as_uint(*src
);
625 assert(index
< bt
->sizes
[group
]);
626 bt
->used_mask
[group
] |= 1ull << index
;
628 /* There's an indirect usage, we need all the surfaces. */
629 bt
->used_mask
[group
] = BITFIELD64_MASK(bt
->sizes
[group
]);
634 skip_compacting_binding_tables(void)
636 static int skip
= -1;
638 skip
= env_var_as_boolean("INTEL_DISABLE_COMPACT_BINDING_TABLE", false);
643 * Set up the binding table indices and apply to the shader.
646 iris_setup_binding_table(const struct gen_device_info
*devinfo
,
647 struct nir_shader
*nir
,
648 struct iris_binding_table
*bt
,
649 unsigned num_render_targets
,
650 unsigned num_system_values
,
653 const struct shader_info
*info
= &nir
->info
;
655 memset(bt
, 0, sizeof(*bt
));
657 /* Set the sizes for each surface group. For some groups, we already know
658 * upfront how many will be used, so mark them.
660 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
661 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET
] = num_render_targets
;
662 /* All render targets used. */
663 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET
] =
664 BITFIELD64_MASK(num_render_targets
);
666 /* Setup render target read surface group inorder to support non-coherent
667 * framebuffer fetch on Gen8
669 if (devinfo
->gen
== 8 && info
->outputs_read
) {
670 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = num_render_targets
;
671 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] =
672 BITFIELD64_MASK(num_render_targets
);
674 } else if (info
->stage
== MESA_SHADER_COMPUTE
) {
675 bt
->sizes
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
678 bt
->sizes
[IRIS_SURFACE_GROUP_TEXTURE
] = util_last_bit(info
->textures_used
);
679 bt
->used_mask
[IRIS_SURFACE_GROUP_TEXTURE
] = info
->textures_used
;
681 bt
->sizes
[IRIS_SURFACE_GROUP_IMAGE
] = info
->num_images
;
683 /* Allocate an extra slot in the UBO section for NIR constants.
684 * Binding table compaction will remove it if unnecessary.
686 * We don't include them in iris_compiled_shader::num_cbufs because
687 * they are uploaded separately from shs->constbuf[], but from a shader
688 * point of view, they're another UBO (at the end of the section).
690 bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] = num_cbufs
+ 1;
692 /* The first IRIS_MAX_ABOs indices in the SSBO group are for atomics, real
693 * SSBOs start after that. Compaction will remove unused ABOs.
695 bt
->sizes
[IRIS_SURFACE_GROUP_SSBO
] = IRIS_MAX_ABOS
+ info
->num_ssbos
;
697 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
698 assert(bt
->sizes
[i
] <= SURFACE_GROUP_MAX_ELEMENTS
);
700 /* Mark surfaces used for the cases we don't have the information available
703 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
704 nir_foreach_block (block
, impl
) {
705 nir_foreach_instr (instr
, block
) {
706 if (instr
->type
!= nir_instr_type_intrinsic
)
709 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
710 switch (intrin
->intrinsic
) {
711 case nir_intrinsic_load_num_work_groups
:
712 bt
->used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
715 case nir_intrinsic_load_output
:
716 if (devinfo
->gen
== 8) {
717 mark_used_with_src(bt
, &intrin
->src
[0],
718 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
722 case nir_intrinsic_image_size
:
723 case nir_intrinsic_image_load
:
724 case nir_intrinsic_image_store
:
725 case nir_intrinsic_image_atomic_add
:
726 case nir_intrinsic_image_atomic_min
:
727 case nir_intrinsic_image_atomic_max
:
728 case nir_intrinsic_image_atomic_and
:
729 case nir_intrinsic_image_atomic_or
:
730 case nir_intrinsic_image_atomic_xor
:
731 case nir_intrinsic_image_atomic_exchange
:
732 case nir_intrinsic_image_atomic_comp_swap
:
733 case nir_intrinsic_image_load_raw_intel
:
734 case nir_intrinsic_image_store_raw_intel
:
735 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_IMAGE
);
738 case nir_intrinsic_load_ubo
:
739 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_UBO
);
742 case nir_intrinsic_store_ssbo
:
743 mark_used_with_src(bt
, &intrin
->src
[1], IRIS_SURFACE_GROUP_SSBO
);
746 case nir_intrinsic_get_buffer_size
:
747 case nir_intrinsic_ssbo_atomic_add
:
748 case nir_intrinsic_ssbo_atomic_imin
:
749 case nir_intrinsic_ssbo_atomic_umin
:
750 case nir_intrinsic_ssbo_atomic_imax
:
751 case nir_intrinsic_ssbo_atomic_umax
:
752 case nir_intrinsic_ssbo_atomic_and
:
753 case nir_intrinsic_ssbo_atomic_or
:
754 case nir_intrinsic_ssbo_atomic_xor
:
755 case nir_intrinsic_ssbo_atomic_exchange
:
756 case nir_intrinsic_ssbo_atomic_comp_swap
:
757 case nir_intrinsic_ssbo_atomic_fmin
:
758 case nir_intrinsic_ssbo_atomic_fmax
:
759 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
760 case nir_intrinsic_load_ssbo
:
761 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_SSBO
);
770 /* When disable we just mark everything as used. */
771 if (unlikely(skip_compacting_binding_tables())) {
772 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
773 bt
->used_mask
[i
] = BITFIELD64_MASK(bt
->sizes
[i
]);
776 /* Calculate the offsets and the binding table size based on the used
777 * surfaces. After this point, the functions to go between "group indices"
778 * and binding table indices can be used.
781 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
782 if (bt
->used_mask
[i
] != 0) {
783 bt
->offsets
[i
] = next
;
784 next
+= util_bitcount64(bt
->used_mask
[i
]);
787 bt
->size_bytes
= next
* 4;
789 if (unlikely(INTEL_DEBUG
& DEBUG_BT
)) {
790 iris_print_binding_table(stderr
, gl_shader_stage_name(info
->stage
), bt
);
793 /* Apply the binding table indices. The backend compiler is not expected
794 * to change those, as we haven't set any of the *_start entries in brw
798 nir_builder_init(&b
, impl
);
800 nir_foreach_block (block
, impl
) {
801 nir_foreach_instr (instr
, block
) {
802 if (instr
->type
== nir_instr_type_tex
) {
803 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
805 iris_group_index_to_bti(bt
, IRIS_SURFACE_GROUP_TEXTURE
,
810 if (instr
->type
!= nir_instr_type_intrinsic
)
813 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
814 switch (intrin
->intrinsic
) {
815 case nir_intrinsic_image_size
:
816 case nir_intrinsic_image_load
:
817 case nir_intrinsic_image_store
:
818 case nir_intrinsic_image_atomic_add
:
819 case nir_intrinsic_image_atomic_min
:
820 case nir_intrinsic_image_atomic_max
:
821 case nir_intrinsic_image_atomic_and
:
822 case nir_intrinsic_image_atomic_or
:
823 case nir_intrinsic_image_atomic_xor
:
824 case nir_intrinsic_image_atomic_exchange
:
825 case nir_intrinsic_image_atomic_comp_swap
:
826 case nir_intrinsic_image_load_raw_intel
:
827 case nir_intrinsic_image_store_raw_intel
:
828 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
829 IRIS_SURFACE_GROUP_IMAGE
);
832 case nir_intrinsic_load_ubo
:
833 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
834 IRIS_SURFACE_GROUP_UBO
);
837 case nir_intrinsic_store_ssbo
:
838 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[1],
839 IRIS_SURFACE_GROUP_SSBO
);
842 case nir_intrinsic_load_output
:
843 if (devinfo
->gen
== 8) {
844 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
845 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
849 case nir_intrinsic_get_buffer_size
:
850 case nir_intrinsic_ssbo_atomic_add
:
851 case nir_intrinsic_ssbo_atomic_imin
:
852 case nir_intrinsic_ssbo_atomic_umin
:
853 case nir_intrinsic_ssbo_atomic_imax
:
854 case nir_intrinsic_ssbo_atomic_umax
:
855 case nir_intrinsic_ssbo_atomic_and
:
856 case nir_intrinsic_ssbo_atomic_or
:
857 case nir_intrinsic_ssbo_atomic_xor
:
858 case nir_intrinsic_ssbo_atomic_exchange
:
859 case nir_intrinsic_ssbo_atomic_comp_swap
:
860 case nir_intrinsic_ssbo_atomic_fmin
:
861 case nir_intrinsic_ssbo_atomic_fmax
:
862 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
863 case nir_intrinsic_load_ssbo
:
864 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
865 IRIS_SURFACE_GROUP_SSBO
);
876 iris_debug_recompile(struct iris_context
*ice
,
877 struct shader_info
*info
,
878 const struct brw_base_prog_key
*key
)
880 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
881 const struct brw_compiler
*c
= screen
->compiler
;
886 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
887 _mesa_shader_stage_to_string(info
->stage
),
888 info
->name
? info
->name
: "(no identifier)",
889 info
->label
? info
->label
: "");
891 const void *old_key
=
892 iris_find_previous_compile(ice
, info
->stage
, key
->program_string_id
);
894 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
898 * Get the shader for the last enabled geometry stage.
900 * This stage is the one which will feed stream output and the rasterizer.
902 static gl_shader_stage
903 last_vue_stage(struct iris_context
*ice
)
905 if (ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
906 return MESA_SHADER_GEOMETRY
;
908 if (ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
909 return MESA_SHADER_TESS_EVAL
;
911 return MESA_SHADER_VERTEX
;
915 * Compile a vertex shader, and upload the assembly.
917 static struct iris_compiled_shader
*
918 iris_compile_vs(struct iris_context
*ice
,
919 struct iris_uncompiled_shader
*ish
,
920 const struct brw_vs_prog_key
*key
)
922 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
923 const struct brw_compiler
*compiler
= screen
->compiler
;
924 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
925 void *mem_ctx
= ralloc_context(NULL
);
926 struct brw_vs_prog_data
*vs_prog_data
=
927 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
928 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
929 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
930 enum brw_param_builtin
*system_values
;
931 unsigned num_system_values
;
934 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
936 if (key
->nr_userclip_plane_consts
) {
937 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
938 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
939 nir_lower_io_to_temporaries(nir
, impl
, true, false);
940 nir_lower_global_vars_to_local(nir
);
941 nir_lower_vars_to_ssa(nir
);
942 nir_shader_gather_info(nir
, impl
);
945 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
947 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
948 &num_system_values
, &num_cbufs
);
950 struct iris_binding_table bt
;
951 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
952 num_system_values
, num_cbufs
);
954 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
956 brw_compute_vue_map(devinfo
,
957 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
958 nir
->info
.separate_shader
);
960 /* Don't tell the backend about our clip plane constants, we've already
961 * lowered them in NIR and we don't want it doing it again.
963 struct brw_vs_prog_key key_no_ucp
= *key
;
964 key_no_ucp
.nr_userclip_plane_consts
= 0;
966 char *error_str
= NULL
;
967 const unsigned *program
=
968 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
969 nir
, -1, NULL
, &error_str
);
970 if (program
== NULL
) {
971 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
972 ralloc_free(mem_ctx
);
976 if (ish
->compiled_once
) {
977 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
979 ish
->compiled_once
= true;
983 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
984 &vue_prog_data
->vue_map
);
986 struct iris_compiled_shader
*shader
=
987 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
988 prog_data
, so_decls
, system_values
, num_system_values
,
991 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
993 ralloc_free(mem_ctx
);
998 * Update the current vertex shader variant.
1000 * Fill out the key, look in the cache, compile and bind if needed.
1003 iris_update_compiled_vs(struct iris_context
*ice
)
1005 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1006 struct iris_uncompiled_shader
*ish
=
1007 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
1008 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1009 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1011 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1012 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1014 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
1015 struct iris_compiled_shader
*shader
=
1016 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
1019 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1022 shader
= iris_compile_vs(ice
, ish
, &key
);
1024 if (old
!= shader
) {
1025 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
1026 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
1027 IRIS_DIRTY_BINDINGS_VS
|
1028 IRIS_DIRTY_CONSTANTS_VS
|
1030 shs
->sysvals_need_upload
= true;
1032 const struct brw_vs_prog_data
*vs_prog_data
=
1033 (void *) shader
->prog_data
;
1034 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
1035 vs_prog_data
->uses_baseinstance
;
1036 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
1037 vs_prog_data
->uses_is_indexed_draw
;
1038 const bool needs_sgvs_element
= uses_draw_params
||
1039 vs_prog_data
->uses_instanceid
||
1040 vs_prog_data
->uses_vertexid
;
1041 bool needs_edge_flag
= false;
1042 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
1043 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
1044 needs_edge_flag
= true;
1047 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
1048 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
1049 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
1050 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
1051 IRIS_DIRTY_VERTEX_ELEMENTS
;
1053 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
1054 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
1055 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
1056 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
1061 * Get the shader_info for a given stage, or NULL if the stage is disabled.
1063 const struct shader_info
*
1064 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
1066 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
1071 const nir_shader
*nir
= ish
->nir
;
1076 * Get the union of TCS output and TES input slots.
1078 * TCS and TES need to agree on a common URB entry layout. In particular,
1079 * the data for all patch vertices is stored in a single URB entry (unlike
1080 * GS which has one entry per input vertex). This means that per-vertex
1081 * array indexing needs a stride.
1083 * SSO requires locations to match, but doesn't require the number of
1084 * outputs/inputs to match (in fact, the TCS often has extra outputs).
1085 * So, we need to take the extra step of unifying these on the fly.
1088 get_unified_tess_slots(const struct iris_context
*ice
,
1089 uint64_t *per_vertex_slots
,
1090 uint32_t *per_patch_slots
)
1092 const struct shader_info
*tcs
=
1093 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
1094 const struct shader_info
*tes
=
1095 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1097 *per_vertex_slots
= tes
->inputs_read
;
1098 *per_patch_slots
= tes
->patch_inputs_read
;
1101 *per_vertex_slots
|= tcs
->outputs_written
;
1102 *per_patch_slots
|= tcs
->patch_outputs_written
;
1107 * Compile a tessellation control shader, and upload the assembly.
1109 static struct iris_compiled_shader
*
1110 iris_compile_tcs(struct iris_context
*ice
,
1111 struct iris_uncompiled_shader
*ish
,
1112 const struct brw_tcs_prog_key
*key
)
1114 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1115 const struct brw_compiler
*compiler
= screen
->compiler
;
1116 const struct nir_shader_compiler_options
*options
=
1117 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
1118 void *mem_ctx
= ralloc_context(NULL
);
1119 struct brw_tcs_prog_data
*tcs_prog_data
=
1120 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
1121 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
1122 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1123 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1124 enum brw_param_builtin
*system_values
= NULL
;
1125 unsigned num_system_values
= 0;
1126 unsigned num_cbufs
= 0;
1130 struct iris_binding_table bt
;
1133 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1135 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1136 &num_system_values
, &num_cbufs
);
1137 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1138 num_system_values
, num_cbufs
);
1139 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1141 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
1143 /* Reserve space for passing the default tess levels as constants. */
1145 num_system_values
= 8;
1147 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
1148 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
1149 prog_data
->nr_params
= num_system_values
;
1151 if (key
->tes_primitive_mode
== GL_QUADS
) {
1152 for (int i
= 0; i
< 4; i
++)
1153 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1155 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1156 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
1157 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
1158 for (int i
= 0; i
< 3; i
++)
1159 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1161 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1163 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
1164 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
1165 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
1168 /* Manually setup the TCS binding table. */
1169 memset(&bt
, 0, sizeof(bt
));
1170 bt
.sizes
[IRIS_SURFACE_GROUP_UBO
] = 1;
1171 bt
.used_mask
[IRIS_SURFACE_GROUP_UBO
] = 1;
1174 prog_data
->ubo_ranges
[0].length
= 1;
1177 char *error_str
= NULL
;
1178 const unsigned *program
=
1179 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
1180 -1, NULL
, &error_str
);
1181 if (program
== NULL
) {
1182 dbg_printf("Failed to compile control shader: %s\n", error_str
);
1183 ralloc_free(mem_ctx
);
1188 if (ish
->compiled_once
) {
1189 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1191 ish
->compiled_once
= true;
1195 struct iris_compiled_shader
*shader
=
1196 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
1197 prog_data
, NULL
, system_values
, num_system_values
,
1201 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1203 ralloc_free(mem_ctx
);
1208 * Update the current tessellation control shader variant.
1210 * Fill out the key, look in the cache, compile and bind if needed.
1213 iris_update_compiled_tcs(struct iris_context
*ice
)
1215 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
1216 struct iris_uncompiled_shader
*tcs
=
1217 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
1218 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1219 const struct brw_compiler
*compiler
= screen
->compiler
;
1220 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1222 const struct shader_info
*tes_info
=
1223 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1224 struct brw_tcs_prog_key key
= {
1225 KEY_INIT_NO_ID(devinfo
->gen
),
1226 .base
.program_string_id
= tcs
? tcs
->program_id
: 0,
1227 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
1229 !tcs
|| compiler
->use_tcs_8_patch
? ice
->state
.vertices_per_patch
: 0,
1231 get_unified_tess_slots(ice
, &key
.outputs_written
,
1232 &key
.patch_outputs_written
);
1233 ice
->vtbl
.populate_tcs_key(ice
, &key
);
1235 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
1236 struct iris_compiled_shader
*shader
=
1237 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
1240 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
1243 shader
= iris_compile_tcs(ice
, tcs
, &key
);
1245 if (old
!= shader
) {
1246 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
1247 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
1248 IRIS_DIRTY_BINDINGS_TCS
|
1249 IRIS_DIRTY_CONSTANTS_TCS
;
1250 shs
->sysvals_need_upload
= true;
1255 * Compile a tessellation evaluation shader, and upload the assembly.
1257 static struct iris_compiled_shader
*
1258 iris_compile_tes(struct iris_context
*ice
,
1259 struct iris_uncompiled_shader
*ish
,
1260 const struct brw_tes_prog_key
*key
)
1262 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1263 const struct brw_compiler
*compiler
= screen
->compiler
;
1264 void *mem_ctx
= ralloc_context(NULL
);
1265 struct brw_tes_prog_data
*tes_prog_data
=
1266 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1267 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1268 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1269 enum brw_param_builtin
*system_values
;
1270 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1271 unsigned num_system_values
;
1274 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1276 if (key
->nr_userclip_plane_consts
) {
1277 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1278 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
1279 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1280 nir_lower_global_vars_to_local(nir
);
1281 nir_lower_vars_to_ssa(nir
);
1282 nir_shader_gather_info(nir
, impl
);
1285 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1286 &num_system_values
, &num_cbufs
);
1288 struct iris_binding_table bt
;
1289 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1290 num_system_values
, num_cbufs
);
1292 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1294 struct brw_vue_map input_vue_map
;
1295 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1296 key
->patch_inputs_read
);
1298 char *error_str
= NULL
;
1299 const unsigned *program
=
1300 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
1301 tes_prog_data
, nir
, NULL
, -1, NULL
, &error_str
);
1302 if (program
== NULL
) {
1303 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1304 ralloc_free(mem_ctx
);
1308 if (ish
->compiled_once
) {
1309 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1311 ish
->compiled_once
= true;
1314 uint32_t *so_decls
=
1315 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1316 &vue_prog_data
->vue_map
);
1319 struct iris_compiled_shader
*shader
=
1320 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1321 prog_data
, so_decls
, system_values
, num_system_values
,
1324 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1326 ralloc_free(mem_ctx
);
1331 * Update the current tessellation evaluation shader variant.
1333 * Fill out the key, look in the cache, compile and bind if needed.
1336 iris_update_compiled_tes(struct iris_context
*ice
)
1338 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
1339 struct iris_uncompiled_shader
*ish
=
1340 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1341 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1342 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1344 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1345 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1346 ice
->vtbl
.populate_tes_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1348 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1349 struct iris_compiled_shader
*shader
=
1350 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1353 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1356 shader
= iris_compile_tes(ice
, ish
, &key
);
1358 if (old
!= shader
) {
1359 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1360 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1361 IRIS_DIRTY_BINDINGS_TES
|
1362 IRIS_DIRTY_CONSTANTS_TES
;
1363 shs
->sysvals_need_upload
= true;
1366 /* TODO: Could compare and avoid flagging this. */
1367 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1368 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1369 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1370 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].sysvals_need_upload
= true;
1375 * Compile a geometry shader, and upload the assembly.
1377 static struct iris_compiled_shader
*
1378 iris_compile_gs(struct iris_context
*ice
,
1379 struct iris_uncompiled_shader
*ish
,
1380 const struct brw_gs_prog_key
*key
)
1382 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1383 const struct brw_compiler
*compiler
= screen
->compiler
;
1384 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1385 void *mem_ctx
= ralloc_context(NULL
);
1386 struct brw_gs_prog_data
*gs_prog_data
=
1387 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1388 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1389 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1390 enum brw_param_builtin
*system_values
;
1391 unsigned num_system_values
;
1394 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1396 if (key
->nr_userclip_plane_consts
) {
1397 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1398 nir_lower_clip_gs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1);
1399 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1400 nir_lower_global_vars_to_local(nir
);
1401 nir_lower_vars_to_ssa(nir
);
1402 nir_shader_gather_info(nir
, impl
);
1405 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1406 &num_system_values
, &num_cbufs
);
1408 struct iris_binding_table bt
;
1409 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1410 num_system_values
, num_cbufs
);
1412 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1414 brw_compute_vue_map(devinfo
,
1415 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1416 nir
->info
.separate_shader
);
1418 char *error_str
= NULL
;
1419 const unsigned *program
=
1420 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1421 NULL
, -1, NULL
, &error_str
);
1422 if (program
== NULL
) {
1423 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1424 ralloc_free(mem_ctx
);
1428 if (ish
->compiled_once
) {
1429 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1431 ish
->compiled_once
= true;
1434 uint32_t *so_decls
=
1435 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1436 &vue_prog_data
->vue_map
);
1438 struct iris_compiled_shader
*shader
=
1439 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1440 prog_data
, so_decls
, system_values
, num_system_values
,
1443 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1445 ralloc_free(mem_ctx
);
1450 * Update the current geometry shader variant.
1452 * Fill out the key, look in the cache, compile and bind if needed.
1455 iris_update_compiled_gs(struct iris_context
*ice
)
1457 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
1458 struct iris_uncompiled_shader
*ish
=
1459 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1460 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1461 struct iris_compiled_shader
*shader
= NULL
;
1464 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1465 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1466 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1467 ice
->vtbl
.populate_gs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1470 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1473 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1476 shader
= iris_compile_gs(ice
, ish
, &key
);
1479 if (old
!= shader
) {
1480 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1481 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1482 IRIS_DIRTY_BINDINGS_GS
|
1483 IRIS_DIRTY_CONSTANTS_GS
;
1484 shs
->sysvals_need_upload
= true;
1489 * Compile a fragment (pixel) shader, and upload the assembly.
1491 static struct iris_compiled_shader
*
1492 iris_compile_fs(struct iris_context
*ice
,
1493 struct iris_uncompiled_shader
*ish
,
1494 const struct brw_wm_prog_key
*key
,
1495 struct brw_vue_map
*vue_map
)
1497 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1498 const struct brw_compiler
*compiler
= screen
->compiler
;
1499 void *mem_ctx
= ralloc_context(NULL
);
1500 struct brw_wm_prog_data
*fs_prog_data
=
1501 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1502 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1503 enum brw_param_builtin
*system_values
;
1504 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1505 unsigned num_system_values
;
1508 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1510 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1512 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1513 &num_system_values
, &num_cbufs
);
1515 /* Lower output variables to load_output intrinsics before setting up
1516 * binding tables, so iris_setup_binding_table can map any load_output
1517 * intrinsics to IRIS_SURFACE_GROUP_RENDER_TARGET_READ on Gen8 for
1518 * non-coherent framebuffer fetches.
1520 brw_nir_lower_fs_outputs(nir
);
1522 struct iris_binding_table bt
;
1523 iris_setup_binding_table(devinfo
, nir
, &bt
, MAX2(key
->nr_color_regions
, 1),
1524 num_system_values
, num_cbufs
);
1526 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1528 char *error_str
= NULL
;
1529 const unsigned *program
=
1530 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1531 nir
, NULL
, -1, -1, -1, true, false, vue_map
,
1533 if (program
== NULL
) {
1534 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1535 ralloc_free(mem_ctx
);
1539 if (ish
->compiled_once
) {
1540 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1542 ish
->compiled_once
= true;
1545 struct iris_compiled_shader
*shader
=
1546 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1547 prog_data
, NULL
, system_values
, num_system_values
,
1550 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1552 ralloc_free(mem_ctx
);
1557 * Update the current fragment shader variant.
1559 * Fill out the key, look in the cache, compile and bind if needed.
1562 iris_update_compiled_fs(struct iris_context
*ice
)
1564 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_FRAGMENT
];
1565 struct iris_uncompiled_shader
*ish
=
1566 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1567 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1568 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1569 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1570 ice
->vtbl
.populate_fs_key(ice
, &ish
->nir
->info
, &key
);
1572 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1573 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1575 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1576 struct iris_compiled_shader
*shader
=
1577 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1580 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1583 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1585 if (old
!= shader
) {
1586 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1587 // toggles. might be able to avoid flagging SBE too.
1588 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1589 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1590 IRIS_DIRTY_BINDINGS_FS
|
1591 IRIS_DIRTY_CONSTANTS_FS
|
1595 shs
->sysvals_need_upload
= true;
1600 * Update the last enabled stage's VUE map.
1602 * When the shader feeding the rasterizer's output interface changes, we
1603 * need to re-emit various packets.
1606 update_last_vue_map(struct iris_context
*ice
,
1607 struct brw_stage_prog_data
*prog_data
)
1609 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1610 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1611 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1612 const uint64_t changed_slots
=
1613 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1615 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1616 ice
->state
.num_viewports
=
1617 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1618 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1619 IRIS_DIRTY_SF_CL_VIEWPORT
|
1620 IRIS_DIRTY_CC_VIEWPORT
|
1621 IRIS_DIRTY_SCISSOR_RECT
|
1622 IRIS_DIRTY_UNCOMPILED_FS
|
1623 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1626 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1627 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1630 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1634 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1636 static struct brw_vue_prog_data
*
1637 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1639 if (!ice
->shaders
.prog
[stage
])
1642 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1645 // XXX: iris_compiled_shaders are space-leaking :(
1646 // XXX: do remember to unbind them if deleting them.
1649 * Update the current shader variants for the given state.
1651 * This should be called on every draw call to ensure that the correct
1652 * shaders are bound. It will also flag any dirty state triggered by
1653 * swapping out those shaders.
1656 iris_update_compiled_shaders(struct iris_context
*ice
)
1658 const uint64_t dirty
= ice
->state
.dirty
;
1660 struct brw_vue_prog_data
*old_prog_datas
[4];
1661 if (!(dirty
& IRIS_DIRTY_URB
)) {
1662 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1663 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1666 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1667 struct iris_uncompiled_shader
*tes
=
1668 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1670 iris_update_compiled_tcs(ice
);
1671 iris_update_compiled_tes(ice
);
1673 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1674 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1676 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1677 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1678 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1682 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1683 iris_update_compiled_vs(ice
);
1684 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1685 iris_update_compiled_gs(ice
);
1687 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1688 const struct iris_compiled_shader
*gs
=
1689 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1690 const struct iris_compiled_shader
*tes
=
1691 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1693 bool points_or_lines
= false;
1696 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1698 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1699 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1701 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1703 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1704 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1707 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1708 /* Outbound to XY Clip enables */
1709 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1710 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1714 gl_shader_stage last_stage
= last_vue_stage(ice
);
1715 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1716 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1717 update_last_vue_map(ice
, shader
->prog_data
);
1718 if (ice
->state
.streamout
!= shader
->streamout
) {
1719 ice
->state
.streamout
= shader
->streamout
;
1720 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1723 if (ice
->state
.streamout_active
) {
1724 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1725 struct iris_stream_output_target
*so
=
1726 (void *) ice
->state
.so_target
[i
];
1728 so
->stride
= ish
->stream_output
.stride
[i
] * sizeof(uint32_t);
1732 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1733 iris_update_compiled_fs(ice
);
1735 /* Changing shader interfaces may require a URB configuration. */
1736 if (!(dirty
& IRIS_DIRTY_URB
)) {
1737 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1738 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1739 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1740 if (!!old
!= !!new ||
1741 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1742 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1749 static struct iris_compiled_shader
*
1750 iris_compile_cs(struct iris_context
*ice
,
1751 struct iris_uncompiled_shader
*ish
,
1752 const struct brw_cs_prog_key
*key
)
1754 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1755 const struct brw_compiler
*compiler
= screen
->compiler
;
1756 void *mem_ctx
= ralloc_context(NULL
);
1757 struct brw_cs_prog_data
*cs_prog_data
=
1758 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1759 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1760 enum brw_param_builtin
*system_values
;
1761 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1762 unsigned num_system_values
;
1765 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1767 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1768 &num_system_values
, &num_cbufs
);
1770 struct iris_binding_table bt
;
1771 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1772 num_system_values
, num_cbufs
);
1774 char *error_str
= NULL
;
1775 const unsigned *program
=
1776 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1777 nir
, -1, NULL
, &error_str
);
1778 if (program
== NULL
) {
1779 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1780 ralloc_free(mem_ctx
);
1784 if (ish
->compiled_once
) {
1785 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1787 ish
->compiled_once
= true;
1790 struct iris_compiled_shader
*shader
=
1791 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1792 prog_data
, NULL
, system_values
, num_system_values
,
1795 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1797 ralloc_free(mem_ctx
);
1802 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1804 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
1805 struct iris_uncompiled_shader
*ish
=
1806 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1808 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1809 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1810 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1811 ice
->vtbl
.populate_cs_key(ice
, &key
);
1813 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1814 struct iris_compiled_shader
*shader
=
1815 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1818 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1821 shader
= iris_compile_cs(ice
, ish
, &key
);
1823 if (old
!= shader
) {
1824 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1825 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1826 IRIS_DIRTY_BINDINGS_CS
|
1827 IRIS_DIRTY_CONSTANTS_CS
;
1828 shs
->sysvals_need_upload
= true;
1833 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1836 assert(cs_prog_data
->push
.total
.size
> 0);
1837 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1838 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1839 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1840 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1845 * Allocate scratch BOs as needed for the given per-thread size and stage.
1848 iris_get_scratch_space(struct iris_context
*ice
,
1849 unsigned per_thread_scratch
,
1850 gl_shader_stage stage
)
1852 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1853 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1854 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1856 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1857 assert(encoded_size
< (1 << 16));
1859 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1861 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1863 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1864 * must allocate scratch space enough so that each slice has 4
1867 * According to the other driver team, this applies to compute shaders
1868 * as well. This is not currently documented at all.
1870 * This hack is no longer necessary on Gen11+.
1872 unsigned subslice_total
= screen
->subslice_total
;
1873 if (devinfo
->gen
< 11)
1874 subslice_total
= 4 * devinfo
->num_slices
;
1875 assert(subslice_total
>= screen
->subslice_total
);
1878 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1879 uint32_t max_threads
[] = {
1880 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1881 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1882 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1883 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1884 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1885 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1888 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1890 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1896 /* ------------------------------------------------------------------- */
1899 * The pipe->create_[stage]_state() driver hooks.
1901 * Performs basic NIR preprocessing, records any state dependencies, and
1902 * returns an iris_uncompiled_shader as the Gallium CSO.
1904 * Actual shader compilation to assembly happens later, at first use.
1907 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1909 const struct pipe_stream_output_info
*so_info
)
1911 struct iris_context
*ice
= (void *)ctx
;
1912 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1913 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1915 struct iris_uncompiled_shader
*ish
=
1916 calloc(1, sizeof(struct iris_uncompiled_shader
));
1920 brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1922 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1923 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1927 if (nir
->constant_data_size
> 0) {
1928 unsigned data_offset
;
1929 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
1930 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
1932 struct pipe_shader_buffer psb
= {
1933 .buffer
= ish
->const_data
,
1934 .buffer_offset
= data_offset
,
1935 .buffer_size
= nir
->constant_data_size
,
1937 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
1940 ish
->program_id
= get_new_program_id(screen
);
1943 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1944 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1947 /* Save this now before potentially dropping nir->info.name */
1948 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1949 ish
->use_alt_mode
= true;
1951 if (screen
->disk_cache
) {
1952 /* Serialize the NIR to a binary blob that we can hash for the disk
1953 * cache. First, drop unnecessary information (like variable names)
1954 * so the serialized NIR is smaller, and also to let us detect more
1955 * isomorphic shaders when hashing, increasing cache hits. We clone
1956 * the NIR before stripping away this info because it can be useful
1957 * when inspecting and debugging shaders.
1959 nir_shader
*clone
= nir_shader_clone(NULL
, nir
);
1964 nir_serialize(&blob
, clone
);
1965 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
1974 static struct iris_uncompiled_shader
*
1975 iris_create_shader_state(struct pipe_context
*ctx
,
1976 const struct pipe_shader_state
*state
)
1978 struct nir_shader
*nir
;
1980 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1981 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1983 nir
= state
->ir
.nir
;
1985 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1989 iris_create_vs_state(struct pipe_context
*ctx
,
1990 const struct pipe_shader_state
*state
)
1992 struct iris_context
*ice
= (void *) ctx
;
1993 struct iris_screen
*screen
= (void *) ctx
->screen
;
1994 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1996 /* User clip planes */
1997 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1998 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2000 if (screen
->precompile
) {
2001 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2002 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2004 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2005 iris_compile_vs(ice
, ish
, &key
);
2012 iris_create_tcs_state(struct pipe_context
*ctx
,
2013 const struct pipe_shader_state
*state
)
2015 struct iris_context
*ice
= (void *) ctx
;
2016 struct iris_screen
*screen
= (void *) ctx
->screen
;
2017 const struct brw_compiler
*compiler
= screen
->compiler
;
2018 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2019 struct shader_info
*info
= &ish
->nir
->info
;
2021 if (screen
->precompile
) {
2022 const unsigned _GL_TRIANGLES
= 0x0004;
2023 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2024 struct brw_tcs_prog_key key
= {
2025 KEY_INIT(devinfo
->gen
),
2026 // XXX: make sure the linker fills this out from the TES...
2027 .tes_primitive_mode
=
2028 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
2030 .outputs_written
= info
->outputs_written
,
2031 .patch_outputs_written
= info
->patch_outputs_written
,
2034 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
2035 * We don't have that information, so we randomly guess that the input
2036 * and output patches are the same size. This is a bad guess, but we
2037 * can't do much better.
2039 if (compiler
->use_tcs_8_patch
)
2040 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
2042 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2043 iris_compile_tcs(ice
, ish
, &key
);
2050 iris_create_tes_state(struct pipe_context
*ctx
,
2051 const struct pipe_shader_state
*state
)
2053 struct iris_context
*ice
= (void *) ctx
;
2054 struct iris_screen
*screen
= (void *) ctx
->screen
;
2055 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2056 struct shader_info
*info
= &ish
->nir
->info
;
2058 /* User clip planes */
2059 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2060 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2062 if (screen
->precompile
) {
2063 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2064 struct brw_tes_prog_key key
= {
2065 KEY_INIT(devinfo
->gen
),
2066 // XXX: not ideal, need TCS output/TES input unification
2067 .inputs_read
= info
->inputs_read
,
2068 .patch_inputs_read
= info
->patch_inputs_read
,
2071 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2072 iris_compile_tes(ice
, ish
, &key
);
2079 iris_create_gs_state(struct pipe_context
*ctx
,
2080 const struct pipe_shader_state
*state
)
2082 struct iris_context
*ice
= (void *) ctx
;
2083 struct iris_screen
*screen
= (void *) ctx
->screen
;
2084 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2086 /* User clip planes */
2087 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2088 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2090 if (screen
->precompile
) {
2091 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2092 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2094 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2095 iris_compile_gs(ice
, ish
, &key
);
2102 iris_create_fs_state(struct pipe_context
*ctx
,
2103 const struct pipe_shader_state
*state
)
2105 struct iris_context
*ice
= (void *) ctx
;
2106 struct iris_screen
*screen
= (void *) ctx
->screen
;
2107 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2108 struct shader_info
*info
= &ish
->nir
->info
;
2110 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
2111 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
2112 (1ull << IRIS_NOS_RASTERIZER
) |
2113 (1ull << IRIS_NOS_BLEND
);
2115 /* The program key needs the VUE map if there are > 16 inputs */
2116 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
2117 BRW_FS_VARYING_INPUT_MASK
) > 16) {
2118 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
2121 if (screen
->precompile
) {
2122 const uint64_t color_outputs
= info
->outputs_written
&
2123 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
2124 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
2125 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
2127 bool can_rearrange_varyings
=
2128 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
2130 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2131 struct brw_wm_prog_key key
= {
2132 KEY_INIT(devinfo
->gen
),
2133 .nr_color_regions
= util_bitcount(color_outputs
),
2134 .coherent_fb_fetch
= true,
2135 .input_slots_valid
=
2136 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
2139 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2140 iris_compile_fs(ice
, ish
, &key
, NULL
);
2147 iris_create_compute_state(struct pipe_context
*ctx
,
2148 const struct pipe_compute_state
*state
)
2150 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
2152 struct iris_context
*ice
= (void *) ctx
;
2153 struct iris_screen
*screen
= (void *) ctx
->screen
;
2154 struct iris_uncompiled_shader
*ish
=
2155 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
2157 // XXX: disallow more than 64KB of shared variables
2159 if (screen
->precompile
) {
2160 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2161 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2163 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2164 iris_compile_cs(ice
, ish
, &key
);
2171 * The pipe->delete_[stage]_state() driver hooks.
2173 * Frees the iris_uncompiled_shader.
2176 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
2178 struct iris_uncompiled_shader
*ish
= state
;
2179 struct iris_context
*ice
= (void *) ctx
;
2181 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
2182 ice
->shaders
.uncompiled
[stage
] = NULL
;
2183 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2186 if (ish
->const_data
) {
2187 pipe_resource_reference(&ish
->const_data
, NULL
);
2188 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
2191 ralloc_free(ish
->nir
);
2196 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
2198 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
2202 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
2204 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
2208 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
2210 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
2214 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
2216 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
2220 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
2222 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
2226 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
2228 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
2232 * The pipe->bind_[stage]_state() driver hook.
2234 * Binds an uncompiled shader as the current one for a particular stage.
2235 * Updates dirty tracking to account for the shader's NOS.
2238 bind_shader_state(struct iris_context
*ice
,
2239 struct iris_uncompiled_shader
*ish
,
2240 gl_shader_stage stage
)
2242 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2243 const uint64_t nos
= ish
? ish
->nos
: 0;
2245 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
2246 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
2248 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
2249 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
2250 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
2253 ice
->shaders
.uncompiled
[stage
] = ish
;
2254 ice
->state
.dirty
|= dirty_bit
;
2256 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
2257 * (or that they no longer need to do so).
2259 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
2261 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
2263 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
2268 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
2270 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2271 struct iris_uncompiled_shader
*new_ish
= state
;
2274 ice
->state
.window_space_position
!=
2275 new_ish
->nir
->info
.vs
.window_space_position
) {
2276 ice
->state
.window_space_position
=
2277 new_ish
->nir
->info
.vs
.window_space_position
;
2279 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
2281 IRIS_DIRTY_CC_VIEWPORT
;
2284 bind_shader_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
2288 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
2290 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
2294 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
2296 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2298 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2299 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
2300 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2302 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
2306 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
2308 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2310 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2311 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
2312 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2314 bind_shader_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
2318 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
2320 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2321 struct iris_uncompiled_shader
*old_ish
=
2322 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2323 struct iris_uncompiled_shader
*new_ish
= state
;
2325 const unsigned color_bits
=
2326 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
2327 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
2329 /* Fragment shader outputs influence HasWriteableRT */
2330 if (!old_ish
|| !new_ish
||
2331 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
2332 (new_ish
->nir
->info
.outputs_written
& color_bits
))
2333 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
2335 bind_shader_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
2339 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
2341 bind_shader_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
2345 iris_init_program_functions(struct pipe_context
*ctx
)
2347 ctx
->create_vs_state
= iris_create_vs_state
;
2348 ctx
->create_tcs_state
= iris_create_tcs_state
;
2349 ctx
->create_tes_state
= iris_create_tes_state
;
2350 ctx
->create_gs_state
= iris_create_gs_state
;
2351 ctx
->create_fs_state
= iris_create_fs_state
;
2352 ctx
->create_compute_state
= iris_create_compute_state
;
2354 ctx
->delete_vs_state
= iris_delete_vs_state
;
2355 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
2356 ctx
->delete_tes_state
= iris_delete_tes_state
;
2357 ctx
->delete_gs_state
= iris_delete_gs_state
;
2358 ctx
->delete_fs_state
= iris_delete_fs_state
;
2359 ctx
->delete_compute_state
= iris_delete_cs_state
;
2361 ctx
->bind_vs_state
= iris_bind_vs_state
;
2362 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2363 ctx
->bind_tes_state
= iris_bind_tes_state
;
2364 ctx
->bind_gs_state
= iris_bind_gs_state
;
2365 ctx
->bind_fs_state
= iris_bind_fs_state
;
2366 ctx
->bind_compute_state
= iris_bind_cs_state
;