2 * Copyright © 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
46 get_new_program_id(struct iris_screen
*screen
)
48 return p_atomic_inc_return(&screen
->program_id
);
52 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
53 * It primarily contains the NIR for the shader.
55 * Each API-facing shader can be compiled into multiple shader variants,
56 * based on non-orthogonal state dependencies, recorded in the shader key.
58 * See iris_compiled_shader, which represents a compiled shader variant.
60 struct iris_uncompiled_shader
{
63 struct pipe_stream_output_info stream_output
;
67 /** Bitfield of (1 << IRIS_NOS_*) flags. */
72 get_aoa_deref_offset(nir_builder
*b
,
73 nir_deref_instr
*deref
,
76 unsigned array_size
= elem_size
;
77 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
79 while (deref
->deref_type
!= nir_deref_type_var
) {
80 assert(deref
->deref_type
== nir_deref_type_array
);
82 /* This level's element size is the previous level's array size */
83 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
84 assert(deref
->arr
.index
.ssa
);
85 offset
= nir_iadd(b
, offset
,
86 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
88 deref
= nir_deref_instr_parent(deref
);
89 assert(glsl_type_is_array(deref
->type
));
90 array_size
*= glsl_get_length(deref
->type
);
93 /* Accessing an invalid surface index with the dataport can result in a
94 * hang. According to the spec "if the index used to select an individual
95 * element is negative or greater than or equal to the size of the array,
96 * the results of the operation are undefined but may not lead to
97 * termination" -- which is one of the possible outcomes of the hang.
98 * Clamp the index to prevent access outside of the array bounds.
100 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
104 iris_lower_storage_image_derefs(nir_shader
*nir
)
106 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
109 nir_builder_init(&b
, impl
);
111 nir_foreach_block(block
, impl
) {
112 nir_foreach_instr_safe(instr
, block
) {
113 if (instr
->type
!= nir_instr_type_intrinsic
)
116 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
117 switch (intrin
->intrinsic
) {
118 case nir_intrinsic_image_deref_load
:
119 case nir_intrinsic_image_deref_store
:
120 case nir_intrinsic_image_deref_atomic_add
:
121 case nir_intrinsic_image_deref_atomic_min
:
122 case nir_intrinsic_image_deref_atomic_max
:
123 case nir_intrinsic_image_deref_atomic_and
:
124 case nir_intrinsic_image_deref_atomic_or
:
125 case nir_intrinsic_image_deref_atomic_xor
:
126 case nir_intrinsic_image_deref_atomic_exchange
:
127 case nir_intrinsic_image_deref_atomic_comp_swap
:
128 case nir_intrinsic_image_deref_size
:
129 case nir_intrinsic_image_deref_samples
: {
130 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
131 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
133 b
.cursor
= nir_before_instr(&intrin
->instr
);
135 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
136 get_aoa_deref_offset(&b
, deref
, 1));
137 brw_nir_rewrite_image_intrinsic(intrin
, index
);
150 // XXX: need unify_interfaces() at link time...
153 * The pipe->create_[stage]_state() driver hooks.
155 * Performs basic NIR preprocessing, records any state dependencies, and
156 * returns an iris_uncompiled_shader as the Gallium CSO.
158 * Actual shader compilation to assembly happens later, at first use.
161 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
163 const struct pipe_stream_output_info
*so_info
)
165 //struct iris_context *ice = (struct iris_context *)ctx;
166 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 struct iris_uncompiled_shader
*ish
=
170 calloc(1, sizeof(struct iris_uncompiled_shader
));
174 nir
= brw_preprocess_nir(screen
->compiler
, nir
);
176 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
177 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
179 ish
->program_id
= get_new_program_id(screen
);
182 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
184 switch (nir
->info
.stage
) {
185 case MESA_SHADER_VERTEX
:
188 case MESA_SHADER_TESS_CTRL
:
191 case MESA_SHADER_TESS_EVAL
:
194 case MESA_SHADER_GEOMETRY
:
197 case MESA_SHADER_FRAGMENT
:
198 ish
->nos
|= IRIS_NOS_FRAMEBUFFER
|
199 IRIS_NOS_DEPTH_STENCIL_ALPHA
|
200 IRIS_NOS_RASTERIZER
|
203 /* The program key needs the VUE map if there are > 16 inputs */
204 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
205 BRW_FS_VARYING_INPUT_MASK
) > 16) {
206 ish
->nos
|= IRIS_NOS_LAST_VUE_MAP
;
209 case MESA_SHADER_COMPUTE
:
217 // XXX: disallow more than 64KB of shared variables
223 * The pipe->delete_[stage]_state() driver hooks.
225 * Frees the iris_uncompiled_shader.
228 iris_create_shader_state(struct pipe_context
*ctx
,
229 const struct pipe_shader_state
*state
)
231 assert(state
->type
== PIPE_SHADER_IR_NIR
);
233 return iris_create_uncompiled_shader(ctx
, state
->ir
.nir
,
234 &state
->stream_output
);
238 iris_create_compute_state(struct pipe_context
*ctx
,
239 const struct pipe_compute_state
*state
)
241 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
243 return iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
247 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
249 struct iris_uncompiled_shader
*ish
= state
;
251 ralloc_free(ish
->nir
);
256 * The pipe->bind_[stage]_state() driver hook.
258 * Binds an uncompiled shader as the current one for a particular stage.
259 * Updates dirty tracking to account for the shader's NOS.
262 bind_state(struct iris_context
*ice
,
263 struct iris_uncompiled_shader
*ish
,
264 gl_shader_stage stage
)
266 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
267 const uint64_t nos
= ish
? ish
->nos
: 0;
269 ice
->shaders
.uncompiled
[stage
] = ish
;
270 ice
->state
.dirty
|= dirty_bit
;
272 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
273 * (or that they no longer need to do so).
275 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
277 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
279 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
284 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
286 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
290 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
292 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
296 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
298 struct iris_context
*ice
= (struct iris_context
*)ctx
;
300 /* Enabling/disabling optional stages requires a URB reconfiguration. */
301 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
302 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
304 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
308 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
310 struct iris_context
*ice
= (struct iris_context
*)ctx
;
312 /* Enabling/disabling optional stages requires a URB reconfiguration. */
313 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
314 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
316 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
320 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
322 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
326 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
328 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
332 * Sets up the starting offsets for the groups of binding table entries
333 * common to all pipeline stages.
335 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
336 * unused but also make sure that addition of small offsets to them will
337 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
340 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
341 const struct nir_shader
*nir
,
342 struct brw_stage_prog_data
*prog_data
,
343 uint32_t next_binding_table_offset
)
345 const struct shader_info
*info
= &nir
->info
;
347 if (info
->num_textures
) {
348 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
349 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
350 next_binding_table_offset
+= info
->num_textures
;
352 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
353 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
356 if (info
->num_images
) {
357 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
358 next_binding_table_offset
+= info
->num_images
;
360 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
363 int num_ubos
= info
->num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
366 //assert(info->num_ubos <= BRW_MAX_UBO);
367 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
368 next_binding_table_offset
+= num_ubos
;
370 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
373 if (info
->num_ssbos
|| info
->num_abos
) {
374 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
375 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
376 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
378 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
381 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
383 /* This may or may not be used depending on how the compile goes. */
384 prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
385 next_binding_table_offset
++;
387 /* Plane 0 is just the regular texture section */
388 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
390 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
391 next_binding_table_offset
+= info
->num_textures
;
393 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
394 next_binding_table_offset
+= info
->num_textures
;
396 /* Set the binding table size */
397 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
399 return next_binding_table_offset
;
403 * Associate NIR uniform variables with the prog_data->param[] mechanism
404 * used by the backend. Also, decide which UBOs we'd like to push in an
405 * ideal situation (though the backend can reduce this).
408 iris_setup_uniforms(const struct brw_compiler
*compiler
,
411 struct brw_stage_prog_data
*prog_data
)
413 prog_data
->nr_params
= nir
->num_uniforms
;
414 /* The intel compiler assumes that num_uniforms is in bytes. For
415 * scalar that means 4 bytes per uniform slot.
417 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
419 nir
->num_uniforms
*= 4;
420 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
422 nir_foreach_variable(var
, &nir
->uniforms
) {
423 const unsigned components
= glsl_get_components(var
->type
);
425 for (unsigned i
= 0; i
< components
; i
++) {
426 prog_data
->param
[var
->data
.driver_location
] =
427 var
->data
.driver_location
;
431 // XXX: vs clip planes?
432 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
433 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
437 * If we still have regular uniforms as push constants after the backend
438 * compilation, set up a UBO range for them. This will be used to fill
439 * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
442 iris_setup_push_uniform_range(const struct brw_compiler
*compiler
,
443 struct brw_stage_prog_data
*prog_data
)
445 if (prog_data
->nr_params
) {
446 for (int i
= 3; i
> 0; i
--)
447 prog_data
->ubo_ranges
[i
] = prog_data
->ubo_ranges
[i
- 1];
449 prog_data
->ubo_ranges
[0] = (struct brw_ubo_range
) {
452 .length
= DIV_ROUND_UP(prog_data
->nr_params
, 8),
458 * Compile a vertex shader, and upload the assembly.
461 iris_compile_vs(struct iris_context
*ice
,
462 struct iris_uncompiled_shader
*ish
,
463 const struct brw_vs_prog_key
*key
)
465 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
466 const struct brw_compiler
*compiler
= screen
->compiler
;
467 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
468 void *mem_ctx
= ralloc_context(NULL
);
469 struct brw_vs_prog_data
*vs_prog_data
=
470 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
471 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
472 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
474 nir_shader
*nir
= ish
->nir
;
477 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
479 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
481 brw_compute_vue_map(devinfo
,
482 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
483 nir
->info
.separate_shader
);
485 char *error_str
= NULL
;
486 const unsigned *program
=
487 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, key
, vs_prog_data
,
488 nir
, -1, &error_str
);
489 if (program
== NULL
) {
490 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
491 ralloc_free(mem_ctx
);
495 iris_setup_push_uniform_range(compiler
, prog_data
);
498 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
499 &vue_prog_data
->vue_map
);
501 iris_upload_and_bind_shader(ice
, IRIS_CACHE_VS
, key
, program
, prog_data
,
504 ralloc_free(mem_ctx
);
509 * Update the current vertex shader variant.
511 * Fill out the key, look in the cache, compile and bind if needed.
514 iris_update_compiled_vs(struct iris_context
*ice
)
516 struct iris_uncompiled_shader
*ish
=
517 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
519 struct brw_vs_prog_key key
= { .program_string_id
= ish
->program_id
};
520 ice
->vtbl
.populate_vs_key(ice
, &key
);
522 if (iris_bind_cached_shader(ice
, IRIS_CACHE_VS
, &key
))
525 UNUSED
bool success
= iris_compile_vs(ice
, ish
, &key
);
529 * Get the shader_info for a given stage, or NULL if the stage is disabled.
531 const struct shader_info
*
532 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
534 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
539 const nir_shader
*nir
= ish
->nir
;
543 // XXX: this function is gross
545 iris_get_shader_num_ubos(const struct iris_context
*ice
, gl_shader_stage stage
)
547 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
550 const nir_shader
*nir
= ish
->nir
;
551 /* see assign_common_binding_table_offsets */
552 return nir
->info
.num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
558 * Get the union of TCS output and TES input slots.
560 * TCS and TES need to agree on a common URB entry layout. In particular,
561 * the data for all patch vertices is stored in a single URB entry (unlike
562 * GS which has one entry per input vertex). This means that per-vertex
563 * array indexing needs a stride.
565 * SSO requires locations to match, but doesn't require the number of
566 * outputs/inputs to match (in fact, the TCS often has extra outputs).
567 * So, we need to take the extra step of unifying these on the fly.
570 get_unified_tess_slots(const struct iris_context
*ice
,
571 uint64_t *per_vertex_slots
,
572 uint32_t *per_patch_slots
)
574 const struct shader_info
*tcs
=
575 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
576 const struct shader_info
*tes
=
577 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
579 *per_vertex_slots
= tes
->inputs_read
;
580 *per_patch_slots
= tes
->patch_inputs_read
;
583 *per_vertex_slots
|= tcs
->inputs_read
;
584 *per_patch_slots
|= tcs
->patch_inputs_read
;
589 * Compile a tessellation control shader, and upload the assembly.
592 iris_compile_tcs(struct iris_context
*ice
,
593 struct iris_uncompiled_shader
*ish
,
594 const struct brw_tcs_prog_key
*key
)
596 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
597 const struct brw_compiler
*compiler
= screen
->compiler
;
598 const struct nir_shader_compiler_options
*options
=
599 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
600 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
601 void *mem_ctx
= ralloc_context(NULL
);
602 struct brw_tcs_prog_data
*tcs_prog_data
=
603 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
604 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
605 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
612 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
613 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
615 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
617 /* Reserve space for passing the default tess levels as constants. */
618 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
619 prog_data
->nr_params
= 8;
620 prog_data
->ubo_ranges
[0].length
= 1;
623 char *error_str
= NULL
;
624 const unsigned *program
=
625 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
627 if (program
== NULL
) {
628 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
629 ralloc_free(mem_ctx
);
633 iris_setup_push_uniform_range(compiler
, prog_data
);
635 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TCS
, key
, program
, prog_data
,
638 ralloc_free(mem_ctx
);
643 * Update the current tessellation control shader variant.
645 * Fill out the key, look in the cache, compile and bind if needed.
648 iris_update_compiled_tcs(struct iris_context
*ice
)
650 struct iris_uncompiled_shader
*tcs
=
651 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
653 const struct shader_info
*tes_info
=
654 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
655 struct brw_tcs_prog_key key
= {
656 .program_string_id
= tcs
? tcs
->program_id
: 0,
657 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
658 .input_vertices
= ice
->state
.vertices_per_patch
,
660 get_unified_tess_slots(ice
, &key
.outputs_written
,
661 &key
.patch_outputs_written
);
662 ice
->vtbl
.populate_tcs_key(ice
, &key
);
664 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TCS
, &key
))
667 UNUSED
bool success
= iris_compile_tcs(ice
, tcs
, &key
);
671 * Compile a tessellation evaluation shader, and upload the assembly.
674 iris_compile_tes(struct iris_context
*ice
,
675 struct iris_uncompiled_shader
*ish
,
676 const struct brw_tes_prog_key
*key
)
678 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
679 const struct brw_compiler
*compiler
= screen
->compiler
;
680 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
681 void *mem_ctx
= ralloc_context(NULL
);
682 struct brw_tes_prog_data
*tes_prog_data
=
683 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
684 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
685 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
687 nir_shader
*nir
= ish
->nir
;
689 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
691 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
693 struct brw_vue_map input_vue_map
;
694 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
695 key
->patch_inputs_read
);
697 char *error_str
= NULL
;
698 const unsigned *program
=
699 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
700 tes_prog_data
, nir
, NULL
, -1, &error_str
);
701 if (program
== NULL
) {
702 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
703 ralloc_free(mem_ctx
);
707 iris_setup_push_uniform_range(compiler
, prog_data
);
710 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
711 &vue_prog_data
->vue_map
);
713 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TES
, key
, program
, prog_data
,
716 ralloc_free(mem_ctx
);
721 * Update the current tessellation evaluation shader variant.
723 * Fill out the key, look in the cache, compile and bind if needed.
726 iris_update_compiled_tes(struct iris_context
*ice
)
728 struct iris_uncompiled_shader
*ish
=
729 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
731 struct brw_tes_prog_key key
= { .program_string_id
= ish
->program_id
};
732 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
733 ice
->vtbl
.populate_tes_key(ice
, &key
);
735 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TES
, &key
))
738 UNUSED
bool success
= iris_compile_tes(ice
, ish
, &key
);
742 * Compile a geometry shader, and upload the assembly.
745 iris_compile_gs(struct iris_context
*ice
,
746 struct iris_uncompiled_shader
*ish
,
747 const struct brw_gs_prog_key
*key
)
749 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
750 const struct brw_compiler
*compiler
= screen
->compiler
;
751 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
752 void *mem_ctx
= ralloc_context(NULL
);
753 struct brw_gs_prog_data
*gs_prog_data
=
754 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
755 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
756 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
758 nir_shader
*nir
= ish
->nir
;
760 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
762 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
764 brw_compute_vue_map(devinfo
,
765 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
766 nir
->info
.separate_shader
);
768 char *error_str
= NULL
;
769 const unsigned *program
=
770 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
771 NULL
, -1, &error_str
);
772 if (program
== NULL
) {
773 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
774 ralloc_free(mem_ctx
);
778 iris_setup_push_uniform_range(compiler
, prog_data
);
781 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
782 &vue_prog_data
->vue_map
);
784 iris_upload_and_bind_shader(ice
, IRIS_CACHE_GS
, key
, program
, prog_data
,
787 ralloc_free(mem_ctx
);
792 * Update the current geometry shader variant.
794 * Fill out the key, look in the cache, compile and bind if needed.
797 iris_update_compiled_gs(struct iris_context
*ice
)
799 struct iris_uncompiled_shader
*ish
=
800 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
803 iris_unbind_shader(ice
, IRIS_CACHE_GS
);
807 struct brw_gs_prog_key key
= { .program_string_id
= ish
->program_id
};
808 ice
->vtbl
.populate_gs_key(ice
, &key
);
810 if (iris_bind_cached_shader(ice
, IRIS_CACHE_GS
, &key
))
813 UNUSED
bool success
= iris_compile_gs(ice
, ish
, &key
);
817 * Compile a fragment (pixel) shader, and upload the assembly.
820 iris_compile_fs(struct iris_context
*ice
,
821 struct iris_uncompiled_shader
*ish
,
822 const struct brw_wm_prog_key
*key
,
823 struct brw_vue_map
*vue_map
)
825 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
826 const struct brw_compiler
*compiler
= screen
->compiler
;
827 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
828 void *mem_ctx
= ralloc_context(NULL
);
829 struct brw_wm_prog_data
*fs_prog_data
=
830 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
831 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
833 nir_shader
*nir
= ish
->nir
;
836 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
837 MAX2(key
->nr_color_regions
, 1));
839 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
841 char *error_str
= NULL
;
842 const unsigned *program
=
843 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
844 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
845 if (program
== NULL
) {
846 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
847 ralloc_free(mem_ctx
);
851 //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
853 iris_setup_push_uniform_range(compiler
, prog_data
);
855 iris_upload_and_bind_shader(ice
, IRIS_CACHE_FS
, key
, program
, prog_data
,
858 ralloc_free(mem_ctx
);
863 * Update the current fragment shader variant.
865 * Fill out the key, look in the cache, compile and bind if needed.
868 iris_update_compiled_fs(struct iris_context
*ice
)
870 struct iris_uncompiled_shader
*ish
=
871 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
872 struct brw_wm_prog_key key
= { .program_string_id
= ish
->program_id
};
873 ice
->vtbl
.populate_fs_key(ice
, &key
);
875 if (ish
->nos
& IRIS_NOS_LAST_VUE_MAP
)
876 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
878 if (iris_bind_cached_shader(ice
, IRIS_CACHE_FS
, &key
))
881 UNUSED
bool success
=
882 iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
886 * Get the compiled shader for the last enabled geometry stage.
888 * This stage is the one which will feed stream output and the rasterizer.
890 static struct iris_compiled_shader
*
891 last_vue_shader(struct iris_context
*ice
)
893 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
894 return ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
896 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
897 return ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
899 return ice
->shaders
.prog
[MESA_SHADER_VERTEX
];
903 * Update the last enabled stage's VUE map.
905 * When the shader feeding the rasterizer's output interface changes, we
906 * need to re-emit various packets.
909 update_last_vue_map(struct iris_context
*ice
,
910 struct brw_stage_prog_data
*prog_data
)
912 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
913 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
914 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
915 const uint64_t changed_slots
=
916 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
918 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
919 // XXX: could use ctx->Const.MaxViewports for old API efficiency
920 ice
->state
.num_viewports
=
921 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
922 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
923 IRIS_DIRTY_SF_CL_VIEWPORT
|
924 IRIS_DIRTY_CC_VIEWPORT
|
925 IRIS_DIRTY_SCISSOR_RECT
|
926 IRIS_DIRTY_UNCOMPILED_FS
|
927 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
931 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
932 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
935 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
939 * Get the prog_data for a given stage, or NULL if the stage is disabled.
941 static struct brw_vue_prog_data
*
942 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
944 if (!ice
->shaders
.prog
[stage
])
947 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
951 * Update the current shader variants for the given state.
953 * This should be called on every draw call to ensure that the correct
954 * shaders are bound. It will also flag any dirty state triggered by
955 * swapping out those shaders.
958 iris_update_compiled_shaders(struct iris_context
*ice
)
960 const uint64_t dirty
= ice
->state
.dirty
;
962 struct brw_vue_prog_data
*old_prog_datas
[4];
963 if (!(dirty
& IRIS_DIRTY_URB
)) {
964 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
965 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
968 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
969 struct iris_uncompiled_shader
*tes
=
970 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
972 iris_update_compiled_tcs(ice
);
973 iris_update_compiled_tes(ice
);
975 iris_unbind_shader(ice
, IRIS_CACHE_TCS
);
976 iris_unbind_shader(ice
, IRIS_CACHE_TES
);
980 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
981 iris_update_compiled_vs(ice
);
982 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
983 iris_update_compiled_gs(ice
);
985 struct iris_compiled_shader
*shader
= last_vue_shader(ice
);
986 update_last_vue_map(ice
, shader
->prog_data
);
987 if (ice
->state
.streamout
!= shader
->streamout
) {
988 ice
->state
.streamout
= shader
->streamout
;
989 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
992 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
993 iris_update_compiled_fs(ice
);
996 /* Changing shader interfaces may require a URB configuration. */
997 if (!(dirty
& IRIS_DIRTY_URB
)) {
998 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
999 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1000 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1001 if (!!old
!= !!new ||
1002 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1003 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1011 iris_compile_cs(struct iris_context
*ice
,
1012 struct iris_uncompiled_shader
*ish
,
1013 const struct brw_cs_prog_key
*key
)
1015 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1016 const struct brw_compiler
*compiler
= screen
->compiler
;
1017 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1018 void *mem_ctx
= ralloc_context(NULL
);
1019 struct brw_cs_prog_data
*cs_prog_data
=
1020 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1021 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1023 nir_shader
*nir
= ish
->nir
;
1025 cs_prog_data
->binding_table
.work_groups_start
= 0;
1026 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1);
1028 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
1030 char *error_str
= NULL
;
1031 const unsigned *program
=
1032 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1033 nir
, -1, &error_str
);
1034 if (program
== NULL
) {
1035 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1036 ralloc_free(mem_ctx
);
1040 iris_upload_and_bind_shader(ice
, IRIS_CACHE_CS
, key
, program
, prog_data
,
1043 ralloc_free(mem_ctx
);
1048 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1050 struct iris_uncompiled_shader
*ish
=
1051 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1053 struct brw_cs_prog_key key
= { .program_string_id
= ish
->program_id
};
1054 ice
->vtbl
.populate_cs_key(ice
, &key
);
1056 if (iris_bind_cached_shader(ice
, IRIS_CACHE_CS
, &key
))
1059 UNUSED
bool success
= iris_compile_cs(ice
, ish
, &key
);
1063 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1066 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1067 assert(cs_prog_data
->push
.total
.size
> 0);
1068 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1069 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1070 assert(prog_data
->param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1071 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1076 iris_init_program_functions(struct pipe_context
*ctx
)
1078 ctx
->create_vs_state
= iris_create_shader_state
;
1079 ctx
->create_tcs_state
= iris_create_shader_state
;
1080 ctx
->create_tes_state
= iris_create_shader_state
;
1081 ctx
->create_gs_state
= iris_create_shader_state
;
1082 ctx
->create_fs_state
= iris_create_shader_state
;
1083 ctx
->create_compute_state
= iris_create_compute_state
;
1085 ctx
->delete_vs_state
= iris_delete_shader_state
;
1086 ctx
->delete_tcs_state
= iris_delete_shader_state
;
1087 ctx
->delete_tes_state
= iris_delete_shader_state
;
1088 ctx
->delete_gs_state
= iris_delete_shader_state
;
1089 ctx
->delete_fs_state
= iris_delete_shader_state
;
1090 ctx
->delete_compute_state
= iris_delete_shader_state
;
1092 ctx
->bind_vs_state
= iris_bind_vs_state
;
1093 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1094 ctx
->bind_tes_state
= iris_bind_tes_state
;
1095 ctx
->bind_gs_state
= iris_bind_gs_state
;
1096 ctx
->bind_fs_state
= iris_bind_fs_state
;
1097 ctx
->bind_compute_state
= iris_bind_cs_state
;