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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
46 get_new_program_id(struct iris_screen
*screen
)
48 return p_atomic_inc_return(&screen
->program_id
);
52 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
53 * It primarily contains the NIR for the shader.
55 * Each API-facing shader can be compiled into multiple shader variants,
56 * based on non-orthogonal state dependencies, recorded in the shader key.
58 * See iris_compiled_shader, which represents a compiled shader variant.
60 struct iris_uncompiled_shader
{
63 struct pipe_stream_output_info stream_output
;
67 /** Bitfield of (1 << IRIS_NOS_*) flags. */
72 get_aoa_deref_offset(nir_builder
*b
,
73 nir_deref_instr
*deref
,
76 unsigned array_size
= elem_size
;
77 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
79 while (deref
->deref_type
!= nir_deref_type_var
) {
80 assert(deref
->deref_type
== nir_deref_type_array
);
82 /* This level's element size is the previous level's array size */
83 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
84 assert(deref
->arr
.index
.ssa
);
85 offset
= nir_iadd(b
, offset
,
86 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
88 deref
= nir_deref_instr_parent(deref
);
89 assert(glsl_type_is_array(deref
->type
));
90 array_size
*= glsl_get_length(deref
->type
);
93 /* Accessing an invalid surface index with the dataport can result in a
94 * hang. According to the spec "if the index used to select an individual
95 * element is negative or greater than or equal to the size of the array,
96 * the results of the operation are undefined but may not lead to
97 * termination" -- which is one of the possible outcomes of the hang.
98 * Clamp the index to prevent access outside of the array bounds.
100 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
104 iris_lower_storage_image_derefs(nir_shader
*nir
)
106 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
109 nir_builder_init(&b
, impl
);
111 nir_foreach_block(block
, impl
) {
112 nir_foreach_instr_safe(instr
, block
) {
113 if (instr
->type
!= nir_instr_type_intrinsic
)
116 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
117 switch (intrin
->intrinsic
) {
118 case nir_intrinsic_image_deref_load
:
119 case nir_intrinsic_image_deref_store
:
120 case nir_intrinsic_image_deref_atomic_add
:
121 case nir_intrinsic_image_deref_atomic_min
:
122 case nir_intrinsic_image_deref_atomic_max
:
123 case nir_intrinsic_image_deref_atomic_and
:
124 case nir_intrinsic_image_deref_atomic_or
:
125 case nir_intrinsic_image_deref_atomic_xor
:
126 case nir_intrinsic_image_deref_atomic_exchange
:
127 case nir_intrinsic_image_deref_atomic_comp_swap
:
128 case nir_intrinsic_image_deref_size
:
129 case nir_intrinsic_image_deref_samples
: {
130 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
131 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
133 b
.cursor
= nir_before_instr(&intrin
->instr
);
135 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
136 get_aoa_deref_offset(&b
, deref
, 1));
137 brw_nir_rewrite_image_intrinsic(intrin
, index
);
150 // XXX: need unify_interfaces() at link time...
153 * The pipe->create_[stage]_state() driver hooks.
155 * Performs basic NIR preprocessing, records any state dependencies, and
156 * returns an iris_uncompiled_shader as the Gallium CSO.
158 * Actual shader compilation to assembly happens later, at first use.
161 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
163 const struct pipe_stream_output_info
*so_info
)
165 //struct iris_context *ice = (struct iris_context *)ctx;
166 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 struct iris_uncompiled_shader
*ish
=
170 calloc(1, sizeof(struct iris_uncompiled_shader
));
174 nir
= brw_preprocess_nir(screen
->compiler
, nir
);
176 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
177 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
179 ish
->program_id
= get_new_program_id(screen
);
182 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
184 switch (nir
->info
.stage
) {
185 case MESA_SHADER_VERTEX
:
188 case MESA_SHADER_TESS_CTRL
:
191 case MESA_SHADER_TESS_EVAL
:
194 case MESA_SHADER_GEOMETRY
:
197 case MESA_SHADER_FRAGMENT
:
198 ish
->nos
|= IRIS_NOS_FRAMEBUFFER
|
199 IRIS_NOS_DEPTH_STENCIL_ALPHA
|
200 IRIS_NOS_RASTERIZER
|
203 /* The program key needs the VUE map if there are > 16 inputs */
204 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
205 BRW_FS_VARYING_INPUT_MASK
) > 16) {
206 ish
->nos
|= IRIS_NOS_LAST_VUE_MAP
;
209 case MESA_SHADER_COMPUTE
:
222 * The pipe->delete_[stage]_state() driver hooks.
224 * Frees the iris_uncompiled_shader.
227 iris_create_shader_state(struct pipe_context
*ctx
,
228 const struct pipe_shader_state
*state
)
230 assert(state
->type
== PIPE_SHADER_IR_NIR
);
232 return iris_create_uncompiled_shader(ctx
, state
->ir
.nir
,
233 &state
->stream_output
);
237 iris_create_compute_state(struct pipe_context
*ctx
,
238 const struct pipe_compute_state
*state
)
240 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
242 return iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
246 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
248 struct iris_uncompiled_shader
*ish
= state
;
250 ralloc_free(ish
->nir
);
255 * The pipe->bind_[stage]_state() driver hook.
257 * Binds an uncompiled shader as the current one for a particular stage.
258 * Updates dirty tracking to account for the shader's NOS.
261 bind_state(struct iris_context
*ice
,
262 struct iris_uncompiled_shader
*ish
,
263 gl_shader_stage stage
)
265 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
266 const uint64_t nos
= ish
? ish
->nos
: 0;
268 ice
->shaders
.uncompiled
[stage
] = ish
;
269 ice
->state
.dirty
|= dirty_bit
;
271 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
272 * (or that they no longer need to do so).
274 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
276 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
278 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
283 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
285 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
289 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
291 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
295 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
297 struct iris_context
*ice
= (struct iris_context
*)ctx
;
299 /* Enabling/disabling optional stages requires a URB reconfiguration. */
300 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
301 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
303 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
307 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
309 struct iris_context
*ice
= (struct iris_context
*)ctx
;
311 /* Enabling/disabling optional stages requires a URB reconfiguration. */
312 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
313 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
315 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
319 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
321 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
325 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
327 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
331 * Sets up the starting offsets for the groups of binding table entries
332 * common to all pipeline stages.
334 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
335 * unused but also make sure that addition of small offsets to them will
336 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
339 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
340 const struct nir_shader
*nir
,
341 struct brw_stage_prog_data
*prog_data
,
342 uint32_t next_binding_table_offset
)
344 const struct shader_info
*info
= &nir
->info
;
346 if (info
->num_textures
) {
347 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
348 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
349 next_binding_table_offset
+= info
->num_textures
;
351 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
352 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
355 if (info
->num_images
) {
356 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
357 next_binding_table_offset
+= info
->num_images
;
359 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
362 int num_ubos
= info
->num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
365 //assert(info->num_ubos <= BRW_MAX_UBO);
366 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
367 next_binding_table_offset
+= num_ubos
;
369 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
372 if (info
->num_ssbos
|| info
->num_abos
) {
373 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
374 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
375 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
377 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
380 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
382 /* This may or may not be used depending on how the compile goes. */
383 prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
384 next_binding_table_offset
++;
386 /* Plane 0 is just the regular texture section */
387 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
389 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
390 next_binding_table_offset
+= info
->num_textures
;
392 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
393 next_binding_table_offset
+= info
->num_textures
;
395 /* Set the binding table size */
396 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
398 return next_binding_table_offset
;
402 * Associate NIR uniform variables with the prog_data->param[] mechanism
403 * used by the backend. Also, decide which UBOs we'd like to push in an
404 * ideal situation (though the backend can reduce this).
407 iris_setup_uniforms(const struct brw_compiler
*compiler
,
410 struct brw_stage_prog_data
*prog_data
)
412 prog_data
->nr_params
= nir
->num_uniforms
;
413 /* The intel compiler assumes that num_uniforms is in bytes. For
414 * scalar that means 4 bytes per uniform slot.
416 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
418 nir
->num_uniforms
*= 4;
419 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
421 nir_foreach_variable(var
, &nir
->uniforms
) {
422 const unsigned components
= glsl_get_components(var
->type
);
424 for (unsigned i
= 0; i
< components
; i
++) {
425 prog_data
->param
[var
->data
.driver_location
] =
426 var
->data
.driver_location
;
430 // XXX: vs clip planes?
431 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
435 * If we still have regular uniforms as push constants after the backend
436 * compilation, set up a UBO range for them. This will be used to fill
437 * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
440 iris_setup_push_uniform_range(const struct brw_compiler
*compiler
,
441 struct brw_stage_prog_data
*prog_data
)
443 if (prog_data
->nr_params
) {
444 for (int i
= 3; i
> 0; i
--)
445 prog_data
->ubo_ranges
[i
] = prog_data
->ubo_ranges
[i
- 1];
447 prog_data
->ubo_ranges
[0] = (struct brw_ubo_range
) {
450 .length
= DIV_ROUND_UP(prog_data
->nr_params
, 8),
456 * Compile a vertex shader, and upload the assembly.
459 iris_compile_vs(struct iris_context
*ice
,
460 struct iris_uncompiled_shader
*ish
,
461 const struct brw_vs_prog_key
*key
)
463 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
464 const struct brw_compiler
*compiler
= screen
->compiler
;
465 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
466 void *mem_ctx
= ralloc_context(NULL
);
467 struct brw_vs_prog_data
*vs_prog_data
=
468 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
469 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
470 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
472 nir_shader
*nir
= ish
->nir
;
475 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
477 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
479 brw_compute_vue_map(devinfo
,
480 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
481 nir
->info
.separate_shader
);
483 char *error_str
= NULL
;
484 const unsigned *program
=
485 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, key
, vs_prog_data
,
486 nir
, -1, &error_str
);
487 if (program
== NULL
) {
488 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
489 ralloc_free(mem_ctx
);
493 iris_setup_push_uniform_range(compiler
, prog_data
);
496 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
497 &vue_prog_data
->vue_map
);
499 iris_upload_and_bind_shader(ice
, IRIS_CACHE_VS
, key
, program
, prog_data
,
502 ralloc_free(mem_ctx
);
507 * Update the current vertex shader variant.
509 * Fill out the key, look in the cache, compile and bind if needed.
512 iris_update_compiled_vs(struct iris_context
*ice
)
514 struct iris_uncompiled_shader
*ish
=
515 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
517 struct brw_vs_prog_key key
= { .program_string_id
= ish
->program_id
};
518 ice
->vtbl
.populate_vs_key(ice
, &key
);
520 if (iris_bind_cached_shader(ice
, IRIS_CACHE_VS
, &key
))
523 UNUSED
bool success
= iris_compile_vs(ice
, ish
, &key
);
527 * Get the shader_info for a given stage, or NULL if the stage is disabled.
529 const struct shader_info
*
530 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
532 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
537 const nir_shader
*nir
= ish
->nir
;
541 // XXX: this function is gross
543 iris_get_shader_num_ubos(const struct iris_context
*ice
, gl_shader_stage stage
)
545 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
548 const nir_shader
*nir
= ish
->nir
;
549 /* see assign_common_binding_table_offsets */
550 return nir
->info
.num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
556 * Get the union of TCS output and TES input slots.
558 * TCS and TES need to agree on a common URB entry layout. In particular,
559 * the data for all patch vertices is stored in a single URB entry (unlike
560 * GS which has one entry per input vertex). This means that per-vertex
561 * array indexing needs a stride.
563 * SSO requires locations to match, but doesn't require the number of
564 * outputs/inputs to match (in fact, the TCS often has extra outputs).
565 * So, we need to take the extra step of unifying these on the fly.
568 get_unified_tess_slots(const struct iris_context
*ice
,
569 uint64_t *per_vertex_slots
,
570 uint32_t *per_patch_slots
)
572 const struct shader_info
*tcs
=
573 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
574 const struct shader_info
*tes
=
575 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
577 *per_vertex_slots
= tes
->inputs_read
;
578 *per_patch_slots
= tes
->patch_inputs_read
;
581 *per_vertex_slots
|= tcs
->inputs_read
;
582 *per_patch_slots
|= tcs
->patch_inputs_read
;
587 * Compile a tessellation control shader, and upload the assembly.
590 iris_compile_tcs(struct iris_context
*ice
,
591 struct iris_uncompiled_shader
*ish
,
592 const struct brw_tcs_prog_key
*key
)
594 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
595 const struct brw_compiler
*compiler
= screen
->compiler
;
596 const struct nir_shader_compiler_options
*options
=
597 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
598 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
599 void *mem_ctx
= ralloc_context(NULL
);
600 struct brw_tcs_prog_data
*tcs_prog_data
=
601 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
602 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
603 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
610 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
611 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
613 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
615 /* Reserve space for passing the default tess levels as constants. */
616 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
617 prog_data
->nr_params
= 8;
618 prog_data
->ubo_ranges
[0].length
= 1;
621 char *error_str
= NULL
;
622 const unsigned *program
=
623 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
625 if (program
== NULL
) {
626 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
627 ralloc_free(mem_ctx
);
631 iris_setup_push_uniform_range(compiler
, prog_data
);
633 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TCS
, key
, program
, prog_data
,
636 ralloc_free(mem_ctx
);
641 * Update the current tessellation control shader variant.
643 * Fill out the key, look in the cache, compile and bind if needed.
646 iris_update_compiled_tcs(struct iris_context
*ice
)
648 struct iris_uncompiled_shader
*tcs
=
649 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
651 const struct shader_info
*tes_info
=
652 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
653 struct brw_tcs_prog_key key
= {
654 .program_string_id
= tcs
? tcs
->program_id
: 0,
655 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
656 .input_vertices
= ice
->state
.vertices_per_patch
,
658 get_unified_tess_slots(ice
, &key
.outputs_written
,
659 &key
.patch_outputs_written
);
660 ice
->vtbl
.populate_tcs_key(ice
, &key
);
662 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TCS
, &key
))
665 UNUSED
bool success
= iris_compile_tcs(ice
, tcs
, &key
);
669 * Compile a tessellation evaluation shader, and upload the assembly.
672 iris_compile_tes(struct iris_context
*ice
,
673 struct iris_uncompiled_shader
*ish
,
674 const struct brw_tes_prog_key
*key
)
676 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
677 const struct brw_compiler
*compiler
= screen
->compiler
;
678 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
679 void *mem_ctx
= ralloc_context(NULL
);
680 struct brw_tes_prog_data
*tes_prog_data
=
681 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
682 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
683 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
685 nir_shader
*nir
= ish
->nir
;
687 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
689 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
691 struct brw_vue_map input_vue_map
;
692 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
693 key
->patch_inputs_read
);
695 char *error_str
= NULL
;
696 const unsigned *program
=
697 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
698 tes_prog_data
, nir
, NULL
, -1, &error_str
);
699 if (program
== NULL
) {
700 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
701 ralloc_free(mem_ctx
);
705 iris_setup_push_uniform_range(compiler
, prog_data
);
708 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
709 &vue_prog_data
->vue_map
);
711 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TES
, key
, program
, prog_data
,
714 ralloc_free(mem_ctx
);
719 * Update the current tessellation evaluation shader variant.
721 * Fill out the key, look in the cache, compile and bind if needed.
724 iris_update_compiled_tes(struct iris_context
*ice
)
726 struct iris_uncompiled_shader
*ish
=
727 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
729 struct brw_tes_prog_key key
= { .program_string_id
= ish
->program_id
};
730 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
731 ice
->vtbl
.populate_tes_key(ice
, &key
);
733 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TES
, &key
))
736 UNUSED
bool success
= iris_compile_tes(ice
, ish
, &key
);
740 * Compile a geometry shader, and upload the assembly.
743 iris_compile_gs(struct iris_context
*ice
,
744 struct iris_uncompiled_shader
*ish
,
745 const struct brw_gs_prog_key
*key
)
747 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
748 const struct brw_compiler
*compiler
= screen
->compiler
;
749 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
750 void *mem_ctx
= ralloc_context(NULL
);
751 struct brw_gs_prog_data
*gs_prog_data
=
752 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
753 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
754 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
756 nir_shader
*nir
= ish
->nir
;
758 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
760 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
762 brw_compute_vue_map(devinfo
,
763 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
764 nir
->info
.separate_shader
);
766 char *error_str
= NULL
;
767 const unsigned *program
=
768 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
769 NULL
, -1, &error_str
);
770 if (program
== NULL
) {
771 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
772 ralloc_free(mem_ctx
);
776 iris_setup_push_uniform_range(compiler
, prog_data
);
779 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
780 &vue_prog_data
->vue_map
);
782 iris_upload_and_bind_shader(ice
, IRIS_CACHE_GS
, key
, program
, prog_data
,
785 ralloc_free(mem_ctx
);
790 * Update the current geometry shader variant.
792 * Fill out the key, look in the cache, compile and bind if needed.
795 iris_update_compiled_gs(struct iris_context
*ice
)
797 struct iris_uncompiled_shader
*ish
=
798 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
801 iris_unbind_shader(ice
, IRIS_CACHE_GS
);
805 struct brw_gs_prog_key key
= { .program_string_id
= ish
->program_id
};
806 ice
->vtbl
.populate_gs_key(ice
, &key
);
808 if (iris_bind_cached_shader(ice
, IRIS_CACHE_GS
, &key
))
811 UNUSED
bool success
= iris_compile_gs(ice
, ish
, &key
);
815 * Compile a fragment (pixel) shader, and upload the assembly.
818 iris_compile_fs(struct iris_context
*ice
,
819 struct iris_uncompiled_shader
*ish
,
820 const struct brw_wm_prog_key
*key
,
821 struct brw_vue_map
*vue_map
)
823 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
824 const struct brw_compiler
*compiler
= screen
->compiler
;
825 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
826 void *mem_ctx
= ralloc_context(NULL
);
827 struct brw_wm_prog_data
*fs_prog_data
=
828 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
829 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
831 nir_shader
*nir
= ish
->nir
;
834 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
835 MAX2(key
->nr_color_regions
, 1));
837 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
839 char *error_str
= NULL
;
840 const unsigned *program
=
841 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
842 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
843 if (program
== NULL
) {
844 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
845 ralloc_free(mem_ctx
);
849 //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
851 iris_setup_push_uniform_range(compiler
, prog_data
);
853 iris_upload_and_bind_shader(ice
, IRIS_CACHE_FS
, key
, program
, prog_data
,
856 ralloc_free(mem_ctx
);
861 * Update the current fragment shader variant.
863 * Fill out the key, look in the cache, compile and bind if needed.
866 iris_update_compiled_fs(struct iris_context
*ice
)
868 struct iris_uncompiled_shader
*ish
=
869 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
870 struct brw_wm_prog_key key
= { .program_string_id
= ish
->program_id
};
871 ice
->vtbl
.populate_fs_key(ice
, &key
);
873 if (ish
->nos
& IRIS_NOS_LAST_VUE_MAP
)
874 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
876 if (iris_bind_cached_shader(ice
, IRIS_CACHE_FS
, &key
))
879 UNUSED
bool success
=
880 iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
884 * Get the compiled shader for the last enabled geometry stage.
886 * This stage is the one which will feed stream output and the rasterizer.
888 static struct iris_compiled_shader
*
889 last_vue_shader(struct iris_context
*ice
)
891 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
892 return ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
894 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
895 return ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
897 return ice
->shaders
.prog
[MESA_SHADER_VERTEX
];
901 * Update the last enabled stage's VUE map.
903 * When the shader feeding the rasterizer's output interface changes, we
904 * need to re-emit various packets.
907 update_last_vue_map(struct iris_context
*ice
,
908 struct brw_stage_prog_data
*prog_data
)
910 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
911 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
912 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
913 const uint64_t changed_slots
=
914 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
916 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
917 // XXX: could use ctx->Const.MaxViewports for old API efficiency
918 ice
->state
.num_viewports
=
919 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
920 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
921 IRIS_DIRTY_SF_CL_VIEWPORT
|
922 IRIS_DIRTY_SCISSOR_RECT
|
923 IRIS_DIRTY_UNCOMPILED_FS
|
924 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
928 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
929 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
932 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
936 * Get the prog_data for a given stage, or NULL if the stage is disabled.
938 static struct brw_vue_prog_data
*
939 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
941 if (!ice
->shaders
.prog
[stage
])
944 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
948 * Update the current shader variants for the given state.
950 * This should be called on every draw call to ensure that the correct
951 * shaders are bound. It will also flag any dirty state triggered by
952 * swapping out those shaders.
955 iris_update_compiled_shaders(struct iris_context
*ice
)
957 const uint64_t dirty
= ice
->state
.dirty
;
959 struct brw_vue_prog_data
*old_prog_datas
[4];
960 if (!(dirty
& IRIS_DIRTY_URB
)) {
961 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
962 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
965 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
966 struct iris_uncompiled_shader
*tes
=
967 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
969 iris_update_compiled_tcs(ice
);
970 iris_update_compiled_tes(ice
);
972 iris_unbind_shader(ice
, IRIS_CACHE_TCS
);
973 iris_unbind_shader(ice
, IRIS_CACHE_TES
);
977 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
978 iris_update_compiled_vs(ice
);
979 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
980 iris_update_compiled_gs(ice
);
982 struct iris_compiled_shader
*shader
= last_vue_shader(ice
);
983 update_last_vue_map(ice
, shader
->prog_data
);
984 if (ice
->state
.streamout
!= shader
->streamout
) {
985 ice
->state
.streamout
= shader
->streamout
;
986 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
989 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
990 iris_update_compiled_fs(ice
);
993 /* Changing shader interfaces may require a URB configuration. */
994 if (!(dirty
& IRIS_DIRTY_URB
)) {
995 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
996 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
997 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
998 if (!!old
!= !!new ||
999 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1000 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1008 iris_init_program_functions(struct pipe_context
*ctx
)
1010 ctx
->create_vs_state
= iris_create_shader_state
;
1011 ctx
->create_tcs_state
= iris_create_shader_state
;
1012 ctx
->create_tes_state
= iris_create_shader_state
;
1013 ctx
->create_gs_state
= iris_create_shader_state
;
1014 ctx
->create_fs_state
= iris_create_shader_state
;
1015 ctx
->create_compute_state
= iris_create_compute_state
;
1017 ctx
->delete_vs_state
= iris_delete_shader_state
;
1018 ctx
->delete_tcs_state
= iris_delete_shader_state
;
1019 ctx
->delete_tes_state
= iris_delete_shader_state
;
1020 ctx
->delete_gs_state
= iris_delete_shader_state
;
1021 ctx
->delete_fs_state
= iris_delete_shader_state
;
1022 ctx
->delete_compute_state
= iris_delete_shader_state
;
1024 ctx
->bind_vs_state
= iris_bind_vs_state
;
1025 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1026 ctx
->bind_tes_state
= iris_bind_tes_state
;
1027 ctx
->bind_gs_state
= iris_bind_gs_state
;
1028 ctx
->bind_fs_state
= iris_bind_fs_state
;
1029 ctx
->bind_compute_state
= iris_bind_cs_state
;