2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
46 get_new_program_id(struct iris_screen
*screen
)
48 return p_atomic_inc_return(&screen
->program_id
);
52 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
53 * It primarily contains the NIR for the shader.
55 * Each API-facing shader can be compiled into multiple shader variants,
56 * based on non-orthogonal state dependencies, recorded in the shader key.
58 * See iris_compiled_shader, which represents a compiled shader variant.
60 struct iris_uncompiled_shader
{
63 struct pipe_stream_output_info stream_output
;
67 /** Bitfield of (1 << IRIS_NOS_*) flags. */
72 get_aoa_deref_offset(nir_builder
*b
,
73 nir_deref_instr
*deref
,
76 unsigned array_size
= elem_size
;
77 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
79 while (deref
->deref_type
!= nir_deref_type_var
) {
80 assert(deref
->deref_type
== nir_deref_type_array
);
82 /* This level's element size is the previous level's array size */
83 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
84 assert(deref
->arr
.index
.ssa
);
85 offset
= nir_iadd(b
, offset
,
86 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
88 deref
= nir_deref_instr_parent(deref
);
89 assert(glsl_type_is_array(deref
->type
));
90 array_size
*= glsl_get_length(deref
->type
);
93 /* Accessing an invalid surface index with the dataport can result in a
94 * hang. According to the spec "if the index used to select an individual
95 * element is negative or greater than or equal to the size of the array,
96 * the results of the operation are undefined but may not lead to
97 * termination" -- which is one of the possible outcomes of the hang.
98 * Clamp the index to prevent access outside of the array bounds.
100 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
104 iris_lower_storage_image_derefs(nir_shader
*nir
)
106 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
109 nir_builder_init(&b
, impl
);
111 nir_foreach_block(block
, impl
) {
112 nir_foreach_instr_safe(instr
, block
) {
113 if (instr
->type
!= nir_instr_type_intrinsic
)
116 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
117 switch (intrin
->intrinsic
) {
118 case nir_intrinsic_image_deref_load
:
119 case nir_intrinsic_image_deref_store
:
120 case nir_intrinsic_image_deref_atomic_add
:
121 case nir_intrinsic_image_deref_atomic_min
:
122 case nir_intrinsic_image_deref_atomic_max
:
123 case nir_intrinsic_image_deref_atomic_and
:
124 case nir_intrinsic_image_deref_atomic_or
:
125 case nir_intrinsic_image_deref_atomic_xor
:
126 case nir_intrinsic_image_deref_atomic_exchange
:
127 case nir_intrinsic_image_deref_atomic_comp_swap
:
128 case nir_intrinsic_image_deref_size
:
129 case nir_intrinsic_image_deref_samples
: {
130 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
131 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
133 b
.cursor
= nir_before_instr(&intrin
->instr
);
135 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
136 get_aoa_deref_offset(&b
, deref
, 1));
137 brw_nir_rewrite_image_intrinsic(intrin
, index
);
150 // XXX: need unify_interfaces() at link time...
153 * The pipe->create_[stage]_state() driver hooks.
155 * Performs basic NIR preprocessing, records any state dependencies, and
156 * returns an iris_uncompiled_shader as the Gallium CSO.
158 * Actual shader compilation to assembly happens later, at first use.
161 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
163 const struct pipe_stream_output_info
*so_info
)
165 //struct iris_context *ice = (struct iris_context *)ctx;
166 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 struct iris_uncompiled_shader
*ish
=
170 calloc(1, sizeof(struct iris_uncompiled_shader
));
174 nir
= brw_preprocess_nir(screen
->compiler
, nir
);
176 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
177 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
179 ish
->program_id
= get_new_program_id(screen
);
182 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
184 switch (nir
->info
.stage
) {
185 case MESA_SHADER_VERTEX
:
188 case MESA_SHADER_TESS_CTRL
:
191 case MESA_SHADER_TESS_EVAL
:
194 case MESA_SHADER_GEOMETRY
:
197 case MESA_SHADER_FRAGMENT
:
198 ish
->nos
|= IRIS_NOS_FRAMEBUFFER
|
199 IRIS_NOS_DEPTH_STENCIL_ALPHA
|
200 IRIS_NOS_RASTERIZER
|
203 /* The program key needs the VUE map if there are > 16 inputs */
204 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
205 BRW_FS_VARYING_INPUT_MASK
) > 16) {
206 ish
->nos
|= IRIS_NOS_LAST_VUE_MAP
;
209 case MESA_SHADER_COMPUTE
:
217 // XXX: disallow more than 64KB of shared variables
223 * The pipe->delete_[stage]_state() driver hooks.
225 * Frees the iris_uncompiled_shader.
228 iris_create_shader_state(struct pipe_context
*ctx
,
229 const struct pipe_shader_state
*state
)
231 assert(state
->type
== PIPE_SHADER_IR_NIR
);
233 return iris_create_uncompiled_shader(ctx
, state
->ir
.nir
,
234 &state
->stream_output
);
238 iris_create_compute_state(struct pipe_context
*ctx
,
239 const struct pipe_compute_state
*state
)
241 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
243 return iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
247 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
249 struct iris_uncompiled_shader
*ish
= state
;
251 ralloc_free(ish
->nir
);
256 * The pipe->bind_[stage]_state() driver hook.
258 * Binds an uncompiled shader as the current one for a particular stage.
259 * Updates dirty tracking to account for the shader's NOS.
262 bind_state(struct iris_context
*ice
,
263 struct iris_uncompiled_shader
*ish
,
264 gl_shader_stage stage
)
266 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
267 const uint64_t nos
= ish
? ish
->nos
: 0;
269 ice
->shaders
.uncompiled
[stage
] = ish
;
270 ice
->state
.dirty
|= dirty_bit
;
272 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
273 * (or that they no longer need to do so).
275 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
277 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
279 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
284 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
286 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
290 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
292 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
296 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
298 struct iris_context
*ice
= (struct iris_context
*)ctx
;
300 /* Enabling/disabling optional stages requires a URB reconfiguration. */
301 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
302 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
304 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
308 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
310 struct iris_context
*ice
= (struct iris_context
*)ctx
;
312 /* Enabling/disabling optional stages requires a URB reconfiguration. */
313 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
314 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
316 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
320 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
322 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
326 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
328 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
332 * Sets up the starting offsets for the groups of binding table entries
333 * common to all pipeline stages.
335 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
336 * unused but also make sure that addition of small offsets to them will
337 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
340 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
341 const struct nir_shader
*nir
,
342 struct brw_stage_prog_data
*prog_data
,
343 uint32_t next_binding_table_offset
)
345 const struct shader_info
*info
= &nir
->info
;
347 if (info
->num_textures
) {
348 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
349 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
350 next_binding_table_offset
+= info
->num_textures
;
352 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
353 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
356 if (info
->num_images
) {
357 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
358 next_binding_table_offset
+= info
->num_images
;
360 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
363 int num_ubos
= info
->num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
366 //assert(info->num_ubos <= BRW_MAX_UBO);
367 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
368 next_binding_table_offset
+= num_ubos
;
370 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
373 if (info
->num_ssbos
|| info
->num_abos
) {
374 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
375 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
376 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
378 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
381 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
383 /* This may or may not be used depending on how the compile goes. */
384 prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
385 next_binding_table_offset
++;
387 /* Plane 0 is just the regular texture section */
388 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
390 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
391 next_binding_table_offset
+= info
->num_textures
;
393 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
394 next_binding_table_offset
+= info
->num_textures
;
396 /* Set the binding table size */
397 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
399 return next_binding_table_offset
;
403 * Associate NIR uniform variables with the prog_data->param[] mechanism
404 * used by the backend. Also, decide which UBOs we'd like to push in an
405 * ideal situation (though the backend can reduce this).
408 iris_setup_uniforms(const struct brw_compiler
*compiler
,
411 struct brw_stage_prog_data
*prog_data
)
413 /* The intel compiler assumes that num_uniforms is in bytes. For
414 * scalar that means 4 bytes per uniform slot.
416 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
418 nir
->num_uniforms
*= 4;
420 prog_data
->nr_params
= 0;
421 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 1);
423 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
426 nir_builder_init(&b
, impl
);
428 b
.cursor
= nir_before_block(nir_start_block(impl
));
429 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
431 nir_foreach_block(block
, impl
) {
432 nir_foreach_instr_safe(instr
, block
) {
433 if (instr
->type
!= nir_instr_type_intrinsic
)
436 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
438 unsigned param_idx
= prog_data
->nr_params
;
439 uint32_t *param
= NULL
;
441 switch (intrin
->intrinsic
) {
442 case nir_intrinsic_load_user_clip_plane
: {
443 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
444 param
= brw_stage_prog_data_add_params(prog_data
, 4);
445 for (int i
= 0; i
< 4; i
++) {
447 IRIS_PARAM(BUILTIN
, BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
));
455 b
.cursor
= nir_before_instr(instr
);
457 unsigned comps
= nir_intrinsic_dest_components(intrin
);
458 nir_ssa_def
*offset
= nir_imm_int(&b
, param_idx
* sizeof(uint32_t));
460 nir_intrinsic_instr
*load
=
461 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
462 load
->num_components
= comps
;
463 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
464 load
->src
[1] = nir_src_for_ssa(offset
);
465 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
466 nir_builder_instr_insert(&b
, &load
->instr
);
467 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
468 nir_src_for_ssa(&load
->dest
.ssa
));
469 nir_instr_remove(instr
);
473 if (prog_data
->nr_params
> 0) {
474 nir_foreach_block(block
, impl
) {
475 nir_foreach_instr_safe(instr
, block
) {
476 if (instr
->type
!= nir_instr_type_intrinsic
)
479 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
481 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
484 b
.cursor
= nir_before_instr(instr
);
486 if (load
->src
[0].ssa
== temp_ubo_name
) {
487 load
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
488 } else if (nir_src_as_uint(load
->src
[0]) == 0) {
489 nir_ssa_def
*offset
=
490 nir_iadd(&b
, load
->src
[1].ssa
,
491 nir_imm_int(&b
, prog_data
->nr_params
));
492 load
->src
[1] = nir_src_for_ssa(offset
);
498 // XXX: vs clip planes?
499 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
500 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
504 * If we still have regular uniforms as push constants after the backend
505 * compilation, set up a UBO range for them. This will be used to fill
506 * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
509 iris_setup_push_uniform_range(const struct brw_compiler
*compiler
,
510 struct brw_stage_prog_data
*prog_data
)
512 if (prog_data
->nr_params
) {
513 for (int i
= 3; i
> 0; i
--)
514 prog_data
->ubo_ranges
[i
] = prog_data
->ubo_ranges
[i
- 1];
516 prog_data
->ubo_ranges
[0] = (struct brw_ubo_range
) {
519 .length
= DIV_ROUND_UP(prog_data
->nr_params
, 8),
525 * Compile a vertex shader, and upload the assembly.
528 iris_compile_vs(struct iris_context
*ice
,
529 struct iris_uncompiled_shader
*ish
,
530 const struct brw_vs_prog_key
*key
)
532 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
533 const struct brw_compiler
*compiler
= screen
->compiler
;
534 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
535 void *mem_ctx
= ralloc_context(NULL
);
536 struct brw_vs_prog_data
*vs_prog_data
=
537 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
538 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
539 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
541 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
544 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
546 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
548 brw_compute_vue_map(devinfo
,
549 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
550 nir
->info
.separate_shader
);
552 char *error_str
= NULL
;
553 const unsigned *program
=
554 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, key
, vs_prog_data
,
555 nir
, -1, &error_str
);
556 if (program
== NULL
) {
557 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
558 ralloc_free(mem_ctx
);
562 iris_setup_push_uniform_range(compiler
, prog_data
);
565 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
566 &vue_prog_data
->vue_map
);
568 iris_upload_and_bind_shader(ice
, IRIS_CACHE_VS
, key
, program
, prog_data
,
571 ralloc_free(mem_ctx
);
576 * Update the current vertex shader variant.
578 * Fill out the key, look in the cache, compile and bind if needed.
581 iris_update_compiled_vs(struct iris_context
*ice
)
583 struct iris_uncompiled_shader
*ish
=
584 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
586 struct brw_vs_prog_key key
= { .program_string_id
= ish
->program_id
};
587 ice
->vtbl
.populate_vs_key(ice
, &key
);
589 if (iris_bind_cached_shader(ice
, IRIS_CACHE_VS
, &key
))
592 UNUSED
bool success
= iris_compile_vs(ice
, ish
, &key
);
596 * Get the shader_info for a given stage, or NULL if the stage is disabled.
598 const struct shader_info
*
599 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
601 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
606 const nir_shader
*nir
= ish
->nir
;
610 // XXX: this function is gross
612 iris_get_shader_num_ubos(const struct iris_context
*ice
, gl_shader_stage stage
)
614 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
617 const nir_shader
*nir
= ish
->nir
;
618 /* see assign_common_binding_table_offsets */
619 return nir
->info
.num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
625 * Get the union of TCS output and TES input slots.
627 * TCS and TES need to agree on a common URB entry layout. In particular,
628 * the data for all patch vertices is stored in a single URB entry (unlike
629 * GS which has one entry per input vertex). This means that per-vertex
630 * array indexing needs a stride.
632 * SSO requires locations to match, but doesn't require the number of
633 * outputs/inputs to match (in fact, the TCS often has extra outputs).
634 * So, we need to take the extra step of unifying these on the fly.
637 get_unified_tess_slots(const struct iris_context
*ice
,
638 uint64_t *per_vertex_slots
,
639 uint32_t *per_patch_slots
)
641 const struct shader_info
*tcs
=
642 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
643 const struct shader_info
*tes
=
644 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
646 *per_vertex_slots
= tes
->inputs_read
;
647 *per_patch_slots
= tes
->patch_inputs_read
;
650 *per_vertex_slots
|= tcs
->inputs_read
;
651 *per_patch_slots
|= tcs
->patch_inputs_read
;
656 * Compile a tessellation control shader, and upload the assembly.
659 iris_compile_tcs(struct iris_context
*ice
,
660 struct iris_uncompiled_shader
*ish
,
661 const struct brw_tcs_prog_key
*key
)
663 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
664 const struct brw_compiler
*compiler
= screen
->compiler
;
665 const struct nir_shader_compiler_options
*options
=
666 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
667 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
668 void *mem_ctx
= ralloc_context(NULL
);
669 struct brw_tcs_prog_data
*tcs_prog_data
=
670 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
671 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
672 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
677 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
679 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
680 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
682 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
684 /* Reserve space for passing the default tess levels as constants. */
685 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
686 prog_data
->nr_params
= 8;
687 prog_data
->ubo_ranges
[0].length
= 1;
690 char *error_str
= NULL
;
691 const unsigned *program
=
692 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
694 if (program
== NULL
) {
695 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
696 ralloc_free(mem_ctx
);
700 iris_setup_push_uniform_range(compiler
, prog_data
);
702 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TCS
, key
, program
, prog_data
,
705 ralloc_free(mem_ctx
);
710 * Update the current tessellation control shader variant.
712 * Fill out the key, look in the cache, compile and bind if needed.
715 iris_update_compiled_tcs(struct iris_context
*ice
)
717 struct iris_uncompiled_shader
*tcs
=
718 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
720 const struct shader_info
*tes_info
=
721 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
722 struct brw_tcs_prog_key key
= {
723 .program_string_id
= tcs
? tcs
->program_id
: 0,
724 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
725 .input_vertices
= ice
->state
.vertices_per_patch
,
727 get_unified_tess_slots(ice
, &key
.outputs_written
,
728 &key
.patch_outputs_written
);
729 ice
->vtbl
.populate_tcs_key(ice
, &key
);
731 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TCS
, &key
))
734 UNUSED
bool success
= iris_compile_tcs(ice
, tcs
, &key
);
738 * Compile a tessellation evaluation shader, and upload the assembly.
741 iris_compile_tes(struct iris_context
*ice
,
742 struct iris_uncompiled_shader
*ish
,
743 const struct brw_tes_prog_key
*key
)
745 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
746 const struct brw_compiler
*compiler
= screen
->compiler
;
747 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
748 void *mem_ctx
= ralloc_context(NULL
);
749 struct brw_tes_prog_data
*tes_prog_data
=
750 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
751 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
752 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
754 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
756 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
758 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
760 struct brw_vue_map input_vue_map
;
761 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
762 key
->patch_inputs_read
);
764 char *error_str
= NULL
;
765 const unsigned *program
=
766 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
767 tes_prog_data
, nir
, NULL
, -1, &error_str
);
768 if (program
== NULL
) {
769 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
770 ralloc_free(mem_ctx
);
774 iris_setup_push_uniform_range(compiler
, prog_data
);
777 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
778 &vue_prog_data
->vue_map
);
780 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TES
, key
, program
, prog_data
,
783 ralloc_free(mem_ctx
);
788 * Update the current tessellation evaluation shader variant.
790 * Fill out the key, look in the cache, compile and bind if needed.
793 iris_update_compiled_tes(struct iris_context
*ice
)
795 struct iris_uncompiled_shader
*ish
=
796 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
798 struct brw_tes_prog_key key
= { .program_string_id
= ish
->program_id
};
799 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
800 ice
->vtbl
.populate_tes_key(ice
, &key
);
802 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TES
, &key
))
805 UNUSED
bool success
= iris_compile_tes(ice
, ish
, &key
);
809 * Compile a geometry shader, and upload the assembly.
812 iris_compile_gs(struct iris_context
*ice
,
813 struct iris_uncompiled_shader
*ish
,
814 const struct brw_gs_prog_key
*key
)
816 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
817 const struct brw_compiler
*compiler
= screen
->compiler
;
818 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
819 void *mem_ctx
= ralloc_context(NULL
);
820 struct brw_gs_prog_data
*gs_prog_data
=
821 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
822 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
823 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
825 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
827 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
829 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
831 brw_compute_vue_map(devinfo
,
832 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
833 nir
->info
.separate_shader
);
835 char *error_str
= NULL
;
836 const unsigned *program
=
837 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
838 NULL
, -1, &error_str
);
839 if (program
== NULL
) {
840 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
841 ralloc_free(mem_ctx
);
845 iris_setup_push_uniform_range(compiler
, prog_data
);
848 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
849 &vue_prog_data
->vue_map
);
851 iris_upload_and_bind_shader(ice
, IRIS_CACHE_GS
, key
, program
, prog_data
,
854 ralloc_free(mem_ctx
);
859 * Update the current geometry shader variant.
861 * Fill out the key, look in the cache, compile and bind if needed.
864 iris_update_compiled_gs(struct iris_context
*ice
)
866 struct iris_uncompiled_shader
*ish
=
867 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
870 iris_unbind_shader(ice
, IRIS_CACHE_GS
);
874 struct brw_gs_prog_key key
= { .program_string_id
= ish
->program_id
};
875 ice
->vtbl
.populate_gs_key(ice
, &key
);
877 if (iris_bind_cached_shader(ice
, IRIS_CACHE_GS
, &key
))
880 UNUSED
bool success
= iris_compile_gs(ice
, ish
, &key
);
884 * Compile a fragment (pixel) shader, and upload the assembly.
887 iris_compile_fs(struct iris_context
*ice
,
888 struct iris_uncompiled_shader
*ish
,
889 const struct brw_wm_prog_key
*key
,
890 struct brw_vue_map
*vue_map
)
892 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
893 const struct brw_compiler
*compiler
= screen
->compiler
;
894 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
895 void *mem_ctx
= ralloc_context(NULL
);
896 struct brw_wm_prog_data
*fs_prog_data
=
897 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
898 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
900 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
903 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
904 MAX2(key
->nr_color_regions
, 1));
906 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
908 char *error_str
= NULL
;
909 const unsigned *program
=
910 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
911 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
912 if (program
== NULL
) {
913 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
914 ralloc_free(mem_ctx
);
918 //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
920 iris_setup_push_uniform_range(compiler
, prog_data
);
922 iris_upload_and_bind_shader(ice
, IRIS_CACHE_FS
, key
, program
, prog_data
,
925 ralloc_free(mem_ctx
);
930 * Update the current fragment shader variant.
932 * Fill out the key, look in the cache, compile and bind if needed.
935 iris_update_compiled_fs(struct iris_context
*ice
)
937 struct iris_uncompiled_shader
*ish
=
938 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
939 struct brw_wm_prog_key key
= { .program_string_id
= ish
->program_id
};
940 ice
->vtbl
.populate_fs_key(ice
, &key
);
942 if (ish
->nos
& IRIS_NOS_LAST_VUE_MAP
)
943 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
945 if (iris_bind_cached_shader(ice
, IRIS_CACHE_FS
, &key
))
948 UNUSED
bool success
=
949 iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
953 * Get the compiled shader for the last enabled geometry stage.
955 * This stage is the one which will feed stream output and the rasterizer.
957 static struct iris_compiled_shader
*
958 last_vue_shader(struct iris_context
*ice
)
960 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
961 return ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
963 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
964 return ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
966 return ice
->shaders
.prog
[MESA_SHADER_VERTEX
];
970 * Update the last enabled stage's VUE map.
972 * When the shader feeding the rasterizer's output interface changes, we
973 * need to re-emit various packets.
976 update_last_vue_map(struct iris_context
*ice
,
977 struct brw_stage_prog_data
*prog_data
)
979 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
980 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
981 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
982 const uint64_t changed_slots
=
983 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
985 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
986 // XXX: could use ctx->Const.MaxViewports for old API efficiency
987 ice
->state
.num_viewports
=
988 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
989 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
990 IRIS_DIRTY_SF_CL_VIEWPORT
|
991 IRIS_DIRTY_CC_VIEWPORT
|
992 IRIS_DIRTY_SCISSOR_RECT
|
993 IRIS_DIRTY_UNCOMPILED_FS
|
994 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
998 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
999 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1002 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1006 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1008 static struct brw_vue_prog_data
*
1009 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1011 if (!ice
->shaders
.prog
[stage
])
1014 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1018 * Update the current shader variants for the given state.
1020 * This should be called on every draw call to ensure that the correct
1021 * shaders are bound. It will also flag any dirty state triggered by
1022 * swapping out those shaders.
1025 iris_update_compiled_shaders(struct iris_context
*ice
)
1027 const uint64_t dirty
= ice
->state
.dirty
;
1029 struct brw_vue_prog_data
*old_prog_datas
[4];
1030 if (!(dirty
& IRIS_DIRTY_URB
)) {
1031 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1032 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1035 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1036 struct iris_uncompiled_shader
*tes
=
1037 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1039 iris_update_compiled_tcs(ice
);
1040 iris_update_compiled_tes(ice
);
1042 iris_unbind_shader(ice
, IRIS_CACHE_TCS
);
1043 iris_unbind_shader(ice
, IRIS_CACHE_TES
);
1047 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1048 iris_update_compiled_vs(ice
);
1049 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1050 iris_update_compiled_gs(ice
);
1052 struct iris_compiled_shader
*shader
= last_vue_shader(ice
);
1053 update_last_vue_map(ice
, shader
->prog_data
);
1054 if (ice
->state
.streamout
!= shader
->streamout
) {
1055 ice
->state
.streamout
= shader
->streamout
;
1056 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1059 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1060 iris_update_compiled_fs(ice
);
1063 /* Changing shader interfaces may require a URB configuration. */
1064 if (!(dirty
& IRIS_DIRTY_URB
)) {
1065 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1066 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1067 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1068 if (!!old
!= !!new ||
1069 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1070 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1078 iris_compile_cs(struct iris_context
*ice
,
1079 struct iris_uncompiled_shader
*ish
,
1080 const struct brw_cs_prog_key
*key
)
1082 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1083 const struct brw_compiler
*compiler
= screen
->compiler
;
1084 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1085 void *mem_ctx
= ralloc_context(NULL
);
1086 struct brw_cs_prog_data
*cs_prog_data
=
1087 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1088 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1090 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1092 cs_prog_data
->binding_table
.work_groups_start
= 0;
1093 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1);
1095 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
1097 char *error_str
= NULL
;
1098 const unsigned *program
=
1099 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1100 nir
, -1, &error_str
);
1101 if (program
== NULL
) {
1102 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1103 ralloc_free(mem_ctx
);
1107 iris_upload_and_bind_shader(ice
, IRIS_CACHE_CS
, key
, program
, prog_data
,
1110 ralloc_free(mem_ctx
);
1115 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1117 struct iris_uncompiled_shader
*ish
=
1118 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1120 struct brw_cs_prog_key key
= { .program_string_id
= ish
->program_id
};
1121 ice
->vtbl
.populate_cs_key(ice
, &key
);
1123 if (iris_bind_cached_shader(ice
, IRIS_CACHE_CS
, &key
))
1126 UNUSED
bool success
= iris_compile_cs(ice
, ish
, &key
);
1130 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1133 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1134 assert(cs_prog_data
->push
.total
.size
> 0);
1135 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1136 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1137 assert(prog_data
->param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1138 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1143 * Allocate scratch BOs as needed for the given per-thread size and stage.
1145 * Returns the 32-bit "Scratch Space Base Pointer" value.
1148 iris_get_scratch_space(struct iris_context
*ice
,
1149 unsigned per_thread_scratch
,
1150 gl_shader_stage stage
)
1152 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1153 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1154 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1156 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1157 assert(encoded_size
< (1 << 16));
1159 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1161 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1163 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1164 * allocate scratch space enough so that each slice has 4 slices
1167 * According to the other driver team, this applies to compute shaders
1168 * as well. This is not currently documented at all.
1170 unsigned subslice_total
= 4 * devinfo
->num_slices
;
1171 assert(subslice_total
>= screen
->subslice_total
);
1174 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1175 uint32_t max_threads
[] = {
1176 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1177 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1178 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1179 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1180 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1181 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1184 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1186 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1189 return (*bop
)->gtt_offset
;
1193 iris_init_program_functions(struct pipe_context
*ctx
)
1195 ctx
->create_vs_state
= iris_create_shader_state
;
1196 ctx
->create_tcs_state
= iris_create_shader_state
;
1197 ctx
->create_tes_state
= iris_create_shader_state
;
1198 ctx
->create_gs_state
= iris_create_shader_state
;
1199 ctx
->create_fs_state
= iris_create_shader_state
;
1200 ctx
->create_compute_state
= iris_create_compute_state
;
1202 ctx
->delete_vs_state
= iris_delete_shader_state
;
1203 ctx
->delete_tcs_state
= iris_delete_shader_state
;
1204 ctx
->delete_tes_state
= iris_delete_shader_state
;
1205 ctx
->delete_gs_state
= iris_delete_shader_state
;
1206 ctx
->delete_fs_state
= iris_delete_shader_state
;
1207 ctx
->delete_compute_state
= iris_delete_shader_state
;
1209 ctx
->bind_vs_state
= iris_bind_vs_state
;
1210 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1211 ctx
->bind_tes_state
= iris_bind_tes_state
;
1212 ctx
->bind_gs_state
= iris_bind_gs_state
;
1213 ctx
->bind_fs_state
= iris_bind_fs_state
;
1214 ctx
->bind_compute_state
= iris_bind_cs_state
;