2 * Copyright © 2017 Intel Corporation
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
46 get_new_program_id(struct iris_screen
*screen
)
48 return p_atomic_inc_return(&screen
->program_id
);
52 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
53 * It primarily contains the NIR for the shader.
55 * Each API-facing shader can be compiled into multiple shader variants,
56 * based on non-orthogonal state dependencies, recorded in the shader key.
58 * See iris_compiled_shader, which represents a compiled shader variant.
60 struct iris_uncompiled_shader
{
63 struct pipe_stream_output_info stream_output
;
67 /** Bitfield of (1 << IRIS_NOS_*) flags. */
72 get_aoa_deref_offset(nir_builder
*b
,
73 nir_deref_instr
*deref
,
76 unsigned array_size
= elem_size
;
77 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
79 while (deref
->deref_type
!= nir_deref_type_var
) {
80 assert(deref
->deref_type
== nir_deref_type_array
);
82 /* This level's element size is the previous level's array size */
83 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
84 assert(deref
->arr
.index
.ssa
);
85 offset
= nir_iadd(b
, offset
,
86 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
88 deref
= nir_deref_instr_parent(deref
);
89 assert(glsl_type_is_array(deref
->type
));
90 array_size
*= glsl_get_length(deref
->type
);
93 /* Accessing an invalid surface index with the dataport can result in a
94 * hang. According to the spec "if the index used to select an individual
95 * element is negative or greater than or equal to the size of the array,
96 * the results of the operation are undefined but may not lead to
97 * termination" -- which is one of the possible outcomes of the hang.
98 * Clamp the index to prevent access outside of the array bounds.
100 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
104 iris_lower_storage_image_derefs(nir_shader
*nir
)
106 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
109 nir_builder_init(&b
, impl
);
111 nir_foreach_block(block
, impl
) {
112 nir_foreach_instr_safe(instr
, block
) {
113 if (instr
->type
!= nir_instr_type_intrinsic
)
116 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
117 switch (intrin
->intrinsic
) {
118 case nir_intrinsic_image_deref_load
:
119 case nir_intrinsic_image_deref_store
:
120 case nir_intrinsic_image_deref_atomic_add
:
121 case nir_intrinsic_image_deref_atomic_min
:
122 case nir_intrinsic_image_deref_atomic_max
:
123 case nir_intrinsic_image_deref_atomic_and
:
124 case nir_intrinsic_image_deref_atomic_or
:
125 case nir_intrinsic_image_deref_atomic_xor
:
126 case nir_intrinsic_image_deref_atomic_exchange
:
127 case nir_intrinsic_image_deref_atomic_comp_swap
:
128 case nir_intrinsic_image_deref_size
:
129 case nir_intrinsic_image_deref_samples
: {
130 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
131 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
133 b
.cursor
= nir_before_instr(&intrin
->instr
);
135 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
136 get_aoa_deref_offset(&b
, deref
, 1));
137 brw_nir_rewrite_image_intrinsic(intrin
, index
);
150 // XXX: need unify_interfaces() at link time...
153 * The pipe->create_[stage]_state() driver hooks.
155 * Performs basic NIR preprocessing, records any state dependencies, and
156 * returns an iris_uncompiled_shader as the Gallium CSO.
158 * Actual shader compilation to assembly happens later, at first use.
161 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
163 const struct pipe_stream_output_info
*so_info
)
165 //struct iris_context *ice = (struct iris_context *)ctx;
166 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 struct iris_uncompiled_shader
*ish
=
170 calloc(1, sizeof(struct iris_uncompiled_shader
));
174 nir
= brw_preprocess_nir(screen
->compiler
, nir
);
176 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
177 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
179 ish
->program_id
= get_new_program_id(screen
);
182 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
184 switch (nir
->info
.stage
) {
185 case MESA_SHADER_VERTEX
:
188 case MESA_SHADER_TESS_CTRL
:
191 case MESA_SHADER_TESS_EVAL
:
194 case MESA_SHADER_GEOMETRY
:
197 case MESA_SHADER_FRAGMENT
:
198 ish
->nos
|= IRIS_NOS_FRAMEBUFFER
|
199 IRIS_NOS_DEPTH_STENCIL_ALPHA
|
200 IRIS_NOS_RASTERIZER
|
203 /* The program key needs the VUE map if there are > 16 inputs */
204 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
205 BRW_FS_VARYING_INPUT_MASK
) > 16) {
206 ish
->nos
|= IRIS_NOS_LAST_VUE_MAP
;
209 case MESA_SHADER_COMPUTE
:
217 // XXX: disallow more than 64KB of shared variables
223 * The pipe->delete_[stage]_state() driver hooks.
225 * Frees the iris_uncompiled_shader.
228 iris_create_shader_state(struct pipe_context
*ctx
,
229 const struct pipe_shader_state
*state
)
231 assert(state
->type
== PIPE_SHADER_IR_NIR
);
233 return iris_create_uncompiled_shader(ctx
, state
->ir
.nir
,
234 &state
->stream_output
);
238 iris_create_compute_state(struct pipe_context
*ctx
,
239 const struct pipe_compute_state
*state
)
241 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
243 return iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
247 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
249 struct iris_uncompiled_shader
*ish
= state
;
251 ralloc_free(ish
->nir
);
256 * The pipe->bind_[stage]_state() driver hook.
258 * Binds an uncompiled shader as the current one for a particular stage.
259 * Updates dirty tracking to account for the shader's NOS.
262 bind_state(struct iris_context
*ice
,
263 struct iris_uncompiled_shader
*ish
,
264 gl_shader_stage stage
)
266 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
267 const uint64_t nos
= ish
? ish
->nos
: 0;
269 ice
->shaders
.uncompiled
[stage
] = ish
;
270 ice
->state
.dirty
|= dirty_bit
;
272 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
273 * (or that they no longer need to do so).
275 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
277 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
279 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
284 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
286 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
290 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
292 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
296 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
298 struct iris_context
*ice
= (struct iris_context
*)ctx
;
300 /* Enabling/disabling optional stages requires a URB reconfiguration. */
301 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
302 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
304 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
308 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
310 struct iris_context
*ice
= (struct iris_context
*)ctx
;
312 /* Enabling/disabling optional stages requires a URB reconfiguration. */
313 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
314 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
316 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
320 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
322 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
326 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
328 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
332 * Sets up the starting offsets for the groups of binding table entries
333 * common to all pipeline stages.
335 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
336 * unused but also make sure that addition of small offsets to them will
337 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
340 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
341 const struct nir_shader
*nir
,
342 struct brw_stage_prog_data
*prog_data
,
343 uint32_t next_binding_table_offset
)
345 const struct shader_info
*info
= &nir
->info
;
347 if (info
->num_textures
) {
348 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
349 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
350 next_binding_table_offset
+= info
->num_textures
;
352 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
353 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
356 if (info
->num_images
) {
357 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
358 next_binding_table_offset
+= info
->num_images
;
360 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
363 int num_ubos
= info
->num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
366 //assert(info->num_ubos <= BRW_MAX_UBO);
367 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
368 next_binding_table_offset
+= num_ubos
;
370 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
373 if (info
->num_ssbos
|| info
->num_abos
) {
374 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
375 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
376 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
378 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
381 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
383 /* This may or may not be used depending on how the compile goes. */
384 prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
385 next_binding_table_offset
++;
387 /* Plane 0 is just the regular texture section */
388 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
390 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
391 next_binding_table_offset
+= info
->num_textures
;
393 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
394 next_binding_table_offset
+= info
->num_textures
;
396 /* Set the binding table size */
397 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
399 return next_binding_table_offset
;
403 * Associate NIR uniform variables with the prog_data->param[] mechanism
404 * used by the backend. Also, decide which UBOs we'd like to push in an
405 * ideal situation (though the backend can reduce this).
408 iris_setup_uniforms(const struct brw_compiler
*compiler
,
411 struct brw_stage_prog_data
*prog_data
)
413 prog_data
->nr_params
= nir
->num_uniforms
;
414 /* The intel compiler assumes that num_uniforms is in bytes. For
415 * scalar that means 4 bytes per uniform slot.
417 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
419 nir
->num_uniforms
*= 4;
420 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
422 nir_foreach_variable(var
, &nir
->uniforms
) {
423 const unsigned components
= glsl_get_components(var
->type
);
425 for (unsigned i
= 0; i
< components
; i
++) {
426 prog_data
->param
[var
->data
.driver_location
] =
427 var
->data
.driver_location
;
431 // XXX: vs clip planes?
432 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
436 * If we still have regular uniforms as push constants after the backend
437 * compilation, set up a UBO range for them. This will be used to fill
438 * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
441 iris_setup_push_uniform_range(const struct brw_compiler
*compiler
,
442 struct brw_stage_prog_data
*prog_data
)
444 if (prog_data
->nr_params
) {
445 for (int i
= 3; i
> 0; i
--)
446 prog_data
->ubo_ranges
[i
] = prog_data
->ubo_ranges
[i
- 1];
448 prog_data
->ubo_ranges
[0] = (struct brw_ubo_range
) {
451 .length
= DIV_ROUND_UP(prog_data
->nr_params
, 8),
457 * Compile a vertex shader, and upload the assembly.
460 iris_compile_vs(struct iris_context
*ice
,
461 struct iris_uncompiled_shader
*ish
,
462 const struct brw_vs_prog_key
*key
)
464 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
465 const struct brw_compiler
*compiler
= screen
->compiler
;
466 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
467 void *mem_ctx
= ralloc_context(NULL
);
468 struct brw_vs_prog_data
*vs_prog_data
=
469 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
470 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
471 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
473 nir_shader
*nir
= ish
->nir
;
476 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
478 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
480 brw_compute_vue_map(devinfo
,
481 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
482 nir
->info
.separate_shader
);
484 char *error_str
= NULL
;
485 const unsigned *program
=
486 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, key
, vs_prog_data
,
487 nir
, -1, &error_str
);
488 if (program
== NULL
) {
489 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
490 ralloc_free(mem_ctx
);
494 iris_setup_push_uniform_range(compiler
, prog_data
);
497 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
498 &vue_prog_data
->vue_map
);
500 iris_upload_and_bind_shader(ice
, IRIS_CACHE_VS
, key
, program
, prog_data
,
503 ralloc_free(mem_ctx
);
508 * Update the current vertex shader variant.
510 * Fill out the key, look in the cache, compile and bind if needed.
513 iris_update_compiled_vs(struct iris_context
*ice
)
515 struct iris_uncompiled_shader
*ish
=
516 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
518 struct brw_vs_prog_key key
= { .program_string_id
= ish
->program_id
};
519 ice
->vtbl
.populate_vs_key(ice
, &key
);
521 if (iris_bind_cached_shader(ice
, IRIS_CACHE_VS
, &key
))
524 UNUSED
bool success
= iris_compile_vs(ice
, ish
, &key
);
528 * Get the shader_info for a given stage, or NULL if the stage is disabled.
530 const struct shader_info
*
531 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
533 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
538 const nir_shader
*nir
= ish
->nir
;
542 // XXX: this function is gross
544 iris_get_shader_num_ubos(const struct iris_context
*ice
, gl_shader_stage stage
)
546 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
549 const nir_shader
*nir
= ish
->nir
;
550 /* see assign_common_binding_table_offsets */
551 return nir
->info
.num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
557 * Get the union of TCS output and TES input slots.
559 * TCS and TES need to agree on a common URB entry layout. In particular,
560 * the data for all patch vertices is stored in a single URB entry (unlike
561 * GS which has one entry per input vertex). This means that per-vertex
562 * array indexing needs a stride.
564 * SSO requires locations to match, but doesn't require the number of
565 * outputs/inputs to match (in fact, the TCS often has extra outputs).
566 * So, we need to take the extra step of unifying these on the fly.
569 get_unified_tess_slots(const struct iris_context
*ice
,
570 uint64_t *per_vertex_slots
,
571 uint32_t *per_patch_slots
)
573 const struct shader_info
*tcs
=
574 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
575 const struct shader_info
*tes
=
576 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
578 *per_vertex_slots
= tes
->inputs_read
;
579 *per_patch_slots
= tes
->patch_inputs_read
;
582 *per_vertex_slots
|= tcs
->inputs_read
;
583 *per_patch_slots
|= tcs
->patch_inputs_read
;
588 * Compile a tessellation control shader, and upload the assembly.
591 iris_compile_tcs(struct iris_context
*ice
,
592 struct iris_uncompiled_shader
*ish
,
593 const struct brw_tcs_prog_key
*key
)
595 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
596 const struct brw_compiler
*compiler
= screen
->compiler
;
597 const struct nir_shader_compiler_options
*options
=
598 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
599 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
600 void *mem_ctx
= ralloc_context(NULL
);
601 struct brw_tcs_prog_data
*tcs_prog_data
=
602 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
603 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
604 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
611 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
612 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
614 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
616 /* Reserve space for passing the default tess levels as constants. */
617 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
618 prog_data
->nr_params
= 8;
619 prog_data
->ubo_ranges
[0].length
= 1;
622 char *error_str
= NULL
;
623 const unsigned *program
=
624 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
626 if (program
== NULL
) {
627 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
628 ralloc_free(mem_ctx
);
632 iris_setup_push_uniform_range(compiler
, prog_data
);
634 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TCS
, key
, program
, prog_data
,
637 ralloc_free(mem_ctx
);
642 * Update the current tessellation control shader variant.
644 * Fill out the key, look in the cache, compile and bind if needed.
647 iris_update_compiled_tcs(struct iris_context
*ice
)
649 struct iris_uncompiled_shader
*tcs
=
650 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
652 const struct shader_info
*tes_info
=
653 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
654 struct brw_tcs_prog_key key
= {
655 .program_string_id
= tcs
? tcs
->program_id
: 0,
656 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
657 .input_vertices
= ice
->state
.vertices_per_patch
,
659 get_unified_tess_slots(ice
, &key
.outputs_written
,
660 &key
.patch_outputs_written
);
661 ice
->vtbl
.populate_tcs_key(ice
, &key
);
663 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TCS
, &key
))
666 UNUSED
bool success
= iris_compile_tcs(ice
, tcs
, &key
);
670 * Compile a tessellation evaluation shader, and upload the assembly.
673 iris_compile_tes(struct iris_context
*ice
,
674 struct iris_uncompiled_shader
*ish
,
675 const struct brw_tes_prog_key
*key
)
677 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
678 const struct brw_compiler
*compiler
= screen
->compiler
;
679 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
680 void *mem_ctx
= ralloc_context(NULL
);
681 struct brw_tes_prog_data
*tes_prog_data
=
682 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
683 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
684 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
686 nir_shader
*nir
= ish
->nir
;
688 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
690 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
692 struct brw_vue_map input_vue_map
;
693 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
694 key
->patch_inputs_read
);
696 char *error_str
= NULL
;
697 const unsigned *program
=
698 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
699 tes_prog_data
, nir
, NULL
, -1, &error_str
);
700 if (program
== NULL
) {
701 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
702 ralloc_free(mem_ctx
);
706 iris_setup_push_uniform_range(compiler
, prog_data
);
709 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
710 &vue_prog_data
->vue_map
);
712 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TES
, key
, program
, prog_data
,
715 ralloc_free(mem_ctx
);
720 * Update the current tessellation evaluation shader variant.
722 * Fill out the key, look in the cache, compile and bind if needed.
725 iris_update_compiled_tes(struct iris_context
*ice
)
727 struct iris_uncompiled_shader
*ish
=
728 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
730 struct brw_tes_prog_key key
= { .program_string_id
= ish
->program_id
};
731 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
732 ice
->vtbl
.populate_tes_key(ice
, &key
);
734 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TES
, &key
))
737 UNUSED
bool success
= iris_compile_tes(ice
, ish
, &key
);
741 * Compile a geometry shader, and upload the assembly.
744 iris_compile_gs(struct iris_context
*ice
,
745 struct iris_uncompiled_shader
*ish
,
746 const struct brw_gs_prog_key
*key
)
748 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
749 const struct brw_compiler
*compiler
= screen
->compiler
;
750 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
751 void *mem_ctx
= ralloc_context(NULL
);
752 struct brw_gs_prog_data
*gs_prog_data
=
753 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
754 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
755 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
757 nir_shader
*nir
= ish
->nir
;
759 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
761 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
763 brw_compute_vue_map(devinfo
,
764 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
765 nir
->info
.separate_shader
);
767 char *error_str
= NULL
;
768 const unsigned *program
=
769 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
770 NULL
, -1, &error_str
);
771 if (program
== NULL
) {
772 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
773 ralloc_free(mem_ctx
);
777 iris_setup_push_uniform_range(compiler
, prog_data
);
780 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
781 &vue_prog_data
->vue_map
);
783 iris_upload_and_bind_shader(ice
, IRIS_CACHE_GS
, key
, program
, prog_data
,
786 ralloc_free(mem_ctx
);
791 * Update the current geometry shader variant.
793 * Fill out the key, look in the cache, compile and bind if needed.
796 iris_update_compiled_gs(struct iris_context
*ice
)
798 struct iris_uncompiled_shader
*ish
=
799 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
802 iris_unbind_shader(ice
, IRIS_CACHE_GS
);
806 struct brw_gs_prog_key key
= { .program_string_id
= ish
->program_id
};
807 ice
->vtbl
.populate_gs_key(ice
, &key
);
809 if (iris_bind_cached_shader(ice
, IRIS_CACHE_GS
, &key
))
812 UNUSED
bool success
= iris_compile_gs(ice
, ish
, &key
);
816 * Compile a fragment (pixel) shader, and upload the assembly.
819 iris_compile_fs(struct iris_context
*ice
,
820 struct iris_uncompiled_shader
*ish
,
821 const struct brw_wm_prog_key
*key
,
822 struct brw_vue_map
*vue_map
)
824 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
825 const struct brw_compiler
*compiler
= screen
->compiler
;
826 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
827 void *mem_ctx
= ralloc_context(NULL
);
828 struct brw_wm_prog_data
*fs_prog_data
=
829 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
830 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
832 nir_shader
*nir
= ish
->nir
;
835 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
836 MAX2(key
->nr_color_regions
, 1));
838 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
840 char *error_str
= NULL
;
841 const unsigned *program
=
842 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
843 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
844 if (program
== NULL
) {
845 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
846 ralloc_free(mem_ctx
);
850 //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
852 iris_setup_push_uniform_range(compiler
, prog_data
);
854 iris_upload_and_bind_shader(ice
, IRIS_CACHE_FS
, key
, program
, prog_data
,
857 ralloc_free(mem_ctx
);
862 * Update the current fragment shader variant.
864 * Fill out the key, look in the cache, compile and bind if needed.
867 iris_update_compiled_fs(struct iris_context
*ice
)
869 struct iris_uncompiled_shader
*ish
=
870 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
871 struct brw_wm_prog_key key
= { .program_string_id
= ish
->program_id
};
872 ice
->vtbl
.populate_fs_key(ice
, &key
);
874 if (ish
->nos
& IRIS_NOS_LAST_VUE_MAP
)
875 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
877 if (iris_bind_cached_shader(ice
, IRIS_CACHE_FS
, &key
))
880 UNUSED
bool success
=
881 iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
885 * Get the compiled shader for the last enabled geometry stage.
887 * This stage is the one which will feed stream output and the rasterizer.
889 static struct iris_compiled_shader
*
890 last_vue_shader(struct iris_context
*ice
)
892 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
893 return ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
895 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
896 return ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
898 return ice
->shaders
.prog
[MESA_SHADER_VERTEX
];
902 * Update the last enabled stage's VUE map.
904 * When the shader feeding the rasterizer's output interface changes, we
905 * need to re-emit various packets.
908 update_last_vue_map(struct iris_context
*ice
,
909 struct brw_stage_prog_data
*prog_data
)
911 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
912 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
913 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
914 const uint64_t changed_slots
=
915 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
917 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
918 // XXX: could use ctx->Const.MaxViewports for old API efficiency
919 ice
->state
.num_viewports
=
920 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
921 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
922 IRIS_DIRTY_SF_CL_VIEWPORT
|
923 IRIS_DIRTY_SCISSOR_RECT
|
924 IRIS_DIRTY_UNCOMPILED_FS
|
925 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
929 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
930 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
933 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
937 * Get the prog_data for a given stage, or NULL if the stage is disabled.
939 static struct brw_vue_prog_data
*
940 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
942 if (!ice
->shaders
.prog
[stage
])
945 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
949 * Update the current shader variants for the given state.
951 * This should be called on every draw call to ensure that the correct
952 * shaders are bound. It will also flag any dirty state triggered by
953 * swapping out those shaders.
956 iris_update_compiled_shaders(struct iris_context
*ice
)
958 const uint64_t dirty
= ice
->state
.dirty
;
960 struct brw_vue_prog_data
*old_prog_datas
[4];
961 if (!(dirty
& IRIS_DIRTY_URB
)) {
962 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
963 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
966 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
967 struct iris_uncompiled_shader
*tes
=
968 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
970 iris_update_compiled_tcs(ice
);
971 iris_update_compiled_tes(ice
);
973 iris_unbind_shader(ice
, IRIS_CACHE_TCS
);
974 iris_unbind_shader(ice
, IRIS_CACHE_TES
);
978 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
979 iris_update_compiled_vs(ice
);
980 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
981 iris_update_compiled_gs(ice
);
983 struct iris_compiled_shader
*shader
= last_vue_shader(ice
);
984 update_last_vue_map(ice
, shader
->prog_data
);
985 if (ice
->state
.streamout
!= shader
->streamout
) {
986 ice
->state
.streamout
= shader
->streamout
;
987 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
990 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
991 iris_update_compiled_fs(ice
);
994 /* Changing shader interfaces may require a URB configuration. */
995 if (!(dirty
& IRIS_DIRTY_URB
)) {
996 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
997 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
998 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
999 if (!!old
!= !!new ||
1000 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1001 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1009 iris_compile_cs(struct iris_context
*ice
,
1010 struct iris_uncompiled_shader
*ish
,
1011 const struct brw_cs_prog_key
*key
)
1013 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1014 const struct brw_compiler
*compiler
= screen
->compiler
;
1015 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1016 void *mem_ctx
= ralloc_context(NULL
);
1017 struct brw_cs_prog_data
*cs_prog_data
=
1018 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1019 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1021 nir_shader
*nir
= ish
->nir
;
1023 cs_prog_data
->binding_table
.work_groups_start
= 0;
1024 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1);
1026 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
1028 char *error_str
= NULL
;
1029 const unsigned *program
=
1030 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1031 nir
, -1, &error_str
);
1032 if (program
== NULL
) {
1033 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1034 ralloc_free(mem_ctx
);
1038 iris_upload_and_bind_shader(ice
, IRIS_CACHE_CS
, key
, program
, prog_data
,
1041 ralloc_free(mem_ctx
);
1046 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1048 struct iris_uncompiled_shader
*ish
=
1049 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1051 struct brw_cs_prog_key key
= { .program_string_id
= ish
->program_id
};
1052 ice
->vtbl
.populate_cs_key(ice
, &key
);
1054 if (iris_bind_cached_shader(ice
, IRIS_CACHE_CS
, &key
))
1057 UNUSED
bool success
= iris_compile_cs(ice
, ish
, &key
);
1061 iris_init_program_functions(struct pipe_context
*ctx
)
1063 ctx
->create_vs_state
= iris_create_shader_state
;
1064 ctx
->create_tcs_state
= iris_create_shader_state
;
1065 ctx
->create_tes_state
= iris_create_shader_state
;
1066 ctx
->create_gs_state
= iris_create_shader_state
;
1067 ctx
->create_fs_state
= iris_create_shader_state
;
1068 ctx
->create_compute_state
= iris_create_compute_state
;
1070 ctx
->delete_vs_state
= iris_delete_shader_state
;
1071 ctx
->delete_tcs_state
= iris_delete_shader_state
;
1072 ctx
->delete_tes_state
= iris_delete_shader_state
;
1073 ctx
->delete_gs_state
= iris_delete_shader_state
;
1074 ctx
->delete_fs_state
= iris_delete_shader_state
;
1075 ctx
->delete_compute_state
= iris_delete_shader_state
;
1077 ctx
->bind_vs_state
= iris_bind_vs_state
;
1078 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1079 ctx
->bind_tes_state
= iris_bind_tes_state
;
1080 ctx
->bind_gs_state
= iris_bind_gs_state
;
1081 ctx
->bind_fs_state
= iris_bind_fs_state
;
1082 ctx
->bind_compute_state
= iris_bind_cs_state
;