2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
44 #include "nir/tgsi_to_nir.h"
46 #define KEY_INIT_NO_ID(gen) \
47 .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
48 .tex.compressed_multisample_layout_mask = ~0, \
49 .tex.msaa_16 = (gen >= 9 ? ~0 : 0)
50 #define KEY_INIT(gen) .program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
53 get_new_program_id(struct iris_screen
*screen
)
55 return p_atomic_inc_return(&screen
->program_id
);
59 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
60 * It primarily contains the NIR for the shader.
62 * Each API-facing shader can be compiled into multiple shader variants,
63 * based on non-orthogonal state dependencies, recorded in the shader key.
65 * See iris_compiled_shader, which represents a compiled shader variant.
67 struct iris_uncompiled_shader
{
70 struct pipe_stream_output_info stream_output
;
74 /** Bitfield of (1 << IRIS_NOS_*) flags. */
77 /** Have any shader variants been compiled yet? */
82 get_aoa_deref_offset(nir_builder
*b
,
83 nir_deref_instr
*deref
,
86 unsigned array_size
= elem_size
;
87 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
89 while (deref
->deref_type
!= nir_deref_type_var
) {
90 assert(deref
->deref_type
== nir_deref_type_array
);
92 /* This level's element size is the previous level's array size */
93 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
94 assert(deref
->arr
.index
.ssa
);
95 offset
= nir_iadd(b
, offset
,
96 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
98 deref
= nir_deref_instr_parent(deref
);
99 assert(glsl_type_is_array(deref
->type
));
100 array_size
*= glsl_get_length(deref
->type
);
103 /* Accessing an invalid surface index with the dataport can result in a
104 * hang. According to the spec "if the index used to select an individual
105 * element is negative or greater than or equal to the size of the array,
106 * the results of the operation are undefined but may not lead to
107 * termination" -- which is one of the possible outcomes of the hang.
108 * Clamp the index to prevent access outside of the array bounds.
110 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
114 iris_lower_storage_image_derefs(nir_shader
*nir
)
116 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
119 nir_builder_init(&b
, impl
);
121 nir_foreach_block(block
, impl
) {
122 nir_foreach_instr_safe(instr
, block
) {
123 if (instr
->type
!= nir_instr_type_intrinsic
)
126 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
127 switch (intrin
->intrinsic
) {
128 case nir_intrinsic_image_deref_load
:
129 case nir_intrinsic_image_deref_store
:
130 case nir_intrinsic_image_deref_atomic_add
:
131 case nir_intrinsic_image_deref_atomic_min
:
132 case nir_intrinsic_image_deref_atomic_max
:
133 case nir_intrinsic_image_deref_atomic_and
:
134 case nir_intrinsic_image_deref_atomic_or
:
135 case nir_intrinsic_image_deref_atomic_xor
:
136 case nir_intrinsic_image_deref_atomic_exchange
:
137 case nir_intrinsic_image_deref_atomic_comp_swap
:
138 case nir_intrinsic_image_deref_size
:
139 case nir_intrinsic_image_deref_samples
:
140 case nir_intrinsic_image_deref_load_raw_intel
:
141 case nir_intrinsic_image_deref_store_raw_intel
: {
142 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
143 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
145 b
.cursor
= nir_before_instr(&intrin
->instr
);
147 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
148 get_aoa_deref_offset(&b
, deref
, 1));
149 brw_nir_rewrite_image_intrinsic(intrin
, index
);
160 // XXX: need unify_interfaces() at link time...
163 * Fix an uncompiled shader's stream output info.
165 * Core Gallium stores output->register_index as a "slot" number, where
166 * slots are assigned consecutively to all outputs in info->outputs_written.
167 * This naive packing of outputs doesn't work for us - we too have slots,
168 * but the layout is defined by the VUE map, which we won't have until we
169 * compile a specific shader variant. So, we remap these and simply store
170 * VARYING_SLOT_* in our copy's output->register_index fields.
172 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
173 * components of our VUE header. See brw_vue_map.c for the layout.
176 update_so_info(struct pipe_stream_output_info
*so_info
,
177 uint64_t outputs_written
)
179 uint8_t reverse_map
[64] = {};
181 while (outputs_written
) {
182 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
185 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
186 struct pipe_stream_output
*output
= &so_info
->output
[i
];
188 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
189 output
->register_index
= reverse_map
[output
->register_index
];
191 /* The VUE header contains three scalar fields packed together:
192 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
193 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
194 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
196 switch (output
->register_index
) {
197 case VARYING_SLOT_LAYER
:
198 assert(output
->num_components
== 1);
199 output
->register_index
= VARYING_SLOT_PSIZ
;
200 output
->start_component
= 1;
202 case VARYING_SLOT_VIEWPORT
:
203 assert(output
->num_components
== 1);
204 output
->register_index
= VARYING_SLOT_PSIZ
;
205 output
->start_component
= 2;
207 case VARYING_SLOT_PSIZ
:
208 assert(output
->num_components
== 1);
209 output
->start_component
= 3;
213 //info->outputs_written |= 1ull << output->register_index;
218 * Sets up the starting offsets for the groups of binding table entries
219 * common to all pipeline stages.
221 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
222 * unused but also make sure that addition of small offsets to them will
223 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
226 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
227 const struct nir_shader
*nir
,
228 struct brw_stage_prog_data
*prog_data
,
229 uint32_t next_binding_table_offset
,
230 unsigned num_system_values
,
233 const struct shader_info
*info
= &nir
->info
;
235 unsigned num_textures
= util_last_bit(info
->textures_used
);
238 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
239 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
240 next_binding_table_offset
+= num_textures
;
242 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
243 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
246 if (info
->num_images
) {
247 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
248 next_binding_table_offset
+= info
->num_images
;
250 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
254 //assert(info->num_ubos <= BRW_MAX_UBO);
255 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
256 next_binding_table_offset
+= num_cbufs
;
258 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
261 if (info
->num_ssbos
|| info
->num_abos
) {
262 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
263 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
264 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
266 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
269 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
271 /* Plane 0 is just the regular texture section */
272 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
274 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
275 next_binding_table_offset
+= num_textures
;
277 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
278 next_binding_table_offset
+= num_textures
;
280 /* Set the binding table size */
281 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
283 return next_binding_table_offset
;
287 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
288 unsigned offset
, unsigned n
)
290 assert(offset
% sizeof(uint32_t) == 0);
292 for (unsigned i
= 0; i
< n
; ++i
)
293 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
295 for (unsigned i
= n
; i
< 4; ++i
)
296 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
300 * Associate NIR uniform variables with the prog_data->param[] mechanism
301 * used by the backend. Also, decide which UBOs we'd like to push in an
302 * ideal situation (though the backend can reduce this).
305 iris_setup_uniforms(const struct brw_compiler
*compiler
,
308 struct brw_stage_prog_data
*prog_data
,
309 enum brw_param_builtin
**out_system_values
,
310 unsigned *out_num_system_values
,
311 unsigned *out_num_cbufs
)
313 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
315 /* The intel compiler assumes that num_uniforms is in bytes. For
316 * scalar that means 4 bytes per uniform slot.
318 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
320 nir
->num_uniforms
*= 4;
322 const unsigned IRIS_MAX_SYSTEM_VALUES
=
323 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
324 enum brw_param_builtin
*system_values
=
325 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
326 unsigned num_system_values
= 0;
328 unsigned patch_vert_idx
= -1;
329 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
330 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
331 memset(ucp_idx
, -1, sizeof(ucp_idx
));
332 memset(img_idx
, -1, sizeof(img_idx
));
334 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
337 nir_builder_init(&b
, impl
);
339 b
.cursor
= nir_before_block(nir_start_block(impl
));
340 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
342 /* Turn system value intrinsics into uniforms */
343 nir_foreach_block(block
, impl
) {
344 nir_foreach_instr_safe(instr
, block
) {
345 if (instr
->type
!= nir_instr_type_intrinsic
)
348 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
351 switch (intrin
->intrinsic
) {
352 case nir_intrinsic_load_user_clip_plane
: {
353 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
355 if (ucp_idx
[ucp
] == -1) {
356 ucp_idx
[ucp
] = num_system_values
;
357 num_system_values
+= 4;
360 for (int i
= 0; i
< 4; i
++) {
361 system_values
[ucp_idx
[ucp
] + i
] =
362 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
365 b
.cursor
= nir_before_instr(instr
);
366 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
369 case nir_intrinsic_load_patch_vertices_in
:
370 if (patch_vert_idx
== -1)
371 patch_vert_idx
= num_system_values
++;
373 system_values
[patch_vert_idx
] =
374 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
376 b
.cursor
= nir_before_instr(instr
);
377 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
379 case nir_intrinsic_image_deref_load_param_intel
: {
380 assert(devinfo
->gen
< 9);
381 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
382 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
384 /* XXX: var->data.binding is not set properly. We need to run
385 * some form of gl_nir_lower_samplers_as_deref() to get it.
386 * This breaks tests which use more than one image.
388 if (img_idx
[var
->data
.binding
] == -1) {
389 /* GL only allows arrays of arrays of images. */
390 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
391 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
393 for (int i
= 0; i
< num_images
; i
++) {
394 const unsigned img
= var
->data
.binding
+ i
;
396 img_idx
[img
] = num_system_values
;
397 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
399 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
401 setup_vec4_image_sysval(
402 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
403 offsetof(struct brw_image_param
, offset
), 2);
404 setup_vec4_image_sysval(
405 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
406 offsetof(struct brw_image_param
, size
), 3);
407 setup_vec4_image_sysval(
408 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
409 offsetof(struct brw_image_param
, stride
), 4);
410 setup_vec4_image_sysval(
411 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
412 offsetof(struct brw_image_param
, tiling
), 3);
413 setup_vec4_image_sysval(
414 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
415 offsetof(struct brw_image_param
, swizzling
), 2);
419 b
.cursor
= nir_before_instr(instr
);
420 offset
= nir_iadd(&b
,
421 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
422 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
423 nir_intrinsic_base(intrin
) * 16));
430 unsigned comps
= nir_intrinsic_dest_components(intrin
);
432 nir_intrinsic_instr
*load
=
433 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
434 load
->num_components
= comps
;
435 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
436 load
->src
[1] = nir_src_for_ssa(offset
);
437 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
438 nir_builder_instr_insert(&b
, &load
->instr
);
439 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
440 nir_src_for_ssa(&load
->dest
.ssa
));
441 nir_instr_remove(instr
);
445 nir_validate_shader(nir
, "before remapping");
447 /* Place the new params at the front of constant buffer 0. */
448 if (num_system_values
> 0) {
449 nir
->num_uniforms
+= num_system_values
* sizeof(uint32_t);
451 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
454 nir_foreach_block(block
, impl
) {
455 nir_foreach_instr_safe(instr
, block
) {
456 if (instr
->type
!= nir_instr_type_intrinsic
)
459 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
461 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
464 b
.cursor
= nir_before_instr(instr
);
466 assert(load
->src
[0].is_ssa
);
468 if (load
->src
[0].ssa
== temp_ubo_name
) {
469 nir_instr_rewrite_src(instr
, &load
->src
[0],
470 nir_src_for_ssa(nir_imm_int(&b
, 0)));
471 } else if (nir_src_as_uint(load
->src
[0]) == 0) {
472 nir_ssa_def
*offset
=
473 nir_iadd(&b
, load
->src
[1].ssa
,
474 nir_imm_int(&b
, 4 * num_system_values
));
475 nir_instr_rewrite_src(instr
, &load
->src
[1],
476 nir_src_for_ssa(offset
));
481 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
482 nir_opt_constant_folding(nir
);
484 ralloc_free(system_values
);
485 system_values
= NULL
;
488 nir_validate_shader(nir
, "after remap");
490 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
491 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
493 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
494 * about it for compute shaders, so go ahead and make some fake ones
495 * which the backend will dead code eliminate.
497 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
498 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
500 /* System values and uniforms are stored in constant buffer 0, the
501 * user-facing UBOs are indexed by one. So if any constant buffer is
502 * needed, the constant buffer 0 will be needed, so account for it.
504 unsigned num_cbufs
= nir
->info
.num_ubos
;
505 if (num_cbufs
|| num_system_values
|| nir
->num_uniforms
)
508 *out_system_values
= system_values
;
509 *out_num_system_values
= num_system_values
;
510 *out_num_cbufs
= num_cbufs
;
514 * Compile a vertex shader, and upload the assembly.
516 static struct iris_compiled_shader
*
517 iris_compile_vs(struct iris_context
*ice
,
518 struct iris_uncompiled_shader
*ish
,
519 const struct brw_vs_prog_key
*key
)
521 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
522 const struct brw_compiler
*compiler
= screen
->compiler
;
523 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
524 void *mem_ctx
= ralloc_context(NULL
);
525 struct brw_vs_prog_data
*vs_prog_data
=
526 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
527 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
528 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
529 enum brw_param_builtin
*system_values
;
530 unsigned num_system_values
;
533 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
535 if (key
->nr_userclip_plane_consts
) {
536 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
537 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
538 nir_lower_io_to_temporaries(nir
, impl
, true, false);
539 nir_lower_global_vars_to_local(nir
);
540 nir_lower_vars_to_ssa(nir
);
541 nir_shader_gather_info(nir
, impl
);
544 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
545 prog_data
->use_alt_mode
= true;
547 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
548 &num_system_values
, &num_cbufs
);
550 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
551 num_system_values
, num_cbufs
);
553 brw_compute_vue_map(devinfo
,
554 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
555 nir
->info
.separate_shader
);
557 /* Don't tell the backend about our clip plane constants, we've already
558 * lowered them in NIR and we don't want it doing it again.
560 struct brw_vs_prog_key key_no_ucp
= *key
;
561 key_no_ucp
.nr_userclip_plane_consts
= 0;
563 char *error_str
= NULL
;
564 const unsigned *program
=
565 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
566 nir
, -1, &error_str
);
567 if (program
== NULL
) {
568 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
569 ralloc_free(mem_ctx
);
574 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
575 &vue_prog_data
->vue_map
);
577 struct iris_compiled_shader
*shader
=
578 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
579 prog_data
, so_decls
, system_values
, num_system_values
,
582 if (ish
->compiled_once
) {
583 perf_debug(&ice
->dbg
, "Recompiling vertex shader\n");
585 ish
->compiled_once
= true;
588 ralloc_free(mem_ctx
);
593 * Update the current vertex shader variant.
595 * Fill out the key, look in the cache, compile and bind if needed.
598 iris_update_compiled_vs(struct iris_context
*ice
)
600 struct iris_uncompiled_shader
*ish
=
601 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
602 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
603 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
605 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
606 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
608 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
609 struct iris_compiled_shader
*shader
=
610 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
613 shader
= iris_compile_vs(ice
, ish
, &key
);
616 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
617 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
618 IRIS_DIRTY_BINDINGS_VS
|
619 IRIS_DIRTY_CONSTANTS_VS
|
621 const struct brw_vs_prog_data
*vs_prog_data
=
622 (void *) shader
->prog_data
;
623 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
624 vs_prog_data
->uses_baseinstance
;
625 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
626 vs_prog_data
->uses_is_indexed_draw
;
627 const bool needs_sgvs_element
= uses_draw_params
||
628 vs_prog_data
->uses_instanceid
||
629 vs_prog_data
->uses_vertexid
;
630 bool needs_edge_flag
= false;
631 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
632 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
633 needs_edge_flag
= true;
636 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
637 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
638 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
639 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
640 IRIS_DIRTY_VERTEX_ELEMENTS
;
642 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
643 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
644 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
645 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
650 * Get the shader_info for a given stage, or NULL if the stage is disabled.
652 const struct shader_info
*
653 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
655 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
660 const nir_shader
*nir
= ish
->nir
;
665 * Get the union of TCS output and TES input slots.
667 * TCS and TES need to agree on a common URB entry layout. In particular,
668 * the data for all patch vertices is stored in a single URB entry (unlike
669 * GS which has one entry per input vertex). This means that per-vertex
670 * array indexing needs a stride.
672 * SSO requires locations to match, but doesn't require the number of
673 * outputs/inputs to match (in fact, the TCS often has extra outputs).
674 * So, we need to take the extra step of unifying these on the fly.
677 get_unified_tess_slots(const struct iris_context
*ice
,
678 uint64_t *per_vertex_slots
,
679 uint32_t *per_patch_slots
)
681 const struct shader_info
*tcs
=
682 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
683 const struct shader_info
*tes
=
684 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
686 *per_vertex_slots
= tes
->inputs_read
;
687 *per_patch_slots
= tes
->patch_inputs_read
;
690 *per_vertex_slots
|= tcs
->outputs_written
;
691 *per_patch_slots
|= tcs
->patch_outputs_written
;
696 * Compile a tessellation control shader, and upload the assembly.
698 static struct iris_compiled_shader
*
699 iris_compile_tcs(struct iris_context
*ice
,
700 struct iris_uncompiled_shader
*ish
,
701 const struct brw_tcs_prog_key
*key
)
703 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
704 const struct brw_compiler
*compiler
= screen
->compiler
;
705 const struct nir_shader_compiler_options
*options
=
706 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
707 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
708 void *mem_ctx
= ralloc_context(NULL
);
709 struct brw_tcs_prog_data
*tcs_prog_data
=
710 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
711 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
712 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
713 enum brw_param_builtin
*system_values
= NULL
;
714 unsigned num_system_values
= 0;
720 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
722 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
723 &num_system_values
, &num_cbufs
);
724 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
725 num_system_values
, num_cbufs
);
727 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
729 /* Reserve space for passing the default tess levels as constants. */
730 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
731 prog_data
->nr_params
= 8;
732 prog_data
->ubo_ranges
[0].length
= 1;
735 char *error_str
= NULL
;
736 const unsigned *program
=
737 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
739 if (program
== NULL
) {
740 dbg_printf("Failed to compile control shader: %s\n", error_str
);
741 ralloc_free(mem_ctx
);
745 struct iris_compiled_shader
*shader
=
746 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
747 prog_data
, NULL
, system_values
, num_system_values
,
751 if (ish
->compiled_once
) {
752 perf_debug(&ice
->dbg
, "Recompiling tessellation control shader\n");
754 ish
->compiled_once
= true;
758 ralloc_free(mem_ctx
);
763 * Update the current tessellation control shader variant.
765 * Fill out the key, look in the cache, compile and bind if needed.
768 iris_update_compiled_tcs(struct iris_context
*ice
)
770 struct iris_uncompiled_shader
*tcs
=
771 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
772 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
773 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
775 const struct shader_info
*tes_info
=
776 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
777 struct brw_tcs_prog_key key
= {
778 KEY_INIT_NO_ID(devinfo
->gen
),
779 .program_string_id
= tcs
? tcs
->program_id
: 0,
780 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
781 .input_vertices
= ice
->state
.vertices_per_patch
,
783 get_unified_tess_slots(ice
, &key
.outputs_written
,
784 &key
.patch_outputs_written
);
785 ice
->vtbl
.populate_tcs_key(ice
, &key
);
787 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
788 struct iris_compiled_shader
*shader
=
789 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
792 shader
= iris_compile_tcs(ice
, tcs
, &key
);
795 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
796 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
797 IRIS_DIRTY_BINDINGS_TCS
|
798 IRIS_DIRTY_CONSTANTS_TCS
;
803 * Compile a tessellation evaluation shader, and upload the assembly.
805 static struct iris_compiled_shader
*
806 iris_compile_tes(struct iris_context
*ice
,
807 struct iris_uncompiled_shader
*ish
,
808 const struct brw_tes_prog_key
*key
)
810 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
811 const struct brw_compiler
*compiler
= screen
->compiler
;
812 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
813 void *mem_ctx
= ralloc_context(NULL
);
814 struct brw_tes_prog_data
*tes_prog_data
=
815 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
816 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
817 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
818 enum brw_param_builtin
*system_values
;
819 unsigned num_system_values
;
822 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
824 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
825 &num_system_values
, &num_cbufs
);
827 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
828 num_system_values
, num_cbufs
);
830 struct brw_vue_map input_vue_map
;
831 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
832 key
->patch_inputs_read
);
834 char *error_str
= NULL
;
835 const unsigned *program
=
836 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
837 tes_prog_data
, nir
, NULL
, -1, &error_str
);
838 if (program
== NULL
) {
839 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
840 ralloc_free(mem_ctx
);
845 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
846 &vue_prog_data
->vue_map
);
849 struct iris_compiled_shader
*shader
=
850 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
851 prog_data
, so_decls
, system_values
, num_system_values
,
854 if (ish
->compiled_once
) {
855 perf_debug(&ice
->dbg
, "Recompiling tessellation evaluation shader\n");
857 ish
->compiled_once
= true;
860 ralloc_free(mem_ctx
);
865 * Update the current tessellation evaluation shader variant.
867 * Fill out the key, look in the cache, compile and bind if needed.
870 iris_update_compiled_tes(struct iris_context
*ice
)
872 struct iris_uncompiled_shader
*ish
=
873 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
874 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
875 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
877 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
878 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
879 ice
->vtbl
.populate_tes_key(ice
, &key
);
881 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
882 struct iris_compiled_shader
*shader
=
883 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
886 shader
= iris_compile_tes(ice
, ish
, &key
);
889 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
890 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
891 IRIS_DIRTY_BINDINGS_TES
|
892 IRIS_DIRTY_CONSTANTS_TES
;
897 * Compile a geometry shader, and upload the assembly.
899 static struct iris_compiled_shader
*
900 iris_compile_gs(struct iris_context
*ice
,
901 struct iris_uncompiled_shader
*ish
,
902 const struct brw_gs_prog_key
*key
)
904 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
905 const struct brw_compiler
*compiler
= screen
->compiler
;
906 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
907 void *mem_ctx
= ralloc_context(NULL
);
908 struct brw_gs_prog_data
*gs_prog_data
=
909 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
910 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
911 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
912 enum brw_param_builtin
*system_values
;
913 unsigned num_system_values
;
916 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
918 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
919 &num_system_values
, &num_cbufs
);
921 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0,
922 num_system_values
, num_cbufs
);
924 brw_compute_vue_map(devinfo
,
925 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
926 nir
->info
.separate_shader
);
928 char *error_str
= NULL
;
929 const unsigned *program
=
930 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
931 NULL
, -1, &error_str
);
932 if (program
== NULL
) {
933 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
934 ralloc_free(mem_ctx
);
939 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
940 &vue_prog_data
->vue_map
);
942 struct iris_compiled_shader
*shader
=
943 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
944 prog_data
, so_decls
, system_values
, num_system_values
,
947 if (ish
->compiled_once
) {
948 perf_debug(&ice
->dbg
, "Recompiling geometry shader\n");
950 ish
->compiled_once
= true;
953 ralloc_free(mem_ctx
);
958 * Update the current geometry shader variant.
960 * Fill out the key, look in the cache, compile and bind if needed.
963 iris_update_compiled_gs(struct iris_context
*ice
)
965 struct iris_uncompiled_shader
*ish
=
966 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
967 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
968 struct iris_compiled_shader
*shader
= NULL
;
971 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
972 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
973 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
974 ice
->vtbl
.populate_gs_key(ice
, &key
);
977 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
980 shader
= iris_compile_gs(ice
, ish
, &key
);
984 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
985 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
986 IRIS_DIRTY_BINDINGS_GS
|
987 IRIS_DIRTY_CONSTANTS_GS
;
992 * Compile a fragment (pixel) shader, and upload the assembly.
994 static struct iris_compiled_shader
*
995 iris_compile_fs(struct iris_context
*ice
,
996 struct iris_uncompiled_shader
*ish
,
997 const struct brw_wm_prog_key
*key
,
998 struct brw_vue_map
*vue_map
)
1000 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1001 const struct brw_compiler
*compiler
= screen
->compiler
;
1002 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1003 void *mem_ctx
= ralloc_context(NULL
);
1004 struct brw_wm_prog_data
*fs_prog_data
=
1005 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1006 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1007 enum brw_param_builtin
*system_values
;
1008 unsigned num_system_values
;
1011 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1013 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1014 prog_data
->use_alt_mode
= true;
1016 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1017 &num_system_values
, &num_cbufs
);
1019 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
1020 MAX2(key
->nr_color_regions
, 1),
1021 num_system_values
, num_cbufs
);
1022 char *error_str
= NULL
;
1023 const unsigned *program
=
1024 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1025 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1026 if (program
== NULL
) {
1027 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1028 ralloc_free(mem_ctx
);
1032 struct iris_compiled_shader
*shader
=
1033 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1034 prog_data
, NULL
, system_values
, num_system_values
,
1037 if (ish
->compiled_once
) {
1038 perf_debug(&ice
->dbg
, "Recompiling fragment shader\n");
1040 ish
->compiled_once
= true;
1043 ralloc_free(mem_ctx
);
1048 * Update the current fragment shader variant.
1050 * Fill out the key, look in the cache, compile and bind if needed.
1053 iris_update_compiled_fs(struct iris_context
*ice
)
1055 struct iris_uncompiled_shader
*ish
=
1056 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1057 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1058 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1059 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1060 ice
->vtbl
.populate_fs_key(ice
, &key
);
1062 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1063 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1065 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1066 struct iris_compiled_shader
*shader
=
1067 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1070 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1072 if (old
!= shader
) {
1073 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1074 // toggles. might be able to avoid flagging SBE too.
1075 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1076 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1077 IRIS_DIRTY_BINDINGS_FS
|
1078 IRIS_DIRTY_CONSTANTS_FS
|
1086 * Get the compiled shader for the last enabled geometry stage.
1088 * This stage is the one which will feed stream output and the rasterizer.
1090 static gl_shader_stage
1091 last_vue_stage(struct iris_context
*ice
)
1093 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
1094 return MESA_SHADER_GEOMETRY
;
1096 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
1097 return MESA_SHADER_TESS_EVAL
;
1099 return MESA_SHADER_VERTEX
;
1103 * Update the last enabled stage's VUE map.
1105 * When the shader feeding the rasterizer's output interface changes, we
1106 * need to re-emit various packets.
1109 update_last_vue_map(struct iris_context
*ice
,
1110 struct brw_stage_prog_data
*prog_data
)
1112 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1113 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1114 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1115 const uint64_t changed_slots
=
1116 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1118 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1119 // XXX: could use ctx->Const.MaxViewports for old API efficiency
1120 ice
->state
.num_viewports
=
1121 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1122 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1123 IRIS_DIRTY_SF_CL_VIEWPORT
|
1124 IRIS_DIRTY_CC_VIEWPORT
|
1125 IRIS_DIRTY_SCISSOR_RECT
|
1126 IRIS_DIRTY_UNCOMPILED_FS
|
1127 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1128 // XXX: CC_VIEWPORT?
1131 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1132 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1135 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1139 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1141 static struct brw_vue_prog_data
*
1142 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1144 if (!ice
->shaders
.prog
[stage
])
1147 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1150 // XXX: iris_compiled_shaders are space-leaking :(
1151 // XXX: do remember to unbind them if deleting them.
1154 * Update the current shader variants for the given state.
1156 * This should be called on every draw call to ensure that the correct
1157 * shaders are bound. It will also flag any dirty state triggered by
1158 * swapping out those shaders.
1161 iris_update_compiled_shaders(struct iris_context
*ice
)
1163 const uint64_t dirty
= ice
->state
.dirty
;
1165 struct brw_vue_prog_data
*old_prog_datas
[4];
1166 if (!(dirty
& IRIS_DIRTY_URB
)) {
1167 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1168 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1171 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1172 struct iris_uncompiled_shader
*tes
=
1173 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1175 iris_update_compiled_tcs(ice
);
1176 iris_update_compiled_tes(ice
);
1178 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1179 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1181 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1182 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1183 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1187 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1188 iris_update_compiled_vs(ice
);
1189 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1190 iris_update_compiled_gs(ice
);
1192 gl_shader_stage last_stage
= last_vue_stage(ice
);
1193 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1194 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1195 update_last_vue_map(ice
, shader
->prog_data
);
1196 if (ice
->state
.streamout
!= shader
->streamout
) {
1197 ice
->state
.streamout
= shader
->streamout
;
1198 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1201 if (ice
->state
.streamout_active
) {
1202 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1203 struct iris_stream_output_target
*so
=
1204 (void *) ice
->state
.so_target
[i
];
1206 so
->stride
= ish
->stream_output
.stride
[i
];
1210 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1211 iris_update_compiled_fs(ice
);
1214 /* Changing shader interfaces may require a URB configuration. */
1215 if (!(dirty
& IRIS_DIRTY_URB
)) {
1216 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1217 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1218 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1219 if (!!old
!= !!new ||
1220 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1221 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1228 static struct iris_compiled_shader
*
1229 iris_compile_cs(struct iris_context
*ice
,
1230 struct iris_uncompiled_shader
*ish
,
1231 const struct brw_cs_prog_key
*key
)
1233 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1234 const struct brw_compiler
*compiler
= screen
->compiler
;
1235 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1236 void *mem_ctx
= ralloc_context(NULL
);
1237 struct brw_cs_prog_data
*cs_prog_data
=
1238 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1239 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1240 enum brw_param_builtin
*system_values
;
1241 unsigned num_system_values
;
1244 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1246 cs_prog_data
->binding_table
.work_groups_start
= 0;
1248 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1250 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1251 &num_system_values
, &num_cbufs
);
1253 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1,
1254 num_system_values
, num_cbufs
);
1256 char *error_str
= NULL
;
1257 const unsigned *program
=
1258 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1259 nir
, -1, &error_str
);
1260 if (program
== NULL
) {
1261 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1262 ralloc_free(mem_ctx
);
1266 struct iris_compiled_shader
*shader
=
1267 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1268 prog_data
, NULL
, system_values
, num_system_values
,
1271 if (ish
->compiled_once
) {
1272 perf_debug(&ice
->dbg
, "Recompiling compute shader\n");
1274 ish
->compiled_once
= true;
1277 ralloc_free(mem_ctx
);
1282 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1284 struct iris_uncompiled_shader
*ish
=
1285 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1287 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1288 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1289 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1290 ice
->vtbl
.populate_cs_key(ice
, &key
);
1292 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1293 struct iris_compiled_shader
*shader
=
1294 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1297 shader
= iris_compile_cs(ice
, ish
, &key
);
1299 if (old
!= shader
) {
1300 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1301 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1302 IRIS_DIRTY_BINDINGS_CS
|
1303 IRIS_DIRTY_CONSTANTS_CS
;
1308 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1311 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1312 assert(cs_prog_data
->push
.total
.size
> 0);
1313 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1314 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1315 assert(prog_data
->param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1316 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1321 * Allocate scratch BOs as needed for the given per-thread size and stage.
1324 iris_get_scratch_space(struct iris_context
*ice
,
1325 unsigned per_thread_scratch
,
1326 gl_shader_stage stage
)
1328 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1329 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1330 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1332 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1333 assert(encoded_size
< (1 << 16));
1335 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1337 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1339 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1340 * must allocate scratch space enough so that each slice has 4
1343 * According to the other driver team, this applies to compute shaders
1344 * as well. This is not currently documented at all.
1346 * This hack is no longer necessary on Gen11+.
1348 unsigned subslice_total
= screen
->subslice_total
;
1349 if (devinfo
->gen
< 11)
1350 subslice_total
= 4 * devinfo
->num_slices
;
1351 assert(subslice_total
>= screen
->subslice_total
);
1354 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1355 uint32_t max_threads
[] = {
1356 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1357 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1358 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1359 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1360 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1361 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1364 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1366 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1372 /* ------------------------------------------------------------------- */
1375 * The pipe->create_[stage]_state() driver hooks.
1377 * Performs basic NIR preprocessing, records any state dependencies, and
1378 * returns an iris_uncompiled_shader as the Gallium CSO.
1380 * Actual shader compilation to assembly happens later, at first use.
1383 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1385 const struct pipe_stream_output_info
*so_info
)
1387 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1388 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1390 struct iris_uncompiled_shader
*ish
=
1391 calloc(1, sizeof(struct iris_uncompiled_shader
));
1395 nir
= brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1397 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1398 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1400 ish
->program_id
= get_new_program_id(screen
);
1403 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1404 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1410 static struct iris_uncompiled_shader
*
1411 iris_create_shader_state(struct pipe_context
*ctx
,
1412 const struct pipe_shader_state
*state
)
1414 struct nir_shader
*nir
;
1416 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1417 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1419 nir
= state
->ir
.nir
;
1421 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1425 iris_create_vs_state(struct pipe_context
*ctx
,
1426 const struct pipe_shader_state
*state
)
1428 struct iris_context
*ice
= (void *) ctx
;
1429 struct iris_screen
*screen
= (void *) ctx
->screen
;
1430 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1432 /* User clip planes */
1433 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1434 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
1436 if (screen
->precompile
) {
1437 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1438 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1440 iris_compile_vs(ice
, ish
, &key
);
1447 iris_create_tcs_state(struct pipe_context
*ctx
,
1448 const struct pipe_shader_state
*state
)
1450 struct iris_context
*ice
= (void *) ctx
;
1451 struct iris_screen
*screen
= (void *) ctx
->screen
;
1452 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1453 struct shader_info
*info
= &ish
->nir
->info
;
1457 if (screen
->precompile
) {
1458 const unsigned _GL_TRIANGLES
= 0x0004;
1459 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1460 struct brw_tcs_prog_key key
= {
1461 KEY_INIT(devinfo
->gen
),
1462 // XXX: make sure the linker fills this out from the TES...
1463 .tes_primitive_mode
=
1464 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
1466 .outputs_written
= info
->outputs_written
,
1467 .patch_outputs_written
= info
->patch_outputs_written
,
1470 iris_compile_tcs(ice
, ish
, &key
);
1477 iris_create_tes_state(struct pipe_context
*ctx
,
1478 const struct pipe_shader_state
*state
)
1480 struct iris_context
*ice
= (void *) ctx
;
1481 struct iris_screen
*screen
= (void *) ctx
->screen
;
1482 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1483 struct shader_info
*info
= &ish
->nir
->info
;
1487 if (screen
->precompile
) {
1488 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1489 struct brw_tes_prog_key key
= {
1490 KEY_INIT(devinfo
->gen
),
1491 // XXX: not ideal, need TCS output/TES input unification
1492 .inputs_read
= info
->inputs_read
,
1493 .patch_inputs_read
= info
->patch_inputs_read
,
1496 iris_compile_tes(ice
, ish
, &key
);
1503 iris_create_gs_state(struct pipe_context
*ctx
,
1504 const struct pipe_shader_state
*state
)
1506 struct iris_context
*ice
= (void *) ctx
;
1507 struct iris_screen
*screen
= (void *) ctx
->screen
;
1508 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1512 if (screen
->precompile
) {
1513 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1514 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1516 iris_compile_gs(ice
, ish
, &key
);
1523 iris_create_fs_state(struct pipe_context
*ctx
,
1524 const struct pipe_shader_state
*state
)
1526 struct iris_context
*ice
= (void *) ctx
;
1527 struct iris_screen
*screen
= (void *) ctx
->screen
;
1528 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1529 struct shader_info
*info
= &ish
->nir
->info
;
1531 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
1532 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
1533 (1ull << IRIS_NOS_RASTERIZER
) |
1534 (1ull << IRIS_NOS_BLEND
);
1536 /* The program key needs the VUE map if there are > 16 inputs */
1537 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
1538 BRW_FS_VARYING_INPUT_MASK
) > 16) {
1539 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
1542 if (screen
->precompile
) {
1543 const uint64_t color_outputs
= info
->outputs_written
&
1544 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
1545 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
1546 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
1548 bool can_rearrange_varyings
=
1549 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
1551 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1552 struct brw_wm_prog_key key
= {
1553 KEY_INIT(devinfo
->gen
),
1554 .nr_color_regions
= util_bitcount(color_outputs
),
1555 .coherent_fb_fetch
= true,
1556 .input_slots_valid
=
1557 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
1560 iris_compile_fs(ice
, ish
, &key
, NULL
);
1567 iris_create_compute_state(struct pipe_context
*ctx
,
1568 const struct pipe_compute_state
*state
)
1570 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
1572 struct iris_context
*ice
= (void *) ctx
;
1573 struct iris_screen
*screen
= (void *) ctx
->screen
;
1574 struct iris_uncompiled_shader
*ish
=
1575 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
1577 // XXX: disallow more than 64KB of shared variables
1579 if (screen
->precompile
) {
1580 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1581 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1583 iris_compile_cs(ice
, ish
, &key
);
1590 * The pipe->delete_[stage]_state() driver hooks.
1592 * Frees the iris_uncompiled_shader.
1595 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
1597 struct iris_uncompiled_shader
*ish
= state
;
1599 ralloc_free(ish
->nir
);
1604 * The pipe->bind_[stage]_state() driver hook.
1606 * Binds an uncompiled shader as the current one for a particular stage.
1607 * Updates dirty tracking to account for the shader's NOS.
1610 bind_state(struct iris_context
*ice
,
1611 struct iris_uncompiled_shader
*ish
,
1612 gl_shader_stage stage
)
1614 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
1615 const uint64_t nos
= ish
? ish
->nos
: 0;
1617 ice
->shaders
.uncompiled
[stage
] = ish
;
1618 ice
->state
.dirty
|= dirty_bit
;
1620 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
1621 * (or that they no longer need to do so).
1623 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
1625 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
1627 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
1632 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1634 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
1638 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1640 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
1644 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1646 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1648 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1649 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
1650 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1652 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
1656 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1658 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1660 /* Enabling/disabling optional stages requires a URB reconfiguration. */
1661 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
1662 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1664 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
1668 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
1670 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1671 struct iris_uncompiled_shader
*old_ish
=
1672 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1673 struct iris_uncompiled_shader
*new_ish
= state
;
1675 const unsigned color_bits
=
1676 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
1677 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
1679 /* Fragment shader outputs influence HasWriteableRT */
1680 if (!old_ish
|| !new_ish
||
1681 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
1682 (new_ish
->nir
->info
.outputs_written
& color_bits
))
1683 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1685 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
1689 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
1691 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
1695 iris_init_program_functions(struct pipe_context
*ctx
)
1697 ctx
->create_vs_state
= iris_create_vs_state
;
1698 ctx
->create_tcs_state
= iris_create_tcs_state
;
1699 ctx
->create_tes_state
= iris_create_tes_state
;
1700 ctx
->create_gs_state
= iris_create_gs_state
;
1701 ctx
->create_fs_state
= iris_create_fs_state
;
1702 ctx
->create_compute_state
= iris_create_compute_state
;
1704 ctx
->delete_vs_state
= iris_delete_shader_state
;
1705 ctx
->delete_tcs_state
= iris_delete_shader_state
;
1706 ctx
->delete_tes_state
= iris_delete_shader_state
;
1707 ctx
->delete_gs_state
= iris_delete_shader_state
;
1708 ctx
->delete_fs_state
= iris_delete_shader_state
;
1709 ctx
->delete_compute_state
= iris_delete_shader_state
;
1711 ctx
->bind_vs_state
= iris_bind_vs_state
;
1712 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1713 ctx
->bind_tes_state
= iris_bind_tes_state
;
1714 ctx
->bind_gs_state
= iris_bind_gs_state
;
1715 ctx
->bind_fs_state
= iris_bind_fs_state
;
1716 ctx
->bind_compute_state
= iris_bind_cs_state
;