2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/debug.h"
41 #include "compiler/nir/nir.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "compiler/nir/nir_serialize.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/compiler/brw_nir.h"
46 #include "iris_context.h"
47 #include "nir/tgsi_to_nir.h"
49 #define KEY_INIT_NO_ID(gen) \
50 .base.subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM, \
51 .base.tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
52 .base.tex.compressed_multisample_layout_mask = ~0, \
53 .base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
54 #define KEY_INIT(gen) .base.program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
57 get_new_program_id(struct iris_screen
*screen
)
59 return p_atomic_inc_return(&screen
->program_id
);
63 upload_state(struct u_upload_mgr
*uploader
,
64 struct iris_state_ref
*ref
,
69 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
74 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
75 struct pipe_shader_buffer
*buf
,
76 struct iris_state_ref
*surf_state
,
79 struct pipe_context
*ctx
= &ice
->ctx
;
80 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
83 upload_state(ice
->state
.surface_uploader
, surf_state
,
84 screen
->isl_dev
.ss
.size
, 64);
86 surf_state
->res
= NULL
;
90 struct iris_resource
*res
= (void *) buf
->buffer
;
91 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
92 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
94 isl_buffer_fill_state(&screen
->isl_dev
, map
,
95 .address
= res
->bo
->gtt_offset
+ res
->offset
+
97 .size_B
= buf
->buffer_size
- res
->offset
,
98 .format
= ssbo
? ISL_FORMAT_RAW
99 : ISL_FORMAT_R32G32B32A32_FLOAT
,
100 .swizzle
= ISL_SWIZZLE_IDENTITY
,
102 .mocs
= ice
->vtbl
.mocs(res
->bo
));
106 get_aoa_deref_offset(nir_builder
*b
,
107 nir_deref_instr
*deref
,
110 unsigned array_size
= elem_size
;
111 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
113 while (deref
->deref_type
!= nir_deref_type_var
) {
114 assert(deref
->deref_type
== nir_deref_type_array
);
116 /* This level's element size is the previous level's array size */
117 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
118 assert(deref
->arr
.index
.ssa
);
119 offset
= nir_iadd(b
, offset
,
120 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
122 deref
= nir_deref_instr_parent(deref
);
123 assert(glsl_type_is_array(deref
->type
));
124 array_size
*= glsl_get_length(deref
->type
);
127 /* Accessing an invalid surface index with the dataport can result in a
128 * hang. According to the spec "if the index used to select an individual
129 * element is negative or greater than or equal to the size of the array,
130 * the results of the operation are undefined but may not lead to
131 * termination" -- which is one of the possible outcomes of the hang.
132 * Clamp the index to prevent access outside of the array bounds.
134 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
138 iris_lower_storage_image_derefs(nir_shader
*nir
)
140 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
143 nir_builder_init(&b
, impl
);
145 nir_foreach_block(block
, impl
) {
146 nir_foreach_instr_safe(instr
, block
) {
147 if (instr
->type
!= nir_instr_type_intrinsic
)
150 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
151 switch (intrin
->intrinsic
) {
152 case nir_intrinsic_image_deref_load
:
153 case nir_intrinsic_image_deref_store
:
154 case nir_intrinsic_image_deref_atomic_add
:
155 case nir_intrinsic_image_deref_atomic_min
:
156 case nir_intrinsic_image_deref_atomic_max
:
157 case nir_intrinsic_image_deref_atomic_and
:
158 case nir_intrinsic_image_deref_atomic_or
:
159 case nir_intrinsic_image_deref_atomic_xor
:
160 case nir_intrinsic_image_deref_atomic_exchange
:
161 case nir_intrinsic_image_deref_atomic_comp_swap
:
162 case nir_intrinsic_image_deref_size
:
163 case nir_intrinsic_image_deref_samples
:
164 case nir_intrinsic_image_deref_load_raw_intel
:
165 case nir_intrinsic_image_deref_store_raw_intel
: {
166 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
167 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
169 b
.cursor
= nir_before_instr(&intrin
->instr
);
171 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
172 get_aoa_deref_offset(&b
, deref
, 1));
173 nir_rewrite_image_intrinsic(intrin
, index
, false);
184 // XXX: need unify_interfaces() at link time...
187 * Fix an uncompiled shader's stream output info.
189 * Core Gallium stores output->register_index as a "slot" number, where
190 * slots are assigned consecutively to all outputs in info->outputs_written.
191 * This naive packing of outputs doesn't work for us - we too have slots,
192 * but the layout is defined by the VUE map, which we won't have until we
193 * compile a specific shader variant. So, we remap these and simply store
194 * VARYING_SLOT_* in our copy's output->register_index fields.
196 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
197 * components of our VUE header. See brw_vue_map.c for the layout.
200 update_so_info(struct pipe_stream_output_info
*so_info
,
201 uint64_t outputs_written
)
203 uint8_t reverse_map
[64] = {};
205 while (outputs_written
) {
206 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
209 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
210 struct pipe_stream_output
*output
= &so_info
->output
[i
];
212 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
213 output
->register_index
= reverse_map
[output
->register_index
];
215 /* The VUE header contains three scalar fields packed together:
216 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
217 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
218 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
220 switch (output
->register_index
) {
221 case VARYING_SLOT_LAYER
:
222 assert(output
->num_components
== 1);
223 output
->register_index
= VARYING_SLOT_PSIZ
;
224 output
->start_component
= 1;
226 case VARYING_SLOT_VIEWPORT
:
227 assert(output
->num_components
== 1);
228 output
->register_index
= VARYING_SLOT_PSIZ
;
229 output
->start_component
= 2;
231 case VARYING_SLOT_PSIZ
:
232 assert(output
->num_components
== 1);
233 output
->start_component
= 3;
237 //info->outputs_written |= 1ull << output->register_index;
242 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
243 unsigned offset
, unsigned n
)
245 assert(offset
% sizeof(uint32_t) == 0);
247 for (unsigned i
= 0; i
< n
; ++i
)
248 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
250 for (unsigned i
= n
; i
< 4; ++i
)
251 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
255 * Associate NIR uniform variables with the prog_data->param[] mechanism
256 * used by the backend. Also, decide which UBOs we'd like to push in an
257 * ideal situation (though the backend can reduce this).
260 iris_setup_uniforms(const struct brw_compiler
*compiler
,
263 struct brw_stage_prog_data
*prog_data
,
264 enum brw_param_builtin
**out_system_values
,
265 unsigned *out_num_system_values
,
266 unsigned *out_num_cbufs
)
268 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
270 /* The intel compiler assumes that num_uniforms is in bytes. For
271 * scalar that means 4 bytes per uniform slot.
273 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
275 nir
->num_uniforms
*= 4;
277 const unsigned IRIS_MAX_SYSTEM_VALUES
=
278 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
279 enum brw_param_builtin
*system_values
=
280 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
281 unsigned num_system_values
= 0;
283 unsigned patch_vert_idx
= -1;
284 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
285 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
286 memset(ucp_idx
, -1, sizeof(ucp_idx
));
287 memset(img_idx
, -1, sizeof(img_idx
));
289 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
292 nir_builder_init(&b
, impl
);
294 b
.cursor
= nir_before_block(nir_start_block(impl
));
295 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
296 nir_ssa_def
*temp_const_ubo_name
= NULL
;
298 /* Turn system value intrinsics into uniforms */
299 nir_foreach_block(block
, impl
) {
300 nir_foreach_instr_safe(instr
, block
) {
301 if (instr
->type
!= nir_instr_type_intrinsic
)
304 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
307 switch (intrin
->intrinsic
) {
308 case nir_intrinsic_load_constant
: {
309 /* This one is special because it reads from the shader constant
310 * data and not cbuf0 which gallium uploads for us.
312 b
.cursor
= nir_before_instr(instr
);
313 nir_ssa_def
*offset
=
314 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
315 nir_intrinsic_base(intrin
));
317 if (temp_const_ubo_name
== NULL
)
318 temp_const_ubo_name
= nir_imm_int(&b
, 0);
320 nir_intrinsic_instr
*load_ubo
=
321 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
322 load_ubo
->num_components
= intrin
->num_components
;
323 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
324 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
325 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
326 intrin
->dest
.ssa
.num_components
,
327 intrin
->dest
.ssa
.bit_size
,
328 intrin
->dest
.ssa
.name
);
329 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
331 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
332 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
333 nir_instr_remove(&intrin
->instr
);
336 case nir_intrinsic_load_user_clip_plane
: {
337 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
339 if (ucp_idx
[ucp
] == -1) {
340 ucp_idx
[ucp
] = num_system_values
;
341 num_system_values
+= 4;
344 for (int i
= 0; i
< 4; i
++) {
345 system_values
[ucp_idx
[ucp
] + i
] =
346 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
349 b
.cursor
= nir_before_instr(instr
);
350 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
353 case nir_intrinsic_load_patch_vertices_in
:
354 if (patch_vert_idx
== -1)
355 patch_vert_idx
= num_system_values
++;
357 system_values
[patch_vert_idx
] =
358 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
360 b
.cursor
= nir_before_instr(instr
);
361 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
363 case nir_intrinsic_image_deref_load_param_intel
: {
364 assert(devinfo
->gen
< 9);
365 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
366 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
368 if (img_idx
[var
->data
.binding
] == -1) {
369 /* GL only allows arrays of arrays of images. */
370 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
371 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
373 for (int i
= 0; i
< num_images
; i
++) {
374 const unsigned img
= var
->data
.binding
+ i
;
376 img_idx
[img
] = num_system_values
;
377 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
379 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
381 setup_vec4_image_sysval(
382 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
383 offsetof(struct brw_image_param
, offset
), 2);
384 setup_vec4_image_sysval(
385 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
386 offsetof(struct brw_image_param
, size
), 3);
387 setup_vec4_image_sysval(
388 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
389 offsetof(struct brw_image_param
, stride
), 4);
390 setup_vec4_image_sysval(
391 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
392 offsetof(struct brw_image_param
, tiling
), 3);
393 setup_vec4_image_sysval(
394 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
395 offsetof(struct brw_image_param
, swizzling
), 2);
399 b
.cursor
= nir_before_instr(instr
);
400 offset
= nir_iadd(&b
,
401 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
402 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
403 nir_intrinsic_base(intrin
) * 16));
410 unsigned comps
= nir_intrinsic_dest_components(intrin
);
412 nir_intrinsic_instr
*load
=
413 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
414 load
->num_components
= comps
;
415 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
416 load
->src
[1] = nir_src_for_ssa(offset
);
417 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
418 nir_builder_instr_insert(&b
, &load
->instr
);
419 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
420 nir_src_for_ssa(&load
->dest
.ssa
));
421 nir_instr_remove(instr
);
425 nir_validate_shader(nir
, "before remapping");
427 /* Uniforms are stored in constant buffer 0, the
428 * user-facing UBOs are indexed by one. So if any constant buffer is
429 * needed, the constant buffer 0 will be needed, so account for it.
431 unsigned num_cbufs
= nir
->info
.num_ubos
;
432 if (num_cbufs
|| nir
->num_uniforms
)
435 /* Place the new params in a new cbuf. */
436 if (num_system_values
> 0) {
437 unsigned sysval_cbuf_index
= num_cbufs
;
440 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
443 nir_foreach_block(block
, impl
) {
444 nir_foreach_instr_safe(instr
, block
) {
445 if (instr
->type
!= nir_instr_type_intrinsic
)
448 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
450 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
453 b
.cursor
= nir_before_instr(instr
);
455 assert(load
->src
[0].is_ssa
);
457 if (load
->src
[0].ssa
== temp_ubo_name
) {
458 nir_ssa_def
*imm
= nir_imm_int(&b
, sysval_cbuf_index
);
459 nir_instr_rewrite_src(instr
, &load
->src
[0],
460 nir_src_for_ssa(imm
));
465 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
466 nir_opt_constant_folding(nir
);
468 ralloc_free(system_values
);
469 system_values
= NULL
;
472 assert(num_cbufs
< PIPE_MAX_CONSTANT_BUFFERS
);
473 nir_validate_shader(nir
, "after remap");
475 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
476 * about it for compute shaders, so go ahead and make some fake ones
477 * which the backend will dead code eliminate.
479 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
480 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
482 /* Constant loads (if any) need to go at the end of the constant buffers so
483 * we need to know num_cbufs before we can lower to them.
485 if (temp_const_ubo_name
!= NULL
) {
486 nir_load_const_instr
*const_ubo_index
=
487 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
488 assert(const_ubo_index
->def
.bit_size
== 32);
489 const_ubo_index
->value
[0].u32
= num_cbufs
;
492 *out_system_values
= system_values
;
493 *out_num_system_values
= num_system_values
;
494 *out_num_cbufs
= num_cbufs
;
497 static const char *surface_group_names
[] = {
498 [IRIS_SURFACE_GROUP_RENDER_TARGET
] = "render target",
499 [IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = "CS work groups",
500 [IRIS_SURFACE_GROUP_TEXTURE
] = "texture",
501 [IRIS_SURFACE_GROUP_UBO
] = "ubo",
502 [IRIS_SURFACE_GROUP_SSBO
] = "ssbo",
503 [IRIS_SURFACE_GROUP_IMAGE
] = "image",
507 iris_print_binding_table(FILE *fp
, const char *name
,
508 const struct iris_binding_table
*bt
)
510 STATIC_ASSERT(ARRAY_SIZE(surface_group_names
) == IRIS_SURFACE_GROUP_COUNT
);
513 uint32_t compacted
= 0;
515 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
516 uint32_t size
= bt
->sizes
[i
];
519 compacted
+= util_bitcount64(bt
->used_mask
[i
]);
523 fprintf(fp
, "Binding table for %s is empty\n\n", name
);
527 if (total
!= compacted
) {
528 fprintf(fp
, "Binding table for %s "
529 "(compacted to %u entries from %u entries)\n",
530 name
, compacted
, total
);
532 fprintf(fp
, "Binding table for %s (%u entries)\n", name
, total
);
536 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
537 uint64_t mask
= bt
->used_mask
[i
];
539 int index
= u_bit_scan64(&mask
);
540 fprintf(fp
, " [%u] %s #%d\n", entry
++, surface_group_names
[i
], index
);
547 /* Max elements in a surface group. */
548 SURFACE_GROUP_MAX_ELEMENTS
= 64,
552 * Map a <group, index> pair to a binding table index.
554 * For example: <UBO, 5> => binding table index 12
557 iris_group_index_to_bti(const struct iris_binding_table
*bt
,
558 enum iris_surface_group group
, uint32_t index
)
560 assert(index
< bt
->sizes
[group
]);
561 uint64_t mask
= bt
->used_mask
[group
];
562 uint64_t bit
= 1ull << index
;
564 return bt
->offsets
[group
] + util_bitcount64((bit
- 1) & mask
);
566 return IRIS_SURFACE_NOT_USED
;
571 * Map a binding table index back to a <group, index> pair.
573 * For example: binding table index 12 => <UBO, 5>
576 iris_bti_to_group_index(const struct iris_binding_table
*bt
,
577 enum iris_surface_group group
, uint32_t bti
)
579 uint64_t used_mask
= bt
->used_mask
[group
];
580 assert(bti
>= bt
->offsets
[group
]);
582 uint32_t c
= bti
- bt
->offsets
[group
];
584 int i
= u_bit_scan64(&used_mask
);
590 return IRIS_SURFACE_NOT_USED
;
594 rewrite_src_with_bti(nir_builder
*b
, struct iris_binding_table
*bt
,
595 nir_instr
*instr
, nir_src
*src
,
596 enum iris_surface_group group
)
598 assert(bt
->sizes
[group
] > 0);
600 b
->cursor
= nir_before_instr(instr
);
602 if (nir_src_is_const(*src
)) {
603 uint32_t index
= nir_src_as_uint(*src
);
604 bti
= nir_imm_intN_t(b
, iris_group_index_to_bti(bt
, group
, index
),
607 /* Indirect usage makes all the surfaces of the group to be available,
608 * so we can just add the base.
610 assert(bt
->used_mask
[group
] == BITFIELD64_MASK(bt
->sizes
[group
]));
611 bti
= nir_iadd_imm(b
, src
->ssa
, bt
->offsets
[group
]);
613 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(bti
));
617 mark_used_with_src(struct iris_binding_table
*bt
, nir_src
*src
,
618 enum iris_surface_group group
)
620 assert(bt
->sizes
[group
] > 0);
622 if (nir_src_is_const(*src
)) {
623 uint64_t index
= nir_src_as_uint(*src
);
624 assert(index
< bt
->sizes
[group
]);
625 bt
->used_mask
[group
] |= 1ull << index
;
627 /* There's an indirect usage, we need all the surfaces. */
628 bt
->used_mask
[group
] = BITFIELD64_MASK(bt
->sizes
[group
]);
633 skip_compacting_binding_tables(void)
635 static int skip
= -1;
637 skip
= env_var_as_boolean("INTEL_DISABLE_COMPACT_BINDING_TABLE", false);
642 * Set up the binding table indices and apply to the shader.
645 iris_setup_binding_table(struct nir_shader
*nir
,
646 struct iris_binding_table
*bt
,
647 unsigned num_render_targets
,
648 unsigned num_system_values
,
651 const struct shader_info
*info
= &nir
->info
;
653 memset(bt
, 0, sizeof(*bt
));
655 /* Set the sizes for each surface group. For some groups, we already know
656 * upfront how many will be used, so mark them.
658 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
659 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET
] = num_render_targets
;
660 /* All render targets used. */
661 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET
] =
662 BITFIELD64_MASK(num_render_targets
);
663 } else if (info
->stage
== MESA_SHADER_COMPUTE
) {
664 bt
->sizes
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
667 bt
->sizes
[IRIS_SURFACE_GROUP_TEXTURE
] = util_last_bit(info
->textures_used
);
668 bt
->used_mask
[IRIS_SURFACE_GROUP_TEXTURE
] = info
->textures_used
;
670 bt
->sizes
[IRIS_SURFACE_GROUP_IMAGE
] = info
->num_images
;
672 /* Allocate an extra slot in the UBO section for NIR constants.
673 * Binding table compaction will remove it if unnecessary.
675 * We don't include them in iris_compiled_shader::num_cbufs because
676 * they are uploaded separately from shs->constbuf[], but from a shader
677 * point of view, they're another UBO (at the end of the section).
679 bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] = num_cbufs
+ 1;
681 /* The first IRIS_MAX_ABOs indices in the SSBO group are for atomics, real
682 * SSBOs start after that. Compaction will remove unused ABOs.
684 bt
->sizes
[IRIS_SURFACE_GROUP_SSBO
] = IRIS_MAX_ABOS
+ info
->num_ssbos
;
686 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
687 assert(bt
->sizes
[i
] <= SURFACE_GROUP_MAX_ELEMENTS
);
689 /* Mark surfaces used for the cases we don't have the information available
692 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
693 nir_foreach_block (block
, impl
) {
694 nir_foreach_instr (instr
, block
) {
695 if (instr
->type
!= nir_instr_type_intrinsic
)
698 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
699 switch (intrin
->intrinsic
) {
700 case nir_intrinsic_load_num_work_groups
:
701 bt
->used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
704 case nir_intrinsic_image_size
:
705 case nir_intrinsic_image_load
:
706 case nir_intrinsic_image_store
:
707 case nir_intrinsic_image_atomic_add
:
708 case nir_intrinsic_image_atomic_min
:
709 case nir_intrinsic_image_atomic_max
:
710 case nir_intrinsic_image_atomic_and
:
711 case nir_intrinsic_image_atomic_or
:
712 case nir_intrinsic_image_atomic_xor
:
713 case nir_intrinsic_image_atomic_exchange
:
714 case nir_intrinsic_image_atomic_comp_swap
:
715 case nir_intrinsic_image_load_raw_intel
:
716 case nir_intrinsic_image_store_raw_intel
:
717 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_IMAGE
);
720 case nir_intrinsic_load_ubo
:
721 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_UBO
);
724 case nir_intrinsic_store_ssbo
:
725 mark_used_with_src(bt
, &intrin
->src
[1], IRIS_SURFACE_GROUP_SSBO
);
728 case nir_intrinsic_get_buffer_size
:
729 case nir_intrinsic_ssbo_atomic_add
:
730 case nir_intrinsic_ssbo_atomic_imin
:
731 case nir_intrinsic_ssbo_atomic_umin
:
732 case nir_intrinsic_ssbo_atomic_imax
:
733 case nir_intrinsic_ssbo_atomic_umax
:
734 case nir_intrinsic_ssbo_atomic_and
:
735 case nir_intrinsic_ssbo_atomic_or
:
736 case nir_intrinsic_ssbo_atomic_xor
:
737 case nir_intrinsic_ssbo_atomic_exchange
:
738 case nir_intrinsic_ssbo_atomic_comp_swap
:
739 case nir_intrinsic_ssbo_atomic_fmin
:
740 case nir_intrinsic_ssbo_atomic_fmax
:
741 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
742 case nir_intrinsic_load_ssbo
:
743 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_SSBO
);
752 /* When disable we just mark everything as used. */
753 if (unlikely(skip_compacting_binding_tables())) {
754 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
755 bt
->used_mask
[i
] = BITFIELD64_MASK(bt
->sizes
[i
]);
758 /* Calculate the offsets and the binding table size based on the used
759 * surfaces. After this point, the functions to go between "group indices"
760 * and binding table indices can be used.
763 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
764 if (bt
->used_mask
[i
] != 0) {
765 bt
->offsets
[i
] = next
;
766 next
+= util_bitcount64(bt
->used_mask
[i
]);
769 bt
->size_bytes
= next
* 4;
771 if (unlikely(INTEL_DEBUG
& DEBUG_BT
)) {
772 iris_print_binding_table(stderr
, gl_shader_stage_name(info
->stage
), bt
);
775 /* Apply the binding table indices. The backend compiler is not expected
776 * to change those, as we haven't set any of the *_start entries in brw
780 nir_builder_init(&b
, impl
);
782 nir_foreach_block (block
, impl
) {
783 nir_foreach_instr (instr
, block
) {
784 if (instr
->type
== nir_instr_type_tex
) {
785 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
787 iris_group_index_to_bti(bt
, IRIS_SURFACE_GROUP_TEXTURE
,
792 if (instr
->type
!= nir_instr_type_intrinsic
)
795 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
796 switch (intrin
->intrinsic
) {
797 case nir_intrinsic_image_size
:
798 case nir_intrinsic_image_load
:
799 case nir_intrinsic_image_store
:
800 case nir_intrinsic_image_atomic_add
:
801 case nir_intrinsic_image_atomic_min
:
802 case nir_intrinsic_image_atomic_max
:
803 case nir_intrinsic_image_atomic_and
:
804 case nir_intrinsic_image_atomic_or
:
805 case nir_intrinsic_image_atomic_xor
:
806 case nir_intrinsic_image_atomic_exchange
:
807 case nir_intrinsic_image_atomic_comp_swap
:
808 case nir_intrinsic_image_load_raw_intel
:
809 case nir_intrinsic_image_store_raw_intel
:
810 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
811 IRIS_SURFACE_GROUP_IMAGE
);
814 case nir_intrinsic_load_ubo
:
815 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
816 IRIS_SURFACE_GROUP_UBO
);
819 case nir_intrinsic_store_ssbo
:
820 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[1],
821 IRIS_SURFACE_GROUP_SSBO
);
824 case nir_intrinsic_get_buffer_size
:
825 case nir_intrinsic_ssbo_atomic_add
:
826 case nir_intrinsic_ssbo_atomic_imin
:
827 case nir_intrinsic_ssbo_atomic_umin
:
828 case nir_intrinsic_ssbo_atomic_imax
:
829 case nir_intrinsic_ssbo_atomic_umax
:
830 case nir_intrinsic_ssbo_atomic_and
:
831 case nir_intrinsic_ssbo_atomic_or
:
832 case nir_intrinsic_ssbo_atomic_xor
:
833 case nir_intrinsic_ssbo_atomic_exchange
:
834 case nir_intrinsic_ssbo_atomic_comp_swap
:
835 case nir_intrinsic_ssbo_atomic_fmin
:
836 case nir_intrinsic_ssbo_atomic_fmax
:
837 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
838 case nir_intrinsic_load_ssbo
:
839 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
840 IRIS_SURFACE_GROUP_SSBO
);
851 iris_debug_recompile(struct iris_context
*ice
,
852 struct shader_info
*info
,
853 const struct brw_base_prog_key
*key
)
855 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
856 const struct brw_compiler
*c
= screen
->compiler
;
861 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
862 _mesa_shader_stage_to_string(info
->stage
),
863 info
->name
? info
->name
: "(no identifier)",
864 info
->label
? info
->label
: "");
866 const void *old_key
=
867 iris_find_previous_compile(ice
, info
->stage
, key
->program_string_id
);
869 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
873 * Get the shader for the last enabled geometry stage.
875 * This stage is the one which will feed stream output and the rasterizer.
877 static gl_shader_stage
878 last_vue_stage(struct iris_context
*ice
)
880 if (ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
881 return MESA_SHADER_GEOMETRY
;
883 if (ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
884 return MESA_SHADER_TESS_EVAL
;
886 return MESA_SHADER_VERTEX
;
890 * Compile a vertex shader, and upload the assembly.
892 static struct iris_compiled_shader
*
893 iris_compile_vs(struct iris_context
*ice
,
894 struct iris_uncompiled_shader
*ish
,
895 const struct brw_vs_prog_key
*key
)
897 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
898 const struct brw_compiler
*compiler
= screen
->compiler
;
899 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
900 void *mem_ctx
= ralloc_context(NULL
);
901 struct brw_vs_prog_data
*vs_prog_data
=
902 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
903 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
904 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
905 enum brw_param_builtin
*system_values
;
906 unsigned num_system_values
;
909 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
911 if (key
->nr_userclip_plane_consts
) {
912 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
913 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
914 nir_lower_io_to_temporaries(nir
, impl
, true, false);
915 nir_lower_global_vars_to_local(nir
);
916 nir_lower_vars_to_ssa(nir
);
917 nir_shader_gather_info(nir
, impl
);
920 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
922 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
923 &num_system_values
, &num_cbufs
);
925 struct iris_binding_table bt
;
926 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
927 num_system_values
, num_cbufs
);
929 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
931 brw_compute_vue_map(devinfo
,
932 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
933 nir
->info
.separate_shader
);
935 /* Don't tell the backend about our clip plane constants, we've already
936 * lowered them in NIR and we don't want it doing it again.
938 struct brw_vs_prog_key key_no_ucp
= *key
;
939 key_no_ucp
.nr_userclip_plane_consts
= 0;
941 char *error_str
= NULL
;
942 const unsigned *program
=
943 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
944 nir
, -1, &error_str
);
945 if (program
== NULL
) {
946 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
947 ralloc_free(mem_ctx
);
951 if (ish
->compiled_once
) {
952 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
954 ish
->compiled_once
= true;
958 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
959 &vue_prog_data
->vue_map
);
961 struct iris_compiled_shader
*shader
=
962 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
963 prog_data
, so_decls
, system_values
, num_system_values
,
966 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
968 ralloc_free(mem_ctx
);
973 * Update the current vertex shader variant.
975 * Fill out the key, look in the cache, compile and bind if needed.
978 iris_update_compiled_vs(struct iris_context
*ice
)
980 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
981 struct iris_uncompiled_shader
*ish
=
982 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
983 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
984 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
986 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
987 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
989 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
990 struct iris_compiled_shader
*shader
=
991 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
994 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
997 shader
= iris_compile_vs(ice
, ish
, &key
);
1000 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
1001 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
1002 IRIS_DIRTY_BINDINGS_VS
|
1003 IRIS_DIRTY_CONSTANTS_VS
|
1005 shs
->sysvals_need_upload
= true;
1007 const struct brw_vs_prog_data
*vs_prog_data
=
1008 (void *) shader
->prog_data
;
1009 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
1010 vs_prog_data
->uses_baseinstance
;
1011 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
1012 vs_prog_data
->uses_is_indexed_draw
;
1013 const bool needs_sgvs_element
= uses_draw_params
||
1014 vs_prog_data
->uses_instanceid
||
1015 vs_prog_data
->uses_vertexid
;
1016 bool needs_edge_flag
= false;
1017 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
1018 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
1019 needs_edge_flag
= true;
1022 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
1023 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
1024 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
1025 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
1026 IRIS_DIRTY_VERTEX_ELEMENTS
;
1028 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
1029 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
1030 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
1031 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
1036 * Get the shader_info for a given stage, or NULL if the stage is disabled.
1038 const struct shader_info
*
1039 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
1041 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
1046 const nir_shader
*nir
= ish
->nir
;
1051 * Get the union of TCS output and TES input slots.
1053 * TCS and TES need to agree on a common URB entry layout. In particular,
1054 * the data for all patch vertices is stored in a single URB entry (unlike
1055 * GS which has one entry per input vertex). This means that per-vertex
1056 * array indexing needs a stride.
1058 * SSO requires locations to match, but doesn't require the number of
1059 * outputs/inputs to match (in fact, the TCS often has extra outputs).
1060 * So, we need to take the extra step of unifying these on the fly.
1063 get_unified_tess_slots(const struct iris_context
*ice
,
1064 uint64_t *per_vertex_slots
,
1065 uint32_t *per_patch_slots
)
1067 const struct shader_info
*tcs
=
1068 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
1069 const struct shader_info
*tes
=
1070 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1072 *per_vertex_slots
= tes
->inputs_read
;
1073 *per_patch_slots
= tes
->patch_inputs_read
;
1076 *per_vertex_slots
|= tcs
->outputs_written
;
1077 *per_patch_slots
|= tcs
->patch_outputs_written
;
1082 * Compile a tessellation control shader, and upload the assembly.
1084 static struct iris_compiled_shader
*
1085 iris_compile_tcs(struct iris_context
*ice
,
1086 struct iris_uncompiled_shader
*ish
,
1087 const struct brw_tcs_prog_key
*key
)
1089 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1090 const struct brw_compiler
*compiler
= screen
->compiler
;
1091 const struct nir_shader_compiler_options
*options
=
1092 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
1093 void *mem_ctx
= ralloc_context(NULL
);
1094 struct brw_tcs_prog_data
*tcs_prog_data
=
1095 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
1096 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
1097 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1098 enum brw_param_builtin
*system_values
= NULL
;
1099 unsigned num_system_values
= 0;
1100 unsigned num_cbufs
= 0;
1104 struct iris_binding_table bt
;
1107 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1109 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1110 &num_system_values
, &num_cbufs
);
1111 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1112 num_system_values
, num_cbufs
);
1113 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1115 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
1117 /* Reserve space for passing the default tess levels as constants. */
1119 num_system_values
= 8;
1121 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
1122 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
1123 prog_data
->nr_params
= num_system_values
;
1125 if (key
->tes_primitive_mode
== GL_QUADS
) {
1126 for (int i
= 0; i
< 4; i
++)
1127 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1129 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1130 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
1131 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
1132 for (int i
= 0; i
< 3; i
++)
1133 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1135 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1137 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
1138 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
1139 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
1142 /* Manually setup the TCS binding table. */
1143 memset(&bt
, 0, sizeof(bt
));
1144 bt
.sizes
[IRIS_SURFACE_GROUP_UBO
] = 1;
1145 bt
.used_mask
[IRIS_SURFACE_GROUP_UBO
] = 1;
1148 prog_data
->ubo_ranges
[0].length
= 1;
1151 char *error_str
= NULL
;
1152 const unsigned *program
=
1153 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
1155 if (program
== NULL
) {
1156 dbg_printf("Failed to compile control shader: %s\n", error_str
);
1157 ralloc_free(mem_ctx
);
1162 if (ish
->compiled_once
) {
1163 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1165 ish
->compiled_once
= true;
1169 struct iris_compiled_shader
*shader
=
1170 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
1171 prog_data
, NULL
, system_values
, num_system_values
,
1175 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1177 ralloc_free(mem_ctx
);
1182 * Update the current tessellation control shader variant.
1184 * Fill out the key, look in the cache, compile and bind if needed.
1187 iris_update_compiled_tcs(struct iris_context
*ice
)
1189 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
1190 struct iris_uncompiled_shader
*tcs
=
1191 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
1192 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1193 const struct brw_compiler
*compiler
= screen
->compiler
;
1194 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1196 const struct shader_info
*tes_info
=
1197 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1198 struct brw_tcs_prog_key key
= {
1199 KEY_INIT_NO_ID(devinfo
->gen
),
1200 .base
.program_string_id
= tcs
? tcs
->program_id
: 0,
1201 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
1203 !tcs
|| compiler
->use_tcs_8_patch
? ice
->state
.vertices_per_patch
: 0,
1205 get_unified_tess_slots(ice
, &key
.outputs_written
,
1206 &key
.patch_outputs_written
);
1207 ice
->vtbl
.populate_tcs_key(ice
, &key
);
1209 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
1210 struct iris_compiled_shader
*shader
=
1211 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
1214 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
1217 shader
= iris_compile_tcs(ice
, tcs
, &key
);
1219 if (old
!= shader
) {
1220 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
1221 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
1222 IRIS_DIRTY_BINDINGS_TCS
|
1223 IRIS_DIRTY_CONSTANTS_TCS
;
1224 shs
->sysvals_need_upload
= true;
1229 * Compile a tessellation evaluation shader, and upload the assembly.
1231 static struct iris_compiled_shader
*
1232 iris_compile_tes(struct iris_context
*ice
,
1233 struct iris_uncompiled_shader
*ish
,
1234 const struct brw_tes_prog_key
*key
)
1236 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1237 const struct brw_compiler
*compiler
= screen
->compiler
;
1238 void *mem_ctx
= ralloc_context(NULL
);
1239 struct brw_tes_prog_data
*tes_prog_data
=
1240 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1241 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1242 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1243 enum brw_param_builtin
*system_values
;
1244 unsigned num_system_values
;
1247 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1249 if (key
->nr_userclip_plane_consts
) {
1250 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1251 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
1252 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1253 nir_lower_global_vars_to_local(nir
);
1254 nir_lower_vars_to_ssa(nir
);
1255 nir_shader_gather_info(nir
, impl
);
1258 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1259 &num_system_values
, &num_cbufs
);
1261 struct iris_binding_table bt
;
1262 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1263 num_system_values
, num_cbufs
);
1265 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1267 struct brw_vue_map input_vue_map
;
1268 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1269 key
->patch_inputs_read
);
1271 char *error_str
= NULL
;
1272 const unsigned *program
=
1273 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
1274 tes_prog_data
, nir
, NULL
, -1, &error_str
);
1275 if (program
== NULL
) {
1276 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1277 ralloc_free(mem_ctx
);
1281 if (ish
->compiled_once
) {
1282 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1284 ish
->compiled_once
= true;
1287 uint32_t *so_decls
=
1288 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1289 &vue_prog_data
->vue_map
);
1292 struct iris_compiled_shader
*shader
=
1293 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1294 prog_data
, so_decls
, system_values
, num_system_values
,
1297 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1299 ralloc_free(mem_ctx
);
1304 * Update the current tessellation evaluation shader variant.
1306 * Fill out the key, look in the cache, compile and bind if needed.
1309 iris_update_compiled_tes(struct iris_context
*ice
)
1311 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
1312 struct iris_uncompiled_shader
*ish
=
1313 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1314 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1315 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1317 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1318 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1319 ice
->vtbl
.populate_tes_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1321 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1322 struct iris_compiled_shader
*shader
=
1323 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1326 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1329 shader
= iris_compile_tes(ice
, ish
, &key
);
1331 if (old
!= shader
) {
1332 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1333 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1334 IRIS_DIRTY_BINDINGS_TES
|
1335 IRIS_DIRTY_CONSTANTS_TES
;
1336 shs
->sysvals_need_upload
= true;
1339 /* TODO: Could compare and avoid flagging this. */
1340 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1341 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1342 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1343 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].sysvals_need_upload
= true;
1348 * Compile a geometry shader, and upload the assembly.
1350 static struct iris_compiled_shader
*
1351 iris_compile_gs(struct iris_context
*ice
,
1352 struct iris_uncompiled_shader
*ish
,
1353 const struct brw_gs_prog_key
*key
)
1355 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1356 const struct brw_compiler
*compiler
= screen
->compiler
;
1357 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1358 void *mem_ctx
= ralloc_context(NULL
);
1359 struct brw_gs_prog_data
*gs_prog_data
=
1360 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1361 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1362 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1363 enum brw_param_builtin
*system_values
;
1364 unsigned num_system_values
;
1367 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1369 if (key
->nr_userclip_plane_consts
) {
1370 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1371 nir_lower_clip_gs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1);
1372 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1373 nir_lower_global_vars_to_local(nir
);
1374 nir_lower_vars_to_ssa(nir
);
1375 nir_shader_gather_info(nir
, impl
);
1378 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1379 &num_system_values
, &num_cbufs
);
1381 struct iris_binding_table bt
;
1382 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1383 num_system_values
, num_cbufs
);
1385 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1387 brw_compute_vue_map(devinfo
,
1388 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1389 nir
->info
.separate_shader
);
1391 char *error_str
= NULL
;
1392 const unsigned *program
=
1393 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1394 NULL
, -1, &error_str
);
1395 if (program
== NULL
) {
1396 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1397 ralloc_free(mem_ctx
);
1401 if (ish
->compiled_once
) {
1402 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1404 ish
->compiled_once
= true;
1407 uint32_t *so_decls
=
1408 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1409 &vue_prog_data
->vue_map
);
1411 struct iris_compiled_shader
*shader
=
1412 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1413 prog_data
, so_decls
, system_values
, num_system_values
,
1416 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1418 ralloc_free(mem_ctx
);
1423 * Update the current geometry shader variant.
1425 * Fill out the key, look in the cache, compile and bind if needed.
1428 iris_update_compiled_gs(struct iris_context
*ice
)
1430 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
1431 struct iris_uncompiled_shader
*ish
=
1432 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1433 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1434 struct iris_compiled_shader
*shader
= NULL
;
1437 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1438 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1439 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1440 ice
->vtbl
.populate_gs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1443 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1446 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1449 shader
= iris_compile_gs(ice
, ish
, &key
);
1452 if (old
!= shader
) {
1453 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1454 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1455 IRIS_DIRTY_BINDINGS_GS
|
1456 IRIS_DIRTY_CONSTANTS_GS
;
1457 shs
->sysvals_need_upload
= true;
1462 * Compile a fragment (pixel) shader, and upload the assembly.
1464 static struct iris_compiled_shader
*
1465 iris_compile_fs(struct iris_context
*ice
,
1466 struct iris_uncompiled_shader
*ish
,
1467 const struct brw_wm_prog_key
*key
,
1468 struct brw_vue_map
*vue_map
)
1470 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1471 const struct brw_compiler
*compiler
= screen
->compiler
;
1472 void *mem_ctx
= ralloc_context(NULL
);
1473 struct brw_wm_prog_data
*fs_prog_data
=
1474 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1475 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1476 enum brw_param_builtin
*system_values
;
1477 unsigned num_system_values
;
1480 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1482 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1484 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1485 &num_system_values
, &num_cbufs
);
1487 struct iris_binding_table bt
;
1488 iris_setup_binding_table(nir
, &bt
, MAX2(key
->nr_color_regions
, 1),
1489 num_system_values
, num_cbufs
);
1491 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1493 char *error_str
= NULL
;
1494 const unsigned *program
=
1495 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1496 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1497 if (program
== NULL
) {
1498 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1499 ralloc_free(mem_ctx
);
1503 if (ish
->compiled_once
) {
1504 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1506 ish
->compiled_once
= true;
1509 struct iris_compiled_shader
*shader
=
1510 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1511 prog_data
, NULL
, system_values
, num_system_values
,
1514 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1516 ralloc_free(mem_ctx
);
1521 * Update the current fragment shader variant.
1523 * Fill out the key, look in the cache, compile and bind if needed.
1526 iris_update_compiled_fs(struct iris_context
*ice
)
1528 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_FRAGMENT
];
1529 struct iris_uncompiled_shader
*ish
=
1530 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1531 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1532 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1533 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1534 ice
->vtbl
.populate_fs_key(ice
, &ish
->nir
->info
, &key
);
1536 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1537 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1539 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1540 struct iris_compiled_shader
*shader
=
1541 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1544 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1547 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1549 if (old
!= shader
) {
1550 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1551 // toggles. might be able to avoid flagging SBE too.
1552 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1553 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1554 IRIS_DIRTY_BINDINGS_FS
|
1555 IRIS_DIRTY_CONSTANTS_FS
|
1559 shs
->sysvals_need_upload
= true;
1564 * Update the last enabled stage's VUE map.
1566 * When the shader feeding the rasterizer's output interface changes, we
1567 * need to re-emit various packets.
1570 update_last_vue_map(struct iris_context
*ice
,
1571 struct brw_stage_prog_data
*prog_data
)
1573 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1574 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1575 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1576 const uint64_t changed_slots
=
1577 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1579 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1580 ice
->state
.num_viewports
=
1581 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1582 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1583 IRIS_DIRTY_SF_CL_VIEWPORT
|
1584 IRIS_DIRTY_CC_VIEWPORT
|
1585 IRIS_DIRTY_SCISSOR_RECT
|
1586 IRIS_DIRTY_UNCOMPILED_FS
|
1587 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1590 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1591 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1594 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1598 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1600 static struct brw_vue_prog_data
*
1601 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1603 if (!ice
->shaders
.prog
[stage
])
1606 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1609 // XXX: iris_compiled_shaders are space-leaking :(
1610 // XXX: do remember to unbind them if deleting them.
1613 * Update the current shader variants for the given state.
1615 * This should be called on every draw call to ensure that the correct
1616 * shaders are bound. It will also flag any dirty state triggered by
1617 * swapping out those shaders.
1620 iris_update_compiled_shaders(struct iris_context
*ice
)
1622 const uint64_t dirty
= ice
->state
.dirty
;
1624 struct brw_vue_prog_data
*old_prog_datas
[4];
1625 if (!(dirty
& IRIS_DIRTY_URB
)) {
1626 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1627 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1630 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1631 struct iris_uncompiled_shader
*tes
=
1632 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1634 iris_update_compiled_tcs(ice
);
1635 iris_update_compiled_tes(ice
);
1637 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1638 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1640 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1641 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1642 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1646 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1647 iris_update_compiled_vs(ice
);
1648 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1649 iris_update_compiled_gs(ice
);
1651 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1652 const struct iris_compiled_shader
*gs
=
1653 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1654 const struct iris_compiled_shader
*tes
=
1655 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1657 bool points_or_lines
= false;
1660 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1662 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1663 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1665 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1667 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1668 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1671 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1672 /* Outbound to XY Clip enables */
1673 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1674 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1678 gl_shader_stage last_stage
= last_vue_stage(ice
);
1679 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1680 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1681 update_last_vue_map(ice
, shader
->prog_data
);
1682 if (ice
->state
.streamout
!= shader
->streamout
) {
1683 ice
->state
.streamout
= shader
->streamout
;
1684 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1687 if (ice
->state
.streamout_active
) {
1688 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1689 struct iris_stream_output_target
*so
=
1690 (void *) ice
->state
.so_target
[i
];
1692 so
->stride
= ish
->stream_output
.stride
[i
] * sizeof(uint32_t);
1696 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1697 iris_update_compiled_fs(ice
);
1699 /* Changing shader interfaces may require a URB configuration. */
1700 if (!(dirty
& IRIS_DIRTY_URB
)) {
1701 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1702 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1703 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1704 if (!!old
!= !!new ||
1705 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1706 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1713 static struct iris_compiled_shader
*
1714 iris_compile_cs(struct iris_context
*ice
,
1715 struct iris_uncompiled_shader
*ish
,
1716 const struct brw_cs_prog_key
*key
)
1718 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1719 const struct brw_compiler
*compiler
= screen
->compiler
;
1720 void *mem_ctx
= ralloc_context(NULL
);
1721 struct brw_cs_prog_data
*cs_prog_data
=
1722 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1723 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1724 enum brw_param_builtin
*system_values
;
1725 unsigned num_system_values
;
1728 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1730 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1732 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1733 &num_system_values
, &num_cbufs
);
1735 struct iris_binding_table bt
;
1736 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1737 num_system_values
, num_cbufs
);
1739 char *error_str
= NULL
;
1740 const unsigned *program
=
1741 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1742 nir
, -1, &error_str
);
1743 if (program
== NULL
) {
1744 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1745 ralloc_free(mem_ctx
);
1749 if (ish
->compiled_once
) {
1750 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1752 ish
->compiled_once
= true;
1755 struct iris_compiled_shader
*shader
=
1756 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1757 prog_data
, NULL
, system_values
, num_system_values
,
1760 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1762 ralloc_free(mem_ctx
);
1767 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1769 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
1770 struct iris_uncompiled_shader
*ish
=
1771 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1773 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1774 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1775 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1776 ice
->vtbl
.populate_cs_key(ice
, &key
);
1778 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1779 struct iris_compiled_shader
*shader
=
1780 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1783 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1786 shader
= iris_compile_cs(ice
, ish
, &key
);
1788 if (old
!= shader
) {
1789 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1790 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1791 IRIS_DIRTY_BINDINGS_CS
|
1792 IRIS_DIRTY_CONSTANTS_CS
;
1793 shs
->sysvals_need_upload
= true;
1798 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1801 assert(cs_prog_data
->push
.total
.size
> 0);
1802 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1803 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1804 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1805 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1810 * Allocate scratch BOs as needed for the given per-thread size and stage.
1813 iris_get_scratch_space(struct iris_context
*ice
,
1814 unsigned per_thread_scratch
,
1815 gl_shader_stage stage
)
1817 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1818 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1819 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1821 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1822 assert(encoded_size
< (1 << 16));
1824 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1826 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1828 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1829 * must allocate scratch space enough so that each slice has 4
1832 * According to the other driver team, this applies to compute shaders
1833 * as well. This is not currently documented at all.
1835 * This hack is no longer necessary on Gen11+.
1837 unsigned subslice_total
= screen
->subslice_total
;
1838 if (devinfo
->gen
< 11)
1839 subslice_total
= 4 * devinfo
->num_slices
;
1840 assert(subslice_total
>= screen
->subslice_total
);
1843 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1844 uint32_t max_threads
[] = {
1845 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1846 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1847 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1848 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1849 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1850 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1853 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1855 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1861 /* ------------------------------------------------------------------- */
1864 * The pipe->create_[stage]_state() driver hooks.
1866 * Performs basic NIR preprocessing, records any state dependencies, and
1867 * returns an iris_uncompiled_shader as the Gallium CSO.
1869 * Actual shader compilation to assembly happens later, at first use.
1872 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1874 const struct pipe_stream_output_info
*so_info
)
1876 struct iris_context
*ice
= (void *)ctx
;
1877 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1878 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1880 struct iris_uncompiled_shader
*ish
=
1881 calloc(1, sizeof(struct iris_uncompiled_shader
));
1885 brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1887 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1888 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1892 if (nir
->constant_data_size
> 0) {
1893 unsigned data_offset
;
1894 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
1895 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
1897 struct pipe_shader_buffer psb
= {
1898 .buffer
= ish
->const_data
,
1899 .buffer_offset
= data_offset
,
1900 .buffer_size
= nir
->constant_data_size
,
1902 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
1905 ish
->program_id
= get_new_program_id(screen
);
1908 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1909 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1912 /* Save this now before potentially dropping nir->info.name */
1913 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1914 ish
->use_alt_mode
= true;
1916 if (screen
->disk_cache
) {
1917 /* Serialize the NIR to a binary blob that we can hash for the disk
1918 * cache. First, drop unnecessary information (like variable names)
1919 * so the serialized NIR is smaller, and also to let us detect more
1920 * isomorphic shaders when hashing, increasing cache hits. We clone
1921 * the NIR before stripping away this info because it can be useful
1922 * when inspecting and debugging shaders.
1924 nir_shader
*clone
= nir_shader_clone(NULL
, nir
);
1929 nir_serialize(&blob
, clone
);
1930 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
1939 static struct iris_uncompiled_shader
*
1940 iris_create_shader_state(struct pipe_context
*ctx
,
1941 const struct pipe_shader_state
*state
)
1943 struct nir_shader
*nir
;
1945 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1946 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1948 nir
= state
->ir
.nir
;
1950 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1954 iris_create_vs_state(struct pipe_context
*ctx
,
1955 const struct pipe_shader_state
*state
)
1957 struct iris_context
*ice
= (void *) ctx
;
1958 struct iris_screen
*screen
= (void *) ctx
->screen
;
1959 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1961 /* User clip planes */
1962 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1963 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
1965 if (screen
->precompile
) {
1966 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1967 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1969 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1970 iris_compile_vs(ice
, ish
, &key
);
1977 iris_create_tcs_state(struct pipe_context
*ctx
,
1978 const struct pipe_shader_state
*state
)
1980 struct iris_context
*ice
= (void *) ctx
;
1981 struct iris_screen
*screen
= (void *) ctx
->screen
;
1982 const struct brw_compiler
*compiler
= screen
->compiler
;
1983 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1984 struct shader_info
*info
= &ish
->nir
->info
;
1986 if (screen
->precompile
) {
1987 const unsigned _GL_TRIANGLES
= 0x0004;
1988 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1989 struct brw_tcs_prog_key key
= {
1990 KEY_INIT(devinfo
->gen
),
1991 // XXX: make sure the linker fills this out from the TES...
1992 .tes_primitive_mode
=
1993 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
1995 .outputs_written
= info
->outputs_written
,
1996 .patch_outputs_written
= info
->patch_outputs_written
,
1999 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
2000 * We don't have that information, so we randomly guess that the input
2001 * and output patches are the same size. This is a bad guess, but we
2002 * can't do much better.
2004 if (compiler
->use_tcs_8_patch
)
2005 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
2007 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2008 iris_compile_tcs(ice
, ish
, &key
);
2015 iris_create_tes_state(struct pipe_context
*ctx
,
2016 const struct pipe_shader_state
*state
)
2018 struct iris_context
*ice
= (void *) ctx
;
2019 struct iris_screen
*screen
= (void *) ctx
->screen
;
2020 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2021 struct shader_info
*info
= &ish
->nir
->info
;
2023 /* User clip planes */
2024 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2025 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2027 if (screen
->precompile
) {
2028 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2029 struct brw_tes_prog_key key
= {
2030 KEY_INIT(devinfo
->gen
),
2031 // XXX: not ideal, need TCS output/TES input unification
2032 .inputs_read
= info
->inputs_read
,
2033 .patch_inputs_read
= info
->patch_inputs_read
,
2036 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2037 iris_compile_tes(ice
, ish
, &key
);
2044 iris_create_gs_state(struct pipe_context
*ctx
,
2045 const struct pipe_shader_state
*state
)
2047 struct iris_context
*ice
= (void *) ctx
;
2048 struct iris_screen
*screen
= (void *) ctx
->screen
;
2049 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2051 /* User clip planes */
2052 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2053 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2055 if (screen
->precompile
) {
2056 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2057 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2059 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2060 iris_compile_gs(ice
, ish
, &key
);
2067 iris_create_fs_state(struct pipe_context
*ctx
,
2068 const struct pipe_shader_state
*state
)
2070 struct iris_context
*ice
= (void *) ctx
;
2071 struct iris_screen
*screen
= (void *) ctx
->screen
;
2072 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2073 struct shader_info
*info
= &ish
->nir
->info
;
2075 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
2076 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
2077 (1ull << IRIS_NOS_RASTERIZER
) |
2078 (1ull << IRIS_NOS_BLEND
);
2080 /* The program key needs the VUE map if there are > 16 inputs */
2081 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
2082 BRW_FS_VARYING_INPUT_MASK
) > 16) {
2083 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
2086 if (screen
->precompile
) {
2087 const uint64_t color_outputs
= info
->outputs_written
&
2088 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
2089 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
2090 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
2092 bool can_rearrange_varyings
=
2093 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
2095 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2096 struct brw_wm_prog_key key
= {
2097 KEY_INIT(devinfo
->gen
),
2098 .nr_color_regions
= util_bitcount(color_outputs
),
2099 .coherent_fb_fetch
= true,
2100 .input_slots_valid
=
2101 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
2104 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2105 iris_compile_fs(ice
, ish
, &key
, NULL
);
2112 iris_create_compute_state(struct pipe_context
*ctx
,
2113 const struct pipe_compute_state
*state
)
2115 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
2117 struct iris_context
*ice
= (void *) ctx
;
2118 struct iris_screen
*screen
= (void *) ctx
->screen
;
2119 struct iris_uncompiled_shader
*ish
=
2120 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
2122 // XXX: disallow more than 64KB of shared variables
2124 if (screen
->precompile
) {
2125 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2126 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2128 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2129 iris_compile_cs(ice
, ish
, &key
);
2136 * The pipe->delete_[stage]_state() driver hooks.
2138 * Frees the iris_uncompiled_shader.
2141 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
2143 struct iris_uncompiled_shader
*ish
= state
;
2144 struct iris_context
*ice
= (void *) ctx
;
2146 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
2147 ice
->shaders
.uncompiled
[stage
] = NULL
;
2148 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2151 if (ish
->const_data
) {
2152 pipe_resource_reference(&ish
->const_data
, NULL
);
2153 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
2156 ralloc_free(ish
->nir
);
2161 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
2163 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
2167 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
2169 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
2173 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
2175 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
2179 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
2181 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
2185 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
2187 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
2191 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
2193 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
2197 * The pipe->bind_[stage]_state() driver hook.
2199 * Binds an uncompiled shader as the current one for a particular stage.
2200 * Updates dirty tracking to account for the shader's NOS.
2203 bind_shader_state(struct iris_context
*ice
,
2204 struct iris_uncompiled_shader
*ish
,
2205 gl_shader_stage stage
)
2207 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2208 const uint64_t nos
= ish
? ish
->nos
: 0;
2210 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
2211 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
2213 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
2214 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
2215 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
2218 ice
->shaders
.uncompiled
[stage
] = ish
;
2219 ice
->state
.dirty
|= dirty_bit
;
2221 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
2222 * (or that they no longer need to do so).
2224 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
2226 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
2228 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
2233 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
2235 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2236 struct iris_uncompiled_shader
*new_ish
= state
;
2239 ice
->state
.window_space_position
!=
2240 new_ish
->nir
->info
.vs
.window_space_position
) {
2241 ice
->state
.window_space_position
=
2242 new_ish
->nir
->info
.vs
.window_space_position
;
2244 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
2246 IRIS_DIRTY_CC_VIEWPORT
;
2249 bind_shader_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
2253 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
2255 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
2259 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
2261 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2263 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2264 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
2265 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2267 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
2271 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
2273 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2275 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2276 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
2277 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2279 bind_shader_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
2283 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
2285 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2286 struct iris_uncompiled_shader
*old_ish
=
2287 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2288 struct iris_uncompiled_shader
*new_ish
= state
;
2290 const unsigned color_bits
=
2291 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
2292 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
2294 /* Fragment shader outputs influence HasWriteableRT */
2295 if (!old_ish
|| !new_ish
||
2296 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
2297 (new_ish
->nir
->info
.outputs_written
& color_bits
))
2298 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
2300 bind_shader_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
2304 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
2306 bind_shader_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
2310 iris_init_program_functions(struct pipe_context
*ctx
)
2312 ctx
->create_vs_state
= iris_create_vs_state
;
2313 ctx
->create_tcs_state
= iris_create_tcs_state
;
2314 ctx
->create_tes_state
= iris_create_tes_state
;
2315 ctx
->create_gs_state
= iris_create_gs_state
;
2316 ctx
->create_fs_state
= iris_create_fs_state
;
2317 ctx
->create_compute_state
= iris_create_compute_state
;
2319 ctx
->delete_vs_state
= iris_delete_vs_state
;
2320 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
2321 ctx
->delete_tes_state
= iris_delete_tes_state
;
2322 ctx
->delete_gs_state
= iris_delete_gs_state
;
2323 ctx
->delete_fs_state
= iris_delete_fs_state
;
2324 ctx
->delete_compute_state
= iris_delete_cs_state
;
2326 ctx
->bind_vs_state
= iris_bind_vs_state
;
2327 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2328 ctx
->bind_tes_state
= iris_bind_tes_state
;
2329 ctx
->bind_gs_state
= iris_bind_gs_state
;
2330 ctx
->bind_fs_state
= iris_bind_fs_state
;
2331 ctx
->bind_compute_state
= iris_bind_cs_state
;