2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/debug.h"
41 #include "compiler/nir/nir.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "compiler/nir/nir_serialize.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/compiler/brw_nir.h"
46 #include "iris_context.h"
47 #include "nir/tgsi_to_nir.h"
49 #define KEY_INIT_NO_ID(gen) \
50 .base.tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
51 .base.tex.compressed_multisample_layout_mask = ~0, \
52 .base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
53 #define KEY_INIT(gen) .base.program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
56 get_new_program_id(struct iris_screen
*screen
)
58 return p_atomic_inc_return(&screen
->program_id
);
62 upload_state(struct u_upload_mgr
*uploader
,
63 struct iris_state_ref
*ref
,
68 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
73 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
74 struct pipe_shader_buffer
*buf
,
75 struct iris_state_ref
*surf_state
,
78 struct pipe_context
*ctx
= &ice
->ctx
;
79 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
82 upload_state(ice
->state
.surface_uploader
, surf_state
,
83 screen
->isl_dev
.ss
.size
, 64);
85 surf_state
->res
= NULL
;
89 struct iris_resource
*res
= (void *) buf
->buffer
;
90 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
91 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
93 isl_buffer_fill_state(&screen
->isl_dev
, map
,
94 .address
= res
->bo
->gtt_offset
+ res
->offset
+
96 .size_B
= buf
->buffer_size
- res
->offset
,
97 .format
= ssbo
? ISL_FORMAT_RAW
98 : ISL_FORMAT_R32G32B32A32_FLOAT
,
99 .swizzle
= ISL_SWIZZLE_IDENTITY
,
101 .mocs
= ice
->vtbl
.mocs(res
->bo
));
105 get_aoa_deref_offset(nir_builder
*b
,
106 nir_deref_instr
*deref
,
109 unsigned array_size
= elem_size
;
110 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
112 while (deref
->deref_type
!= nir_deref_type_var
) {
113 assert(deref
->deref_type
== nir_deref_type_array
);
115 /* This level's element size is the previous level's array size */
116 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
117 assert(deref
->arr
.index
.ssa
);
118 offset
= nir_iadd(b
, offset
,
119 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
121 deref
= nir_deref_instr_parent(deref
);
122 assert(glsl_type_is_array(deref
->type
));
123 array_size
*= glsl_get_length(deref
->type
);
126 /* Accessing an invalid surface index with the dataport can result in a
127 * hang. According to the spec "if the index used to select an individual
128 * element is negative or greater than or equal to the size of the array,
129 * the results of the operation are undefined but may not lead to
130 * termination" -- which is one of the possible outcomes of the hang.
131 * Clamp the index to prevent access outside of the array bounds.
133 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
137 iris_lower_storage_image_derefs(nir_shader
*nir
)
139 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
142 nir_builder_init(&b
, impl
);
144 nir_foreach_block(block
, impl
) {
145 nir_foreach_instr_safe(instr
, block
) {
146 if (instr
->type
!= nir_instr_type_intrinsic
)
149 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
150 switch (intrin
->intrinsic
) {
151 case nir_intrinsic_image_deref_load
:
152 case nir_intrinsic_image_deref_store
:
153 case nir_intrinsic_image_deref_atomic_add
:
154 case nir_intrinsic_image_deref_atomic_min
:
155 case nir_intrinsic_image_deref_atomic_max
:
156 case nir_intrinsic_image_deref_atomic_and
:
157 case nir_intrinsic_image_deref_atomic_or
:
158 case nir_intrinsic_image_deref_atomic_xor
:
159 case nir_intrinsic_image_deref_atomic_exchange
:
160 case nir_intrinsic_image_deref_atomic_comp_swap
:
161 case nir_intrinsic_image_deref_size
:
162 case nir_intrinsic_image_deref_samples
:
163 case nir_intrinsic_image_deref_load_raw_intel
:
164 case nir_intrinsic_image_deref_store_raw_intel
: {
165 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
166 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
168 b
.cursor
= nir_before_instr(&intrin
->instr
);
170 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
171 get_aoa_deref_offset(&b
, deref
, 1));
172 nir_rewrite_image_intrinsic(intrin
, index
, false);
183 // XXX: need unify_interfaces() at link time...
186 * Fix an uncompiled shader's stream output info.
188 * Core Gallium stores output->register_index as a "slot" number, where
189 * slots are assigned consecutively to all outputs in info->outputs_written.
190 * This naive packing of outputs doesn't work for us - we too have slots,
191 * but the layout is defined by the VUE map, which we won't have until we
192 * compile a specific shader variant. So, we remap these and simply store
193 * VARYING_SLOT_* in our copy's output->register_index fields.
195 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
196 * components of our VUE header. See brw_vue_map.c for the layout.
199 update_so_info(struct pipe_stream_output_info
*so_info
,
200 uint64_t outputs_written
)
202 uint8_t reverse_map
[64] = {};
204 while (outputs_written
) {
205 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
208 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
209 struct pipe_stream_output
*output
= &so_info
->output
[i
];
211 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
212 output
->register_index
= reverse_map
[output
->register_index
];
214 /* The VUE header contains three scalar fields packed together:
215 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
216 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
217 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
219 switch (output
->register_index
) {
220 case VARYING_SLOT_LAYER
:
221 assert(output
->num_components
== 1);
222 output
->register_index
= VARYING_SLOT_PSIZ
;
223 output
->start_component
= 1;
225 case VARYING_SLOT_VIEWPORT
:
226 assert(output
->num_components
== 1);
227 output
->register_index
= VARYING_SLOT_PSIZ
;
228 output
->start_component
= 2;
230 case VARYING_SLOT_PSIZ
:
231 assert(output
->num_components
== 1);
232 output
->start_component
= 3;
236 //info->outputs_written |= 1ull << output->register_index;
241 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
242 unsigned offset
, unsigned n
)
244 assert(offset
% sizeof(uint32_t) == 0);
246 for (unsigned i
= 0; i
< n
; ++i
)
247 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
249 for (unsigned i
= n
; i
< 4; ++i
)
250 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
254 * Associate NIR uniform variables with the prog_data->param[] mechanism
255 * used by the backend. Also, decide which UBOs we'd like to push in an
256 * ideal situation (though the backend can reduce this).
259 iris_setup_uniforms(const struct brw_compiler
*compiler
,
262 struct brw_stage_prog_data
*prog_data
,
263 enum brw_param_builtin
**out_system_values
,
264 unsigned *out_num_system_values
,
265 unsigned *out_num_cbufs
)
267 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
269 /* The intel compiler assumes that num_uniforms is in bytes. For
270 * scalar that means 4 bytes per uniform slot.
272 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
274 nir
->num_uniforms
*= 4;
276 const unsigned IRIS_MAX_SYSTEM_VALUES
=
277 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
278 enum brw_param_builtin
*system_values
=
279 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
280 unsigned num_system_values
= 0;
282 unsigned patch_vert_idx
= -1;
283 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
284 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
285 memset(ucp_idx
, -1, sizeof(ucp_idx
));
286 memset(img_idx
, -1, sizeof(img_idx
));
288 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
291 nir_builder_init(&b
, impl
);
293 b
.cursor
= nir_before_block(nir_start_block(impl
));
294 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
295 nir_ssa_def
*temp_const_ubo_name
= NULL
;
297 /* Turn system value intrinsics into uniforms */
298 nir_foreach_block(block
, impl
) {
299 nir_foreach_instr_safe(instr
, block
) {
300 if (instr
->type
!= nir_instr_type_intrinsic
)
303 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
306 switch (intrin
->intrinsic
) {
307 case nir_intrinsic_load_constant
: {
308 /* This one is special because it reads from the shader constant
309 * data and not cbuf0 which gallium uploads for us.
311 b
.cursor
= nir_before_instr(instr
);
312 nir_ssa_def
*offset
=
313 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
314 nir_intrinsic_base(intrin
));
316 if (temp_const_ubo_name
== NULL
)
317 temp_const_ubo_name
= nir_imm_int(&b
, 0);
319 nir_intrinsic_instr
*load_ubo
=
320 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
321 load_ubo
->num_components
= intrin
->num_components
;
322 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
323 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
324 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
325 intrin
->dest
.ssa
.num_components
,
326 intrin
->dest
.ssa
.bit_size
,
327 intrin
->dest
.ssa
.name
);
328 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
330 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
331 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
332 nir_instr_remove(&intrin
->instr
);
335 case nir_intrinsic_load_user_clip_plane
: {
336 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
338 if (ucp_idx
[ucp
] == -1) {
339 ucp_idx
[ucp
] = num_system_values
;
340 num_system_values
+= 4;
343 for (int i
= 0; i
< 4; i
++) {
344 system_values
[ucp_idx
[ucp
] + i
] =
345 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
348 b
.cursor
= nir_before_instr(instr
);
349 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
352 case nir_intrinsic_load_patch_vertices_in
:
353 if (patch_vert_idx
== -1)
354 patch_vert_idx
= num_system_values
++;
356 system_values
[patch_vert_idx
] =
357 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
359 b
.cursor
= nir_before_instr(instr
);
360 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
362 case nir_intrinsic_image_deref_load_param_intel
: {
363 assert(devinfo
->gen
< 9);
364 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
365 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
367 if (img_idx
[var
->data
.binding
] == -1) {
368 /* GL only allows arrays of arrays of images. */
369 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
370 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
372 for (int i
= 0; i
< num_images
; i
++) {
373 const unsigned img
= var
->data
.binding
+ i
;
375 img_idx
[img
] = num_system_values
;
376 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
378 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
380 setup_vec4_image_sysval(
381 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
382 offsetof(struct brw_image_param
, offset
), 2);
383 setup_vec4_image_sysval(
384 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
385 offsetof(struct brw_image_param
, size
), 3);
386 setup_vec4_image_sysval(
387 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
388 offsetof(struct brw_image_param
, stride
), 4);
389 setup_vec4_image_sysval(
390 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
391 offsetof(struct brw_image_param
, tiling
), 3);
392 setup_vec4_image_sysval(
393 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
394 offsetof(struct brw_image_param
, swizzling
), 2);
398 b
.cursor
= nir_before_instr(instr
);
399 offset
= nir_iadd(&b
,
400 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
401 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
402 nir_intrinsic_base(intrin
) * 16));
409 unsigned comps
= nir_intrinsic_dest_components(intrin
);
411 nir_intrinsic_instr
*load
=
412 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
413 load
->num_components
= comps
;
414 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
415 load
->src
[1] = nir_src_for_ssa(offset
);
416 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
417 nir_builder_instr_insert(&b
, &load
->instr
);
418 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
419 nir_src_for_ssa(&load
->dest
.ssa
));
420 nir_instr_remove(instr
);
424 nir_validate_shader(nir
, "before remapping");
426 /* Uniforms are stored in constant buffer 0, the
427 * user-facing UBOs are indexed by one. So if any constant buffer is
428 * needed, the constant buffer 0 will be needed, so account for it.
430 unsigned num_cbufs
= nir
->info
.num_ubos
;
431 if (num_cbufs
|| nir
->num_uniforms
)
434 /* Place the new params in a new cbuf. */
435 if (num_system_values
> 0) {
436 unsigned sysval_cbuf_index
= num_cbufs
;
439 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
442 nir_foreach_block(block
, impl
) {
443 nir_foreach_instr_safe(instr
, block
) {
444 if (instr
->type
!= nir_instr_type_intrinsic
)
447 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
449 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
452 b
.cursor
= nir_before_instr(instr
);
454 assert(load
->src
[0].is_ssa
);
456 if (load
->src
[0].ssa
== temp_ubo_name
) {
457 nir_ssa_def
*imm
= nir_imm_int(&b
, sysval_cbuf_index
);
458 nir_instr_rewrite_src(instr
, &load
->src
[0],
459 nir_src_for_ssa(imm
));
464 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
465 nir_opt_constant_folding(nir
);
467 ralloc_free(system_values
);
468 system_values
= NULL
;
471 assert(num_cbufs
< PIPE_MAX_CONSTANT_BUFFERS
);
472 nir_validate_shader(nir
, "after remap");
474 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
475 * about it for compute shaders, so go ahead and make some fake ones
476 * which the backend will dead code eliminate.
478 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
479 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
481 /* Constant loads (if any) need to go at the end of the constant buffers so
482 * we need to know num_cbufs before we can lower to them.
484 if (temp_const_ubo_name
!= NULL
) {
485 nir_load_const_instr
*const_ubo_index
=
486 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
487 assert(const_ubo_index
->def
.bit_size
== 32);
488 const_ubo_index
->value
[0].u32
= num_cbufs
;
491 *out_system_values
= system_values
;
492 *out_num_system_values
= num_system_values
;
493 *out_num_cbufs
= num_cbufs
;
496 static const char *surface_group_names
[] = {
497 [IRIS_SURFACE_GROUP_RENDER_TARGET
] = "render target",
498 [IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = "CS work groups",
499 [IRIS_SURFACE_GROUP_TEXTURE
] = "texture",
500 [IRIS_SURFACE_GROUP_UBO
] = "ubo",
501 [IRIS_SURFACE_GROUP_SSBO
] = "ssbo",
502 [IRIS_SURFACE_GROUP_IMAGE
] = "image",
506 iris_print_binding_table(FILE *fp
, const char *name
,
507 const struct iris_binding_table
*bt
)
509 STATIC_ASSERT(ARRAY_SIZE(surface_group_names
) == IRIS_SURFACE_GROUP_COUNT
);
512 uint32_t compacted
= 0;
514 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
515 uint32_t size
= bt
->sizes
[i
];
518 compacted
+= util_bitcount64(bt
->used_mask
[i
]);
522 fprintf(fp
, "Binding table for %s is empty\n\n", name
);
526 if (total
!= compacted
) {
527 fprintf(fp
, "Binding table for %s "
528 "(compacted to %u entries from %u entries)\n",
529 name
, compacted
, total
);
531 fprintf(fp
, "Binding table for %s (%u entries)\n", name
, total
);
535 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
536 uint64_t mask
= bt
->used_mask
[i
];
538 int index
= u_bit_scan64(&mask
);
539 fprintf(fp
, " [%u] %s #%d\n", entry
++, surface_group_names
[i
], index
);
546 /* Max elements in a surface group. */
547 SURFACE_GROUP_MAX_ELEMENTS
= 64,
551 * Map a <group, index> pair to a binding table index.
553 * For example: <UBO, 5> => binding table index 12
556 iris_group_index_to_bti(const struct iris_binding_table
*bt
,
557 enum iris_surface_group group
, uint32_t index
)
559 assert(index
< bt
->sizes
[group
]);
560 uint64_t mask
= bt
->used_mask
[group
];
561 uint64_t bit
= 1ull << index
;
563 return bt
->offsets
[group
] + util_bitcount64((bit
- 1) & mask
);
565 return IRIS_SURFACE_NOT_USED
;
570 * Map a binding table index back to a <group, index> pair.
572 * For example: binding table index 12 => <UBO, 5>
575 iris_bti_to_group_index(const struct iris_binding_table
*bt
,
576 enum iris_surface_group group
, uint32_t bti
)
578 uint64_t used_mask
= bt
->used_mask
[group
];
579 assert(bti
>= bt
->offsets
[group
]);
581 uint32_t c
= bti
- bt
->offsets
[group
];
583 int i
= u_bit_scan64(&used_mask
);
589 return IRIS_SURFACE_NOT_USED
;
593 rewrite_src_with_bti(nir_builder
*b
, struct iris_binding_table
*bt
,
594 nir_instr
*instr
, nir_src
*src
,
595 enum iris_surface_group group
)
597 assert(bt
->sizes
[group
] > 0);
599 b
->cursor
= nir_before_instr(instr
);
601 if (nir_src_is_const(*src
)) {
602 uint32_t index
= nir_src_as_uint(*src
);
603 bti
= nir_imm_intN_t(b
, iris_group_index_to_bti(bt
, group
, index
),
606 /* Indirect usage makes all the surfaces of the group to be available,
607 * so we can just add the base.
609 assert(bt
->used_mask
[group
] == BITFIELD64_MASK(bt
->sizes
[group
]));
610 bti
= nir_iadd_imm(b
, src
->ssa
, bt
->offsets
[group
]);
612 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(bti
));
616 mark_used_with_src(struct iris_binding_table
*bt
, nir_src
*src
,
617 enum iris_surface_group group
)
619 assert(bt
->sizes
[group
] > 0);
621 if (nir_src_is_const(*src
)) {
622 uint64_t index
= nir_src_as_uint(*src
);
623 assert(index
< bt
->sizes
[group
]);
624 bt
->used_mask
[group
] |= 1ull << index
;
626 /* There's an indirect usage, we need all the surfaces. */
627 bt
->used_mask
[group
] = BITFIELD64_MASK(bt
->sizes
[group
]);
632 skip_compacting_binding_tables(void)
634 static int skip
= -1;
636 skip
= env_var_as_boolean("INTEL_DISABLE_COMPACT_BINDING_TABLE", false);
641 * Set up the binding table indices and apply to the shader.
644 iris_setup_binding_table(struct nir_shader
*nir
,
645 struct iris_binding_table
*bt
,
646 unsigned num_render_targets
,
647 unsigned num_system_values
,
650 const struct shader_info
*info
= &nir
->info
;
652 memset(bt
, 0, sizeof(*bt
));
654 /* Set the sizes for each surface group. For some groups, we already know
655 * upfront how many will be used, so mark them.
657 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
658 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET
] = num_render_targets
;
659 /* All render targets used. */
660 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET
] =
661 BITFIELD64_MASK(num_render_targets
);
662 } else if (info
->stage
== MESA_SHADER_COMPUTE
) {
663 bt
->sizes
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
666 bt
->sizes
[IRIS_SURFACE_GROUP_TEXTURE
] = util_last_bit(info
->textures_used
);
667 bt
->used_mask
[IRIS_SURFACE_GROUP_TEXTURE
] = info
->textures_used
;
669 bt
->sizes
[IRIS_SURFACE_GROUP_IMAGE
] = info
->num_images
;
671 /* Allocate an extra slot in the UBO section for NIR constants.
672 * Binding table compaction will remove it if unnecessary.
674 * We don't include them in iris_compiled_shader::num_cbufs because
675 * they are uploaded separately from shs->constbuf[], but from a shader
676 * point of view, they're another UBO (at the end of the section).
678 bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] = num_cbufs
+ 1;
680 /* The first IRIS_MAX_ABOs indices in the SSBO group are for atomics, real
681 * SSBOs start after that. Compaction will remove unused ABOs.
683 bt
->sizes
[IRIS_SURFACE_GROUP_SSBO
] = IRIS_MAX_ABOS
+ info
->num_ssbos
;
685 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
686 assert(bt
->sizes
[i
] <= SURFACE_GROUP_MAX_ELEMENTS
);
688 /* Mark surfaces used for the cases we don't have the information available
691 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
692 nir_foreach_block (block
, impl
) {
693 nir_foreach_instr (instr
, block
) {
694 if (instr
->type
!= nir_instr_type_intrinsic
)
697 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
698 switch (intrin
->intrinsic
) {
699 case nir_intrinsic_load_num_work_groups
:
700 bt
->used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
703 case nir_intrinsic_image_size
:
704 case nir_intrinsic_image_load
:
705 case nir_intrinsic_image_store
:
706 case nir_intrinsic_image_atomic_add
:
707 case nir_intrinsic_image_atomic_min
:
708 case nir_intrinsic_image_atomic_max
:
709 case nir_intrinsic_image_atomic_and
:
710 case nir_intrinsic_image_atomic_or
:
711 case nir_intrinsic_image_atomic_xor
:
712 case nir_intrinsic_image_atomic_exchange
:
713 case nir_intrinsic_image_atomic_comp_swap
:
714 case nir_intrinsic_image_load_raw_intel
:
715 case nir_intrinsic_image_store_raw_intel
:
716 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_IMAGE
);
719 case nir_intrinsic_load_ubo
:
720 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_UBO
);
723 case nir_intrinsic_store_ssbo
:
724 mark_used_with_src(bt
, &intrin
->src
[1], IRIS_SURFACE_GROUP_SSBO
);
727 case nir_intrinsic_get_buffer_size
:
728 case nir_intrinsic_ssbo_atomic_add
:
729 case nir_intrinsic_ssbo_atomic_imin
:
730 case nir_intrinsic_ssbo_atomic_umin
:
731 case nir_intrinsic_ssbo_atomic_imax
:
732 case nir_intrinsic_ssbo_atomic_umax
:
733 case nir_intrinsic_ssbo_atomic_and
:
734 case nir_intrinsic_ssbo_atomic_or
:
735 case nir_intrinsic_ssbo_atomic_xor
:
736 case nir_intrinsic_ssbo_atomic_exchange
:
737 case nir_intrinsic_ssbo_atomic_comp_swap
:
738 case nir_intrinsic_ssbo_atomic_fmin
:
739 case nir_intrinsic_ssbo_atomic_fmax
:
740 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
741 case nir_intrinsic_load_ssbo
:
742 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_SSBO
);
751 /* When disable we just mark everything as used. */
752 if (unlikely(skip_compacting_binding_tables())) {
753 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
754 bt
->used_mask
[i
] = BITFIELD64_MASK(bt
->sizes
[i
]);
757 /* Calculate the offsets and the binding table size based on the used
758 * surfaces. After this point, the functions to go between "group indices"
759 * and binding table indices can be used.
762 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
763 if (bt
->used_mask
[i
] != 0) {
764 bt
->offsets
[i
] = next
;
765 next
+= util_bitcount64(bt
->used_mask
[i
]);
768 bt
->size_bytes
= next
* 4;
770 if (unlikely(INTEL_DEBUG
& DEBUG_BT
)) {
771 iris_print_binding_table(stderr
, gl_shader_stage_name(info
->stage
), bt
);
774 /* Apply the binding table indices. The backend compiler is not expected
775 * to change those, as we haven't set any of the *_start entries in brw
779 nir_builder_init(&b
, impl
);
781 nir_foreach_block (block
, impl
) {
782 nir_foreach_instr (instr
, block
) {
783 if (instr
->type
== nir_instr_type_tex
) {
784 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
786 iris_group_index_to_bti(bt
, IRIS_SURFACE_GROUP_TEXTURE
,
791 if (instr
->type
!= nir_instr_type_intrinsic
)
794 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
795 switch (intrin
->intrinsic
) {
796 case nir_intrinsic_image_size
:
797 case nir_intrinsic_image_load
:
798 case nir_intrinsic_image_store
:
799 case nir_intrinsic_image_atomic_add
:
800 case nir_intrinsic_image_atomic_min
:
801 case nir_intrinsic_image_atomic_max
:
802 case nir_intrinsic_image_atomic_and
:
803 case nir_intrinsic_image_atomic_or
:
804 case nir_intrinsic_image_atomic_xor
:
805 case nir_intrinsic_image_atomic_exchange
:
806 case nir_intrinsic_image_atomic_comp_swap
:
807 case nir_intrinsic_image_load_raw_intel
:
808 case nir_intrinsic_image_store_raw_intel
:
809 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
810 IRIS_SURFACE_GROUP_IMAGE
);
813 case nir_intrinsic_load_ubo
:
814 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
815 IRIS_SURFACE_GROUP_UBO
);
818 case nir_intrinsic_store_ssbo
:
819 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[1],
820 IRIS_SURFACE_GROUP_SSBO
);
823 case nir_intrinsic_get_buffer_size
:
824 case nir_intrinsic_ssbo_atomic_add
:
825 case nir_intrinsic_ssbo_atomic_imin
:
826 case nir_intrinsic_ssbo_atomic_umin
:
827 case nir_intrinsic_ssbo_atomic_imax
:
828 case nir_intrinsic_ssbo_atomic_umax
:
829 case nir_intrinsic_ssbo_atomic_and
:
830 case nir_intrinsic_ssbo_atomic_or
:
831 case nir_intrinsic_ssbo_atomic_xor
:
832 case nir_intrinsic_ssbo_atomic_exchange
:
833 case nir_intrinsic_ssbo_atomic_comp_swap
:
834 case nir_intrinsic_ssbo_atomic_fmin
:
835 case nir_intrinsic_ssbo_atomic_fmax
:
836 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
837 case nir_intrinsic_load_ssbo
:
838 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
839 IRIS_SURFACE_GROUP_SSBO
);
850 iris_debug_recompile(struct iris_context
*ice
,
851 struct shader_info
*info
,
852 const struct brw_base_prog_key
*key
)
854 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
855 const struct brw_compiler
*c
= screen
->compiler
;
860 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
861 _mesa_shader_stage_to_string(info
->stage
),
862 info
->name
? info
->name
: "(no identifier)",
863 info
->label
? info
->label
: "");
865 const void *old_key
=
866 iris_find_previous_compile(ice
, info
->stage
, key
->program_string_id
);
868 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
873 * Compile a vertex shader, and upload the assembly.
875 static struct iris_compiled_shader
*
876 iris_compile_vs(struct iris_context
*ice
,
877 struct iris_uncompiled_shader
*ish
,
878 const struct brw_vs_prog_key
*key
)
880 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
881 const struct brw_compiler
*compiler
= screen
->compiler
;
882 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
883 void *mem_ctx
= ralloc_context(NULL
);
884 struct brw_vs_prog_data
*vs_prog_data
=
885 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
886 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
887 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
888 enum brw_param_builtin
*system_values
;
889 unsigned num_system_values
;
892 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
894 if (key
->nr_userclip_plane_consts
) {
895 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
896 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
897 nir_lower_io_to_temporaries(nir
, impl
, true, false);
898 nir_lower_global_vars_to_local(nir
);
899 nir_lower_vars_to_ssa(nir
);
900 nir_shader_gather_info(nir
, impl
);
903 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
905 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
906 &num_system_values
, &num_cbufs
);
908 struct iris_binding_table bt
;
909 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
910 num_system_values
, num_cbufs
);
912 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
914 brw_compute_vue_map(devinfo
,
915 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
916 nir
->info
.separate_shader
);
918 /* Don't tell the backend about our clip plane constants, we've already
919 * lowered them in NIR and we don't want it doing it again.
921 struct brw_vs_prog_key key_no_ucp
= *key
;
922 key_no_ucp
.nr_userclip_plane_consts
= 0;
924 char *error_str
= NULL
;
925 const unsigned *program
=
926 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
927 nir
, -1, &error_str
);
928 if (program
== NULL
) {
929 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
930 ralloc_free(mem_ctx
);
934 if (ish
->compiled_once
) {
935 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
937 ish
->compiled_once
= true;
941 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
942 &vue_prog_data
->vue_map
);
944 struct iris_compiled_shader
*shader
=
945 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
946 prog_data
, so_decls
, system_values
, num_system_values
,
949 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
951 ralloc_free(mem_ctx
);
956 * Update the current vertex shader variant.
958 * Fill out the key, look in the cache, compile and bind if needed.
961 iris_update_compiled_vs(struct iris_context
*ice
)
963 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
964 struct iris_uncompiled_shader
*ish
=
965 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
966 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
967 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
969 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
970 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
972 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
973 struct iris_compiled_shader
*shader
=
974 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
977 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
980 shader
= iris_compile_vs(ice
, ish
, &key
);
983 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
984 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
985 IRIS_DIRTY_BINDINGS_VS
|
986 IRIS_DIRTY_CONSTANTS_VS
|
988 shs
->sysvals_need_upload
= true;
990 const struct brw_vs_prog_data
*vs_prog_data
=
991 (void *) shader
->prog_data
;
992 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
993 vs_prog_data
->uses_baseinstance
;
994 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
995 vs_prog_data
->uses_is_indexed_draw
;
996 const bool needs_sgvs_element
= uses_draw_params
||
997 vs_prog_data
->uses_instanceid
||
998 vs_prog_data
->uses_vertexid
;
999 bool needs_edge_flag
= false;
1000 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
1001 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
1002 needs_edge_flag
= true;
1005 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
1006 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
1007 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
1008 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
1009 IRIS_DIRTY_VERTEX_ELEMENTS
;
1011 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
1012 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
1013 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
1014 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
1019 * Get the shader_info for a given stage, or NULL if the stage is disabled.
1021 const struct shader_info
*
1022 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
1024 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
1029 const nir_shader
*nir
= ish
->nir
;
1034 * Get the union of TCS output and TES input slots.
1036 * TCS and TES need to agree on a common URB entry layout. In particular,
1037 * the data for all patch vertices is stored in a single URB entry (unlike
1038 * GS which has one entry per input vertex). This means that per-vertex
1039 * array indexing needs a stride.
1041 * SSO requires locations to match, but doesn't require the number of
1042 * outputs/inputs to match (in fact, the TCS often has extra outputs).
1043 * So, we need to take the extra step of unifying these on the fly.
1046 get_unified_tess_slots(const struct iris_context
*ice
,
1047 uint64_t *per_vertex_slots
,
1048 uint32_t *per_patch_slots
)
1050 const struct shader_info
*tcs
=
1051 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
1052 const struct shader_info
*tes
=
1053 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1055 *per_vertex_slots
= tes
->inputs_read
;
1056 *per_patch_slots
= tes
->patch_inputs_read
;
1059 *per_vertex_slots
|= tcs
->outputs_written
;
1060 *per_patch_slots
|= tcs
->patch_outputs_written
;
1065 * Compile a tessellation control shader, and upload the assembly.
1067 static struct iris_compiled_shader
*
1068 iris_compile_tcs(struct iris_context
*ice
,
1069 struct iris_uncompiled_shader
*ish
,
1070 const struct brw_tcs_prog_key
*key
)
1072 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1073 const struct brw_compiler
*compiler
= screen
->compiler
;
1074 const struct nir_shader_compiler_options
*options
=
1075 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
1076 void *mem_ctx
= ralloc_context(NULL
);
1077 struct brw_tcs_prog_data
*tcs_prog_data
=
1078 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
1079 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
1080 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1081 enum brw_param_builtin
*system_values
= NULL
;
1082 unsigned num_system_values
= 0;
1083 unsigned num_cbufs
= 0;
1087 struct iris_binding_table bt
;
1090 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1092 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1093 &num_system_values
, &num_cbufs
);
1094 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1095 num_system_values
, num_cbufs
);
1096 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1098 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
1100 /* Reserve space for passing the default tess levels as constants. */
1102 num_system_values
= 8;
1104 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
1105 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
1106 prog_data
->nr_params
= num_system_values
;
1108 if (key
->tes_primitive_mode
== GL_QUADS
) {
1109 for (int i
= 0; i
< 4; i
++)
1110 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1112 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1113 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
1114 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
1115 for (int i
= 0; i
< 3; i
++)
1116 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1118 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1120 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
1121 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
1122 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
1125 /* Manually setup the TCS binding table. */
1126 memset(&bt
, 0, sizeof(bt
));
1127 bt
.sizes
[IRIS_SURFACE_GROUP_UBO
] = 1;
1128 bt
.used_mask
[IRIS_SURFACE_GROUP_UBO
] = 1;
1131 prog_data
->ubo_ranges
[0].length
= 1;
1134 char *error_str
= NULL
;
1135 const unsigned *program
=
1136 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
1138 if (program
== NULL
) {
1139 dbg_printf("Failed to compile control shader: %s\n", error_str
);
1140 ralloc_free(mem_ctx
);
1145 if (ish
->compiled_once
) {
1146 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1148 ish
->compiled_once
= true;
1152 struct iris_compiled_shader
*shader
=
1153 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
1154 prog_data
, NULL
, system_values
, num_system_values
,
1158 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1160 ralloc_free(mem_ctx
);
1165 * Update the current tessellation control shader variant.
1167 * Fill out the key, look in the cache, compile and bind if needed.
1170 iris_update_compiled_tcs(struct iris_context
*ice
)
1172 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
1173 struct iris_uncompiled_shader
*tcs
=
1174 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
1175 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1176 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1178 const struct shader_info
*tes_info
=
1179 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1180 struct brw_tcs_prog_key key
= {
1181 KEY_INIT_NO_ID(devinfo
->gen
),
1182 .base
.program_string_id
= tcs
? tcs
->program_id
: 0,
1183 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
1184 .input_vertices
= ice
->state
.vertices_per_patch
,
1186 get_unified_tess_slots(ice
, &key
.outputs_written
,
1187 &key
.patch_outputs_written
);
1188 ice
->vtbl
.populate_tcs_key(ice
, &key
);
1190 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
1191 struct iris_compiled_shader
*shader
=
1192 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
1195 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
1198 shader
= iris_compile_tcs(ice
, tcs
, &key
);
1200 if (old
!= shader
) {
1201 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
1202 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
1203 IRIS_DIRTY_BINDINGS_TCS
|
1204 IRIS_DIRTY_CONSTANTS_TCS
;
1205 shs
->sysvals_need_upload
= true;
1210 * Compile a tessellation evaluation shader, and upload the assembly.
1212 static struct iris_compiled_shader
*
1213 iris_compile_tes(struct iris_context
*ice
,
1214 struct iris_uncompiled_shader
*ish
,
1215 const struct brw_tes_prog_key
*key
)
1217 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1218 const struct brw_compiler
*compiler
= screen
->compiler
;
1219 void *mem_ctx
= ralloc_context(NULL
);
1220 struct brw_tes_prog_data
*tes_prog_data
=
1221 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1222 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1223 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1224 enum brw_param_builtin
*system_values
;
1225 unsigned num_system_values
;
1228 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1230 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1231 &num_system_values
, &num_cbufs
);
1233 struct iris_binding_table bt
;
1234 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1235 num_system_values
, num_cbufs
);
1237 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1239 struct brw_vue_map input_vue_map
;
1240 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1241 key
->patch_inputs_read
);
1243 char *error_str
= NULL
;
1244 const unsigned *program
=
1245 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
1246 tes_prog_data
, nir
, NULL
, -1, &error_str
);
1247 if (program
== NULL
) {
1248 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1249 ralloc_free(mem_ctx
);
1253 if (ish
->compiled_once
) {
1254 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1256 ish
->compiled_once
= true;
1259 uint32_t *so_decls
=
1260 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1261 &vue_prog_data
->vue_map
);
1264 struct iris_compiled_shader
*shader
=
1265 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1266 prog_data
, so_decls
, system_values
, num_system_values
,
1269 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1271 ralloc_free(mem_ctx
);
1276 * Update the current tessellation evaluation shader variant.
1278 * Fill out the key, look in the cache, compile and bind if needed.
1281 iris_update_compiled_tes(struct iris_context
*ice
)
1283 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
1284 struct iris_uncompiled_shader
*ish
=
1285 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1286 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1287 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1289 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1290 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1291 ice
->vtbl
.populate_tes_key(ice
, &key
);
1293 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1294 struct iris_compiled_shader
*shader
=
1295 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1298 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1301 shader
= iris_compile_tes(ice
, ish
, &key
);
1303 if (old
!= shader
) {
1304 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1305 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1306 IRIS_DIRTY_BINDINGS_TES
|
1307 IRIS_DIRTY_CONSTANTS_TES
;
1308 shs
->sysvals_need_upload
= true;
1311 /* TODO: Could compare and avoid flagging this. */
1312 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1313 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1314 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1315 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].sysvals_need_upload
= true;
1320 * Compile a geometry shader, and upload the assembly.
1322 static struct iris_compiled_shader
*
1323 iris_compile_gs(struct iris_context
*ice
,
1324 struct iris_uncompiled_shader
*ish
,
1325 const struct brw_gs_prog_key
*key
)
1327 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1328 const struct brw_compiler
*compiler
= screen
->compiler
;
1329 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1330 void *mem_ctx
= ralloc_context(NULL
);
1331 struct brw_gs_prog_data
*gs_prog_data
=
1332 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1333 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1334 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1335 enum brw_param_builtin
*system_values
;
1336 unsigned num_system_values
;
1339 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1341 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1342 &num_system_values
, &num_cbufs
);
1344 struct iris_binding_table bt
;
1345 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1346 num_system_values
, num_cbufs
);
1348 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1350 brw_compute_vue_map(devinfo
,
1351 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1352 nir
->info
.separate_shader
);
1354 char *error_str
= NULL
;
1355 const unsigned *program
=
1356 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1357 NULL
, -1, &error_str
);
1358 if (program
== NULL
) {
1359 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1360 ralloc_free(mem_ctx
);
1364 if (ish
->compiled_once
) {
1365 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1367 ish
->compiled_once
= true;
1370 uint32_t *so_decls
=
1371 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1372 &vue_prog_data
->vue_map
);
1374 struct iris_compiled_shader
*shader
=
1375 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1376 prog_data
, so_decls
, system_values
, num_system_values
,
1379 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1381 ralloc_free(mem_ctx
);
1386 * Update the current geometry shader variant.
1388 * Fill out the key, look in the cache, compile and bind if needed.
1391 iris_update_compiled_gs(struct iris_context
*ice
)
1393 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
1394 struct iris_uncompiled_shader
*ish
=
1395 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1396 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1397 struct iris_compiled_shader
*shader
= NULL
;
1400 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1401 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1402 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1403 ice
->vtbl
.populate_gs_key(ice
, &key
);
1406 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1409 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1412 shader
= iris_compile_gs(ice
, ish
, &key
);
1415 if (old
!= shader
) {
1416 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1417 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1418 IRIS_DIRTY_BINDINGS_GS
|
1419 IRIS_DIRTY_CONSTANTS_GS
;
1420 shs
->sysvals_need_upload
= true;
1425 * Compile a fragment (pixel) shader, and upload the assembly.
1427 static struct iris_compiled_shader
*
1428 iris_compile_fs(struct iris_context
*ice
,
1429 struct iris_uncompiled_shader
*ish
,
1430 const struct brw_wm_prog_key
*key
,
1431 struct brw_vue_map
*vue_map
)
1433 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1434 const struct brw_compiler
*compiler
= screen
->compiler
;
1435 void *mem_ctx
= ralloc_context(NULL
);
1436 struct brw_wm_prog_data
*fs_prog_data
=
1437 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1438 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1439 enum brw_param_builtin
*system_values
;
1440 unsigned num_system_values
;
1443 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1445 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1447 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1448 &num_system_values
, &num_cbufs
);
1450 struct iris_binding_table bt
;
1451 iris_setup_binding_table(nir
, &bt
, MAX2(key
->nr_color_regions
, 1),
1452 num_system_values
, num_cbufs
);
1454 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1456 char *error_str
= NULL
;
1457 const unsigned *program
=
1458 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1459 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
1460 if (program
== NULL
) {
1461 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1462 ralloc_free(mem_ctx
);
1466 if (ish
->compiled_once
) {
1467 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1469 ish
->compiled_once
= true;
1472 struct iris_compiled_shader
*shader
=
1473 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1474 prog_data
, NULL
, system_values
, num_system_values
,
1477 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1479 ralloc_free(mem_ctx
);
1484 * Update the current fragment shader variant.
1486 * Fill out the key, look in the cache, compile and bind if needed.
1489 iris_update_compiled_fs(struct iris_context
*ice
)
1491 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_FRAGMENT
];
1492 struct iris_uncompiled_shader
*ish
=
1493 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1494 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1495 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1496 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1497 ice
->vtbl
.populate_fs_key(ice
, &key
);
1499 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1500 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1502 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1503 struct iris_compiled_shader
*shader
=
1504 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1507 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1510 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1512 if (old
!= shader
) {
1513 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1514 // toggles. might be able to avoid flagging SBE too.
1515 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1516 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1517 IRIS_DIRTY_BINDINGS_FS
|
1518 IRIS_DIRTY_CONSTANTS_FS
|
1522 shs
->sysvals_need_upload
= true;
1527 * Get the compiled shader for the last enabled geometry stage.
1529 * This stage is the one which will feed stream output and the rasterizer.
1531 static gl_shader_stage
1532 last_vue_stage(struct iris_context
*ice
)
1534 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
1535 return MESA_SHADER_GEOMETRY
;
1537 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
1538 return MESA_SHADER_TESS_EVAL
;
1540 return MESA_SHADER_VERTEX
;
1544 * Update the last enabled stage's VUE map.
1546 * When the shader feeding the rasterizer's output interface changes, we
1547 * need to re-emit various packets.
1550 update_last_vue_map(struct iris_context
*ice
,
1551 struct brw_stage_prog_data
*prog_data
)
1553 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1554 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1555 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1556 const uint64_t changed_slots
=
1557 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1559 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1560 ice
->state
.num_viewports
=
1561 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1562 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1563 IRIS_DIRTY_SF_CL_VIEWPORT
|
1564 IRIS_DIRTY_CC_VIEWPORT
|
1565 IRIS_DIRTY_SCISSOR_RECT
|
1566 IRIS_DIRTY_UNCOMPILED_FS
|
1567 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1570 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1571 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1574 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1578 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1580 static struct brw_vue_prog_data
*
1581 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1583 if (!ice
->shaders
.prog
[stage
])
1586 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1589 // XXX: iris_compiled_shaders are space-leaking :(
1590 // XXX: do remember to unbind them if deleting them.
1593 * Update the current shader variants for the given state.
1595 * This should be called on every draw call to ensure that the correct
1596 * shaders are bound. It will also flag any dirty state triggered by
1597 * swapping out those shaders.
1600 iris_update_compiled_shaders(struct iris_context
*ice
)
1602 const uint64_t dirty
= ice
->state
.dirty
;
1604 struct brw_vue_prog_data
*old_prog_datas
[4];
1605 if (!(dirty
& IRIS_DIRTY_URB
)) {
1606 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1607 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1610 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1611 struct iris_uncompiled_shader
*tes
=
1612 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1614 iris_update_compiled_tcs(ice
);
1615 iris_update_compiled_tes(ice
);
1617 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1618 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1620 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1621 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1622 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1626 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1627 iris_update_compiled_vs(ice
);
1628 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1629 iris_update_compiled_gs(ice
);
1631 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1632 const struct iris_compiled_shader
*gs
=
1633 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1634 const struct iris_compiled_shader
*tes
=
1635 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1637 bool points_or_lines
= false;
1640 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1642 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1643 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1645 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1647 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1648 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1651 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1652 /* Outbound to XY Clip enables */
1653 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1654 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1658 gl_shader_stage last_stage
= last_vue_stage(ice
);
1659 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1660 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1661 update_last_vue_map(ice
, shader
->prog_data
);
1662 if (ice
->state
.streamout
!= shader
->streamout
) {
1663 ice
->state
.streamout
= shader
->streamout
;
1664 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1667 if (ice
->state
.streamout_active
) {
1668 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1669 struct iris_stream_output_target
*so
=
1670 (void *) ice
->state
.so_target
[i
];
1672 so
->stride
= ish
->stream_output
.stride
[i
] * sizeof(uint32_t);
1676 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1677 iris_update_compiled_fs(ice
);
1679 /* Changing shader interfaces may require a URB configuration. */
1680 if (!(dirty
& IRIS_DIRTY_URB
)) {
1681 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1682 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1683 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1684 if (!!old
!= !!new ||
1685 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1686 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1693 static struct iris_compiled_shader
*
1694 iris_compile_cs(struct iris_context
*ice
,
1695 struct iris_uncompiled_shader
*ish
,
1696 const struct brw_cs_prog_key
*key
)
1698 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1699 const struct brw_compiler
*compiler
= screen
->compiler
;
1700 void *mem_ctx
= ralloc_context(NULL
);
1701 struct brw_cs_prog_data
*cs_prog_data
=
1702 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1703 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1704 enum brw_param_builtin
*system_values
;
1705 unsigned num_system_values
;
1708 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1710 prog_data
->total_shared
= nir
->info
.cs
.shared_size
;
1712 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1713 &num_system_values
, &num_cbufs
);
1715 struct iris_binding_table bt
;
1716 iris_setup_binding_table(nir
, &bt
, /* num_render_targets */ 0,
1717 num_system_values
, num_cbufs
);
1719 char *error_str
= NULL
;
1720 const unsigned *program
=
1721 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1722 nir
, -1, &error_str
);
1723 if (program
== NULL
) {
1724 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1725 ralloc_free(mem_ctx
);
1729 if (ish
->compiled_once
) {
1730 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1732 ish
->compiled_once
= true;
1735 struct iris_compiled_shader
*shader
=
1736 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1737 prog_data
, NULL
, system_values
, num_system_values
,
1740 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1742 ralloc_free(mem_ctx
);
1747 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1749 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
1750 struct iris_uncompiled_shader
*ish
=
1751 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1753 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1754 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1755 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1756 ice
->vtbl
.populate_cs_key(ice
, &key
);
1758 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1759 struct iris_compiled_shader
*shader
=
1760 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1763 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1766 shader
= iris_compile_cs(ice
, ish
, &key
);
1768 if (old
!= shader
) {
1769 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1770 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1771 IRIS_DIRTY_BINDINGS_CS
|
1772 IRIS_DIRTY_CONSTANTS_CS
;
1773 shs
->sysvals_need_upload
= true;
1778 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1781 assert(cs_prog_data
->push
.total
.size
> 0);
1782 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1783 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1784 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1785 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1790 * Allocate scratch BOs as needed for the given per-thread size and stage.
1793 iris_get_scratch_space(struct iris_context
*ice
,
1794 unsigned per_thread_scratch
,
1795 gl_shader_stage stage
)
1797 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1798 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1799 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1801 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1802 assert(encoded_size
< (1 << 16));
1804 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1806 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1808 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1809 * must allocate scratch space enough so that each slice has 4
1812 * According to the other driver team, this applies to compute shaders
1813 * as well. This is not currently documented at all.
1815 * This hack is no longer necessary on Gen11+.
1817 unsigned subslice_total
= screen
->subslice_total
;
1818 if (devinfo
->gen
< 11)
1819 subslice_total
= 4 * devinfo
->num_slices
;
1820 assert(subslice_total
>= screen
->subslice_total
);
1823 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1824 uint32_t max_threads
[] = {
1825 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1826 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1827 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1828 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1829 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1830 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1833 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1835 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1841 /* ------------------------------------------------------------------- */
1844 * The pipe->create_[stage]_state() driver hooks.
1846 * Performs basic NIR preprocessing, records any state dependencies, and
1847 * returns an iris_uncompiled_shader as the Gallium CSO.
1849 * Actual shader compilation to assembly happens later, at first use.
1852 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1854 const struct pipe_stream_output_info
*so_info
)
1856 struct iris_context
*ice
= (void *)ctx
;
1857 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1858 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1860 struct iris_uncompiled_shader
*ish
=
1861 calloc(1, sizeof(struct iris_uncompiled_shader
));
1865 brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1867 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1868 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
1872 if (nir
->constant_data_size
> 0) {
1873 unsigned data_offset
;
1874 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
1875 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
1877 struct pipe_shader_buffer psb
= {
1878 .buffer
= ish
->const_data
,
1879 .buffer_offset
= data_offset
,
1880 .buffer_size
= nir
->constant_data_size
,
1882 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
1885 ish
->program_id
= get_new_program_id(screen
);
1888 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
1889 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
1892 /* Save this now before potentially dropping nir->info.name */
1893 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
1894 ish
->use_alt_mode
= true;
1896 if (screen
->disk_cache
) {
1897 /* Serialize the NIR to a binary blob that we can hash for the disk
1898 * cache. First, drop unnecessary information (like variable names)
1899 * so the serialized NIR is smaller, and also to let us detect more
1900 * isomorphic shaders when hashing, increasing cache hits. We clone
1901 * the NIR before stripping away this info because it can be useful
1902 * when inspecting and debugging shaders.
1904 nir_shader
*clone
= nir_shader_clone(NULL
, nir
);
1909 nir_serialize(&blob
, clone
);
1910 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
1919 static struct iris_uncompiled_shader
*
1920 iris_create_shader_state(struct pipe_context
*ctx
,
1921 const struct pipe_shader_state
*state
)
1923 struct nir_shader
*nir
;
1925 if (state
->type
== PIPE_SHADER_IR_TGSI
)
1926 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
1928 nir
= state
->ir
.nir
;
1930 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
1934 iris_create_vs_state(struct pipe_context
*ctx
,
1935 const struct pipe_shader_state
*state
)
1937 struct iris_context
*ice
= (void *) ctx
;
1938 struct iris_screen
*screen
= (void *) ctx
->screen
;
1939 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1941 /* User clip planes */
1942 if (ish
->nir
->info
.clip_distance_array_size
== 0)
1943 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
1945 if (screen
->precompile
) {
1946 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1947 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1949 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1950 iris_compile_vs(ice
, ish
, &key
);
1957 iris_create_tcs_state(struct pipe_context
*ctx
,
1958 const struct pipe_shader_state
*state
)
1960 struct iris_context
*ice
= (void *) ctx
;
1961 struct iris_screen
*screen
= (void *) ctx
->screen
;
1962 const struct brw_compiler
*compiler
= screen
->compiler
;
1963 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
1964 struct shader_info
*info
= &ish
->nir
->info
;
1966 if (screen
->precompile
) {
1967 const unsigned _GL_TRIANGLES
= 0x0004;
1968 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1969 struct brw_tcs_prog_key key
= {
1970 KEY_INIT(devinfo
->gen
),
1971 // XXX: make sure the linker fills this out from the TES...
1972 .tes_primitive_mode
=
1973 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
1975 .outputs_written
= info
->outputs_written
,
1976 .patch_outputs_written
= info
->patch_outputs_written
,
1979 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
1980 * We don't have that information, so we randomly guess that the input
1981 * and output patches are the same size. This is a bad guess, but we
1982 * can't do much better.
1984 if (compiler
->use_tcs_8_patch
)
1985 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
1987 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
1988 iris_compile_tcs(ice
, ish
, &key
);
1995 iris_create_tes_state(struct pipe_context
*ctx
,
1996 const struct pipe_shader_state
*state
)
1998 struct iris_context
*ice
= (void *) ctx
;
1999 struct iris_screen
*screen
= (void *) ctx
->screen
;
2000 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2001 struct shader_info
*info
= &ish
->nir
->info
;
2003 if (screen
->precompile
) {
2004 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2005 struct brw_tes_prog_key key
= {
2006 KEY_INIT(devinfo
->gen
),
2007 // XXX: not ideal, need TCS output/TES input unification
2008 .inputs_read
= info
->inputs_read
,
2009 .patch_inputs_read
= info
->patch_inputs_read
,
2012 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2013 iris_compile_tes(ice
, ish
, &key
);
2020 iris_create_gs_state(struct pipe_context
*ctx
,
2021 const struct pipe_shader_state
*state
)
2023 struct iris_context
*ice
= (void *) ctx
;
2024 struct iris_screen
*screen
= (void *) ctx
->screen
;
2025 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2027 if (screen
->precompile
) {
2028 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2029 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2031 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2032 iris_compile_gs(ice
, ish
, &key
);
2039 iris_create_fs_state(struct pipe_context
*ctx
,
2040 const struct pipe_shader_state
*state
)
2042 struct iris_context
*ice
= (void *) ctx
;
2043 struct iris_screen
*screen
= (void *) ctx
->screen
;
2044 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2045 struct shader_info
*info
= &ish
->nir
->info
;
2047 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
2048 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
2049 (1ull << IRIS_NOS_RASTERIZER
) |
2050 (1ull << IRIS_NOS_BLEND
);
2052 /* The program key needs the VUE map if there are > 16 inputs */
2053 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
2054 BRW_FS_VARYING_INPUT_MASK
) > 16) {
2055 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
2058 if (screen
->precompile
) {
2059 const uint64_t color_outputs
= info
->outputs_written
&
2060 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
2061 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
2062 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
2064 bool can_rearrange_varyings
=
2065 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
2067 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2068 struct brw_wm_prog_key key
= {
2069 KEY_INIT(devinfo
->gen
),
2070 .nr_color_regions
= util_bitcount(color_outputs
),
2071 .coherent_fb_fetch
= true,
2072 .input_slots_valid
=
2073 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
2076 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2077 iris_compile_fs(ice
, ish
, &key
, NULL
);
2084 iris_create_compute_state(struct pipe_context
*ctx
,
2085 const struct pipe_compute_state
*state
)
2087 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
2089 struct iris_context
*ice
= (void *) ctx
;
2090 struct iris_screen
*screen
= (void *) ctx
->screen
;
2091 struct iris_uncompiled_shader
*ish
=
2092 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
2094 // XXX: disallow more than 64KB of shared variables
2096 if (screen
->precompile
) {
2097 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2098 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2100 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2101 iris_compile_cs(ice
, ish
, &key
);
2108 * The pipe->delete_[stage]_state() driver hooks.
2110 * Frees the iris_uncompiled_shader.
2113 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
2115 struct iris_uncompiled_shader
*ish
= state
;
2116 struct iris_context
*ice
= (void *) ctx
;
2118 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
2119 ice
->shaders
.uncompiled
[stage
] = NULL
;
2120 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2123 if (ish
->const_data
) {
2124 pipe_resource_reference(&ish
->const_data
, NULL
);
2125 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
2128 ralloc_free(ish
->nir
);
2133 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
2135 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
2139 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
2141 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
2145 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
2147 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
2151 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
2153 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
2157 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
2159 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
2163 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
2165 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
2169 * The pipe->bind_[stage]_state() driver hook.
2171 * Binds an uncompiled shader as the current one for a particular stage.
2172 * Updates dirty tracking to account for the shader's NOS.
2175 bind_shader_state(struct iris_context
*ice
,
2176 struct iris_uncompiled_shader
*ish
,
2177 gl_shader_stage stage
)
2179 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2180 const uint64_t nos
= ish
? ish
->nos
: 0;
2182 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
2183 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
2185 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
2186 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
2187 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
2190 ice
->shaders
.uncompiled
[stage
] = ish
;
2191 ice
->state
.dirty
|= dirty_bit
;
2193 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
2194 * (or that they no longer need to do so).
2196 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
2198 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
2200 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
2205 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
2207 bind_shader_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
2211 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
2213 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
2217 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
2219 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2221 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2222 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
2223 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2225 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
2229 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
2231 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2233 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2234 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
2235 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2237 bind_shader_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
2241 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
2243 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2244 struct iris_uncompiled_shader
*old_ish
=
2245 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2246 struct iris_uncompiled_shader
*new_ish
= state
;
2248 const unsigned color_bits
=
2249 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
2250 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
2252 /* Fragment shader outputs influence HasWriteableRT */
2253 if (!old_ish
|| !new_ish
||
2254 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
2255 (new_ish
->nir
->info
.outputs_written
& color_bits
))
2256 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
2258 bind_shader_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
2262 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
2264 bind_shader_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
2268 iris_init_program_functions(struct pipe_context
*ctx
)
2270 ctx
->create_vs_state
= iris_create_vs_state
;
2271 ctx
->create_tcs_state
= iris_create_tcs_state
;
2272 ctx
->create_tes_state
= iris_create_tes_state
;
2273 ctx
->create_gs_state
= iris_create_gs_state
;
2274 ctx
->create_fs_state
= iris_create_fs_state
;
2275 ctx
->create_compute_state
= iris_create_compute_state
;
2277 ctx
->delete_vs_state
= iris_delete_vs_state
;
2278 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
2279 ctx
->delete_tes_state
= iris_delete_tes_state
;
2280 ctx
->delete_gs_state
= iris_delete_gs_state
;
2281 ctx
->delete_fs_state
= iris_delete_fs_state
;
2282 ctx
->delete_compute_state
= iris_delete_cs_state
;
2284 ctx
->bind_vs_state
= iris_bind_vs_state
;
2285 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2286 ctx
->bind_tes_state
= iris_bind_tes_state
;
2287 ctx
->bind_gs_state
= iris_bind_gs_state
;
2288 ctx
->bind_fs_state
= iris_bind_fs_state
;
2289 ctx
->bind_compute_state
= iris_bind_cs_state
;