src/gallium/drivers/iris/iris_program.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_screen.h"
  29 #include "util/u_atomic.h"
  30 #include "compiler/nir/nir.h"
  31 #include "compiler/nir/nir_builder.h"
  32 #include "intel/compiler/brw_compiler.h"
  33 #include "intel/compiler/brw_nir.h"
  34 #include "iris_context.h"
  35
  36 static unsigned
  37 get_new_program_id(struct iris_screen *screen)
  38 {
  39    return p_atomic_inc_return(&screen->program_id);
  40 }
  41
  42 struct iris_uncompiled_shader {
  43    struct pipe_shader_state base;
  44    unsigned program_id;
  45 };
  46
  47 // XXX: need unify_interfaces() at link time...
  48
  49 static void *
  50 iris_create_shader_state(struct pipe_context *ctx,
  51                          const struct pipe_shader_state *state)
  52 {
  53    //struct iris_context *ice = (struct iris_context *)ctx;
  54    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
  55
  56    assert(state->type == PIPE_SHADER_IR_NIR);
  57
  58    nir_shader *nir = state->ir.nir;
  59
  60    struct iris_uncompiled_shader *ish =
  61       calloc(1, sizeof(struct iris_uncompiled_shader));
  62    if (!ish)
  63       return NULL;
  64
  65    nir = brw_preprocess_nir(screen->compiler, nir);
  66
  67    ish->program_id = get_new_program_id(screen);
  68    ish->base.type = PIPE_SHADER_IR_NIR;
  69    ish->base.ir.nir = nir;
  70
  71    return ish;
  72 }
  73
  74 static void
  75 iris_delete_shader_state(struct pipe_context *ctx, void *hwcso)
  76 {
  77    struct iris_uncompiled_shader *ish = hwcso;
  78
  79    ralloc_free(ish->base.ir.nir);
  80    free(ish);
  81 }
  82
  83 static void
  84 iris_bind_vs_state(struct pipe_context *ctx, void *hwcso)
  85 {
  86    struct iris_context *ice = (struct iris_context *)ctx;
  87
  88    ice->shaders.uncompiled[MESA_SHADER_VERTEX] = hwcso;
  89    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_VS;
  90 }
  91
  92 static void
  93 iris_bind_tcs_state(struct pipe_context *ctx, void *hwcso)
  94 {
  95    struct iris_context *ice = (struct iris_context *)ctx;
  96
  97    ice->shaders.uncompiled[MESA_SHADER_TESS_CTRL] = hwcso;
  98    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TCS;
  99 }
 100
 101 static void
 102 iris_bind_tes_state(struct pipe_context *ctx, void *hwcso)
 103 {
 104    struct iris_context *ice = (struct iris_context *)ctx;
 105
 106    if (!!hwcso != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
 107       ice->state.dirty |= IRIS_DIRTY_URB;
 108
 109    ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL] = hwcso;
 110    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_TES;
 111 }
 112
 113 static void
 114 iris_bind_gs_state(struct pipe_context *ctx, void *hwcso)
 115 {
 116    struct iris_context *ice = (struct iris_context *)ctx;
 117
 118    if (!!hwcso != !!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
 119       ice->state.dirty |= IRIS_DIRTY_URB;
 120
 121    ice->shaders.uncompiled[MESA_SHADER_GEOMETRY] = hwcso;
 122    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_GS;
 123 }
 124
 125 static void
 126 iris_bind_fs_state(struct pipe_context *ctx, void *hwcso)
 127 {
 128    struct iris_context *ice = (struct iris_context *)ctx;
 129
 130    ice->shaders.uncompiled[MESA_SHADER_FRAGMENT] = hwcso;
 131    ice->state.dirty |= IRIS_DIRTY_UNCOMPILED_FS;
 132 }
 133
 134 /**
 135  * Sets up the starting offsets for the groups of binding table entries
 136  * common to all pipeline stages.
 137  *
 138  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 139  * unused but also make sure that addition of small offsets to them will
 140  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 141  */
 142 static uint32_t
 143 assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
 144                                     const struct nir_shader *nir,
 145                                     struct brw_stage_prog_data *prog_data,
 146                                     uint32_t next_binding_table_offset)
 147 {
 148    const struct shader_info *info = &nir->info;
 149
 150    if (info->num_textures) {
 151       prog_data->binding_table.texture_start = next_binding_table_offset;
 152       prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 153       next_binding_table_offset += info->num_textures;
 154    } else {
 155       prog_data->binding_table.texture_start = 0xd0d0d0d0;
 156       prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
 157    }
 158
 159    int num_ubos = info->num_ubos + (nir->num_uniforms > 0 ? 1 : 0);
 160
 161    if (num_ubos) {
 162       //assert(info->num_ubos <= BRW_MAX_UBO);
 163       prog_data->binding_table.ubo_start = next_binding_table_offset;
 164       next_binding_table_offset += num_ubos;
 165    } else {
 166       prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 167    }
 168
 169    if (info->num_ssbos || info->num_abos) {
 170       //assert(info->num_abos <= BRW_MAX_ABO);
 171       //assert(info->num_ssbos <= BRW_MAX_SSBO);
 172       prog_data->binding_table.ssbo_start = next_binding_table_offset;
 173       next_binding_table_offset += info->num_abos + info->num_ssbos;
 174    } else {
 175       prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
 176    }
 177
 178    prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 179
 180    if (info->num_images) {
 181       prog_data->binding_table.image_start = next_binding_table_offset;
 182       next_binding_table_offset += info->num_images;
 183    } else {
 184       prog_data->binding_table.image_start = 0xd0d0d0d0;
 185    }
 186
 187    /* This may or may not be used depending on how the compile goes. */
 188    prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 189    next_binding_table_offset++;
 190
 191    /* Plane 0 is just the regular texture section */
 192    prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
 193
 194    prog_data->binding_table.plane_start[1] = next_binding_table_offset;
 195    next_binding_table_offset += info->num_textures;
 196
 197    prog_data->binding_table.plane_start[2] = next_binding_table_offset;
 198    next_binding_table_offset += info->num_textures;
 199
 200    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 201
 202    //assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 203    return next_binding_table_offset;
 204 }
 205
 206 static void
 207 iris_setup_uniforms(const struct brw_compiler *compiler,
 208                     void *mem_ctx,
 209                     nir_shader *nir,
 210                     struct brw_stage_prog_data *prog_data)
 211 {
 212    prog_data->nr_params = nir->num_uniforms;
 213    prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
 214
 215    nir_foreach_variable(var, &nir->uniforms) {
 216       const unsigned components = glsl_get_components(var->type);
 217
 218       for (unsigned i = 0; i < components; i++) {
 219          prog_data->param[var->data.driver_location] =
 220             var->data.driver_location;
 221       }
 222    }
 223
 224    // XXX: vs clip planes?
 225    brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
 226 }
 227
 228 static void
 229 iris_setup_push_uniform_range(const struct brw_compiler *compiler,
 230                               struct brw_stage_prog_data *prog_data)
 231 {
 232    if (prog_data->nr_params) {
 233       for (int i = 3; i > 0; i--)
 234          prog_data->ubo_ranges[i] = prog_data->ubo_ranges[i - 1];
 235
 236       prog_data->ubo_ranges[0] = (struct brw_ubo_range) {
 237          .block = 0,
 238          .start = 0,
 239          .length = DIV_ROUND_UP(prog_data->nr_params, 8),
 240       };
 241    }
 242 }
 243
 244 static bool
 245 iris_compile_vs(struct iris_context *ice,
 246                 struct iris_uncompiled_shader *ish,
 247                 const struct brw_vs_prog_key *key)
 248 {
 249    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 250    const struct brw_compiler *compiler = screen->compiler;
 251    const struct gen_device_info *devinfo = &screen->devinfo;
 252    void *mem_ctx = ralloc_context(NULL);
 253    struct brw_vs_prog_data *vs_prog_data =
 254       rzalloc(mem_ctx, struct brw_vs_prog_data);
 255    struct brw_vue_prog_data *vue_prog_data = &vs_prog_data->base;
 256    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 257
 258    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 259
 260    nir_shader *nir = ish->base.ir.nir;
 261
 262    // XXX: alt mode
 263    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 264
 265    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 266
 267    brw_compute_vue_map(devinfo,
 268                        &vue_prog_data->vue_map, nir->info.outputs_written,
 269                        nir->info.separate_shader);
 270
 271    char *error_str = NULL;
 272    const unsigned *program =
 273       brw_compile_vs(compiler, &ice->dbg, mem_ctx, key, vs_prog_data,
 274                      nir, -1, &error_str);
 275    if (program == NULL) {
 276       dbg_printf("Failed to compile vertex shader: %s\n", error_str);
 277       ralloc_free(mem_ctx);
 278       return false;
 279    }
 280
 281    iris_setup_push_uniform_range(compiler, prog_data);
 282
 283    iris_upload_and_bind_shader(ice, IRIS_CACHE_VS, key, program, prog_data);
 284
 285    ralloc_free(mem_ctx);
 286    return true;
 287 }
 288
 289 static void
 290 iris_update_compiled_vs(struct iris_context *ice)
 291 {
 292    struct brw_vs_prog_key key;
 293    ice->vtbl.populate_vs_key(ice, &key);
 294
 295    if (iris_bind_cached_shader(ice, IRIS_CACHE_VS, &key))
 296       return;
 297
 298    UNUSED bool success =
 299       iris_compile_vs(ice, ice->shaders.uncompiled[MESA_SHADER_VERTEX], &key);
 300 }
 301
 302 static void
 303 iris_update_compiled_tcs(struct iris_context *ice)
 304 {
 305    // XXX: TCS
 306 }
 307
 308 static bool
 309 iris_compile_tes(struct iris_context *ice,
 310                  struct iris_uncompiled_shader *ish,
 311                  const struct brw_tes_prog_key *key)
 312 {
 313    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 314    const struct brw_compiler *compiler = screen->compiler;
 315    const struct gen_device_info *devinfo = &screen->devinfo;
 316    void *mem_ctx = ralloc_context(NULL);
 317    struct brw_tes_prog_data *tes_prog_data =
 318       rzalloc(mem_ctx, struct brw_tes_prog_data);
 319    struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
 320    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
 321
 322    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 323
 324    nir_shader *nir = ish->base.ir.nir;
 325
 326    assign_common_binding_table_offsets(devinfo, nir, prog_data, 0);
 327
 328    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 329
 330    struct brw_vue_map input_vue_map;
 331    brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
 332                             key->patch_inputs_read);
 333
 334    char *error_str = NULL;
 335    const unsigned *program =
 336       brw_compile_tes(compiler, &ice->dbg, mem_ctx, key, &input_vue_map,
 337                       tes_prog_data, nir, NULL, -1, &error_str);
 338    if (program == NULL) {
 339       dbg_printf("Failed to compile evaluation shader: %s\n", error_str);
 340       ralloc_free(mem_ctx);
 341       return false;
 342    }
 343
 344    iris_setup_push_uniform_range(compiler, prog_data);
 345
 346    iris_upload_and_bind_shader(ice, IRIS_CACHE_TES, key, program, prog_data);
 347
 348    ralloc_free(mem_ctx);
 349    return true;
 350 }
 351
 352
 353 static void
 354 iris_update_compiled_tes(struct iris_context *ice)
 355 {
 356    struct iris_uncompiled_shader *ish =
 357       ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
 358
 359    if (!ish)
 360       return;
 361
 362    struct brw_tes_prog_key key;
 363    ice->vtbl.populate_tes_key(ice, &key);
 364
 365    if (iris_bind_cached_shader(ice, IRIS_CACHE_TES, &key))
 366       return;
 367
 368    UNUSED bool success = iris_compile_tes(ice, ish, &key);
 369 }
 370
 371 static void
 372 iris_update_compiled_gs(struct iris_context *ice)
 373 {
 374    // XXX: GS
 375 }
 376
 377 static bool
 378 iris_compile_fs(struct iris_context *ice,
 379                 struct iris_uncompiled_shader *ish,
 380                 const struct brw_wm_prog_key *key,
 381                 struct brw_vue_map *vue_map)
 382 {
 383    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
 384    const struct brw_compiler *compiler = screen->compiler;
 385    const struct gen_device_info *devinfo = &screen->devinfo;
 386    void *mem_ctx = ralloc_context(NULL);
 387    struct brw_wm_prog_data *fs_prog_data =
 388       rzalloc(mem_ctx, struct brw_wm_prog_data);
 389    struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
 390
 391    assert(ish->base.type == PIPE_SHADER_IR_NIR);
 392
 393    nir_shader *nir = ish->base.ir.nir;
 394
 395    // XXX: alt mode
 396    assign_common_binding_table_offsets(devinfo, nir, prog_data,
 397                                        MAX2(key->nr_color_regions, 1));
 398
 399    iris_setup_uniforms(compiler, mem_ctx, nir, prog_data);
 400
 401    char *error_str = NULL;
 402    const unsigned *program =
 403       brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, fs_prog_data,
 404                      nir, NULL, -1, -1, -1, true, false, vue_map, &error_str);
 405    if (program == NULL) {
 406       dbg_printf("Failed to compile fragment shader: %s\n", error_str);
 407       ralloc_free(mem_ctx);
 408       return false;
 409    }
 410
 411    //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
 412
 413    iris_setup_push_uniform_range(compiler, prog_data);
 414
 415    iris_upload_and_bind_shader(ice, IRIS_CACHE_FS, key, program, prog_data);
 416
 417    ralloc_free(mem_ctx);
 418    return true;
 419 }
 420
 421 static void
 422 iris_update_compiled_fs(struct iris_context *ice)
 423 {
 424    struct brw_wm_prog_key key;
 425    ice->vtbl.populate_fs_key(ice, &key);
 426
 427    if (iris_bind_cached_shader(ice, IRIS_CACHE_FS, &key))
 428       return;
 429
 430    UNUSED bool success =
 431       iris_compile_fs(ice, ice->shaders.uncompiled[MESA_SHADER_FRAGMENT], &key,
 432                       ice->shaders.last_vue_map);
 433 }
 434
 435 static void
 436 update_last_vue_map(struct iris_context *ice)
 437 {
 438    struct brw_stage_prog_data *prog_data;
 439
 440    if (ice->shaders.prog[MESA_SHADER_GEOMETRY])
 441       prog_data = ice->shaders.prog[MESA_SHADER_GEOMETRY]->prog_data;
 442    else if (ice->shaders.prog[MESA_SHADER_TESS_EVAL])
 443       prog_data = ice->shaders.prog[MESA_SHADER_TESS_EVAL]->prog_data;
 444    else
 445       prog_data = ice->shaders.prog[MESA_SHADER_VERTEX]->prog_data;
 446
 447    struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
 448    struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
 449    struct brw_vue_map *old_map = ice->shaders.last_vue_map;
 450    const uint64_t changed_slots =
 451       (old_map ? old_map->slots_valid : 0ull) ^ vue_map->slots_valid;
 452
 453    if (changed_slots & VARYING_BIT_VIEWPORT) {
 454       // XXX: could use ctx->Const.MaxViewports for old API efficiency
 455       ice->state.num_viewports =
 456          (vue_map->slots_valid & VARYING_BIT_VIEWPORT) ? IRIS_MAX_VIEWPORTS : 1;
 457       ice->state.dirty |= IRIS_DIRTY_CLIP |
 458                           IRIS_DIRTY_SF_CL_VIEWPORT |
 459                           IRIS_DIRTY_SCISSOR_RECT |
 460                           IRIS_DIRTY_UNCOMPILED_FS;
 461       // XXX: CC_VIEWPORT?
 462    }
 463
 464    ice->shaders.last_vue_map = &vue_prog_data->vue_map;
 465 }
 466
 467 static struct brw_vue_prog_data *
 468 get_vue_prog_data(struct iris_context *ice, gl_shader_stage stage)
 469 {
 470    if (!ice->shaders.prog[stage])
 471       return NULL;
 472
 473    return (void *) ice->shaders.prog[stage]->prog_data;
 474 }
 475
 476 void
 477 iris_update_compiled_shaders(struct iris_context *ice)
 478 {
 479    const uint64_t dirty = ice->state.dirty;
 480
 481    struct brw_vue_prog_data *old_prog_datas[4];
 482    if (!(dirty & IRIS_DIRTY_URB)) {
 483       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++)
 484          old_prog_datas[i] = get_vue_prog_data(ice, i);
 485    }
 486
 487    if (dirty & IRIS_DIRTY_UNCOMPILED_VS)
 488       iris_update_compiled_vs(ice);
 489    if (dirty & IRIS_DIRTY_UNCOMPILED_TCS)
 490       iris_update_compiled_tcs(ice);
 491    if (dirty & IRIS_DIRTY_UNCOMPILED_TES)
 492       iris_update_compiled_tes(ice);
 493    if (dirty & IRIS_DIRTY_UNCOMPILED_GS)
 494       iris_update_compiled_gs(ice);
 495
 496    update_last_vue_map(ice);
 497
 498    if (dirty & IRIS_DIRTY_UNCOMPILED_FS)
 499       iris_update_compiled_fs(ice);
 500    // ...
 501
 502    if (!(dirty & IRIS_DIRTY_URB)) {
 503       for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 504          struct brw_vue_prog_data *old = old_prog_datas[i];
 505          struct brw_vue_prog_data *new = get_vue_prog_data(ice, i);
 506          if (!!old != !!new ||
 507              (new && new->urb_entry_size != old->urb_entry_size)) {
 508             ice->state.dirty |= IRIS_DIRTY_URB;
 509             break;
 510          }
 511       }
 512    }
 513 }
 514
 515 void
 516 iris_init_program_functions(struct pipe_context *ctx)
 517 {
 518    ctx->create_vs_state  = iris_create_shader_state;
 519    ctx->create_tcs_state = iris_create_shader_state;
 520    ctx->create_tes_state = iris_create_shader_state;
 521    ctx->create_gs_state  = iris_create_shader_state;
 522    ctx->create_fs_state  = iris_create_shader_state;
 523
 524    ctx->delete_vs_state  = iris_delete_shader_state;
 525    ctx->delete_tcs_state = iris_delete_shader_state;
 526    ctx->delete_tes_state = iris_delete_shader_state;
 527    ctx->delete_gs_state  = iris_delete_shader_state;
 528    ctx->delete_fs_state  = iris_delete_shader_state;
 529
 530    ctx->bind_vs_state  = iris_bind_vs_state;
 531    ctx->bind_tcs_state = iris_bind_tcs_state;
 532    ctx->bind_tes_state = iris_bind_tes_state;
 533    ctx->bind_gs_state  = iris_bind_gs_state;
 534    ctx->bind_fs_state  = iris_bind_fs_state;
 535 }