2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "compiler/nir/nir.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/compiler/brw_nir.h"
43 #include "iris_context.h"
46 get_new_program_id(struct iris_screen
*screen
)
48 return p_atomic_inc_return(&screen
->program_id
);
52 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
53 * It primarily contains the NIR for the shader.
55 * Each API-facing shader can be compiled into multiple shader variants,
56 * based on non-orthogonal state dependencies, recorded in the shader key.
58 * See iris_compiled_shader, which represents a compiled shader variant.
60 struct iris_uncompiled_shader
{
63 struct pipe_stream_output_info stream_output
;
67 /** Bitfield of (1 << IRIS_NOS_*) flags. */
72 get_aoa_deref_offset(nir_builder
*b
,
73 nir_deref_instr
*deref
,
76 unsigned array_size
= elem_size
;
77 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
79 while (deref
->deref_type
!= nir_deref_type_var
) {
80 assert(deref
->deref_type
== nir_deref_type_array
);
82 /* This level's element size is the previous level's array size */
83 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
84 assert(deref
->arr
.index
.ssa
);
85 offset
= nir_iadd(b
, offset
,
86 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
88 deref
= nir_deref_instr_parent(deref
);
89 assert(glsl_type_is_array(deref
->type
));
90 array_size
*= glsl_get_length(deref
->type
);
93 /* Accessing an invalid surface index with the dataport can result in a
94 * hang. According to the spec "if the index used to select an individual
95 * element is negative or greater than or equal to the size of the array,
96 * the results of the operation are undefined but may not lead to
97 * termination" -- which is one of the possible outcomes of the hang.
98 * Clamp the index to prevent access outside of the array bounds.
100 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
104 iris_lower_storage_image_derefs(nir_shader
*nir
)
106 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
109 nir_builder_init(&b
, impl
);
111 nir_foreach_block(block
, impl
) {
112 nir_foreach_instr_safe(instr
, block
) {
113 if (instr
->type
!= nir_instr_type_intrinsic
)
116 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
117 switch (intrin
->intrinsic
) {
118 case nir_intrinsic_image_deref_load
:
119 case nir_intrinsic_image_deref_store
:
120 case nir_intrinsic_image_deref_atomic_add
:
121 case nir_intrinsic_image_deref_atomic_min
:
122 case nir_intrinsic_image_deref_atomic_max
:
123 case nir_intrinsic_image_deref_atomic_and
:
124 case nir_intrinsic_image_deref_atomic_or
:
125 case nir_intrinsic_image_deref_atomic_xor
:
126 case nir_intrinsic_image_deref_atomic_exchange
:
127 case nir_intrinsic_image_deref_atomic_comp_swap
:
128 case nir_intrinsic_image_deref_size
:
129 case nir_intrinsic_image_deref_samples
: {
130 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
131 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
133 b
.cursor
= nir_before_instr(&intrin
->instr
);
135 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
136 get_aoa_deref_offset(&b
, deref
, 1));
137 brw_nir_rewrite_image_intrinsic(intrin
, index
);
150 // XXX: need unify_interfaces() at link time...
153 * The pipe->create_[stage]_state() driver hooks.
155 * Performs basic NIR preprocessing, records any state dependencies, and
156 * returns an iris_uncompiled_shader as the Gallium CSO.
158 * Actual shader compilation to assembly happens later, at first use.
161 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
163 const struct pipe_stream_output_info
*so_info
)
165 //struct iris_context *ice = (struct iris_context *)ctx;
166 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
167 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
169 struct iris_uncompiled_shader
*ish
=
170 calloc(1, sizeof(struct iris_uncompiled_shader
));
174 nir
= brw_preprocess_nir(screen
->compiler
, nir
);
176 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
177 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
179 ish
->program_id
= get_new_program_id(screen
);
182 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
184 switch (nir
->info
.stage
) {
185 case MESA_SHADER_VERTEX
:
186 /* User clip planes */
187 if (nir
->info
.clip_distance_array_size
== 0)
188 ish
->nos
|= IRIS_NOS_RASTERIZER
;
191 case MESA_SHADER_TESS_CTRL
:
194 case MESA_SHADER_TESS_EVAL
:
197 case MESA_SHADER_GEOMETRY
:
200 case MESA_SHADER_FRAGMENT
:
201 ish
->nos
|= IRIS_NOS_FRAMEBUFFER
|
202 IRIS_NOS_DEPTH_STENCIL_ALPHA
|
203 IRIS_NOS_RASTERIZER
|
206 /* The program key needs the VUE map if there are > 16 inputs */
207 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
208 BRW_FS_VARYING_INPUT_MASK
) > 16) {
209 ish
->nos
|= IRIS_NOS_LAST_VUE_MAP
;
212 case MESA_SHADER_COMPUTE
:
220 // XXX: disallow more than 64KB of shared variables
226 * The pipe->delete_[stage]_state() driver hooks.
228 * Frees the iris_uncompiled_shader.
231 iris_create_shader_state(struct pipe_context
*ctx
,
232 const struct pipe_shader_state
*state
)
234 assert(state
->type
== PIPE_SHADER_IR_NIR
);
236 return iris_create_uncompiled_shader(ctx
, state
->ir
.nir
,
237 &state
->stream_output
);
241 iris_create_compute_state(struct pipe_context
*ctx
,
242 const struct pipe_compute_state
*state
)
244 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
246 return iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
250 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
)
252 struct iris_uncompiled_shader
*ish
= state
;
254 ralloc_free(ish
->nir
);
259 * The pipe->bind_[stage]_state() driver hook.
261 * Binds an uncompiled shader as the current one for a particular stage.
262 * Updates dirty tracking to account for the shader's NOS.
265 bind_state(struct iris_context
*ice
,
266 struct iris_uncompiled_shader
*ish
,
267 gl_shader_stage stage
)
269 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
270 const uint64_t nos
= ish
? ish
->nos
: 0;
272 ice
->shaders
.uncompiled
[stage
] = ish
;
273 ice
->state
.dirty
|= dirty_bit
;
275 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
276 * (or that they no longer need to do so).
278 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
280 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
282 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
287 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
289 bind_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
293 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
295 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
299 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
301 struct iris_context
*ice
= (struct iris_context
*)ctx
;
303 /* Enabling/disabling optional stages requires a URB reconfiguration. */
304 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
305 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
307 bind_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
311 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
313 struct iris_context
*ice
= (struct iris_context
*)ctx
;
315 /* Enabling/disabling optional stages requires a URB reconfiguration. */
316 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
317 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
319 bind_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
323 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
325 bind_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
329 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
331 bind_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
335 * Sets up the starting offsets for the groups of binding table entries
336 * common to all pipeline stages.
338 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
339 * unused but also make sure that addition of small offsets to them will
340 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
343 assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
344 const struct nir_shader
*nir
,
345 struct brw_stage_prog_data
*prog_data
,
346 uint32_t next_binding_table_offset
)
348 const struct shader_info
*info
= &nir
->info
;
350 if (info
->num_textures
) {
351 prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
352 prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
353 next_binding_table_offset
+= info
->num_textures
;
355 prog_data
->binding_table
.texture_start
= 0xd0d0d0d0;
356 prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
359 if (info
->num_images
) {
360 prog_data
->binding_table
.image_start
= next_binding_table_offset
;
361 next_binding_table_offset
+= info
->num_images
;
363 prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
366 int num_ubos
= info
->num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
369 //assert(info->num_ubos <= BRW_MAX_UBO);
370 prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
371 next_binding_table_offset
+= num_ubos
;
373 prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
376 if (info
->num_ssbos
|| info
->num_abos
) {
377 prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
378 // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
379 next_binding_table_offset
+= IRIS_MAX_ABOS
+ info
->num_ssbos
;
381 prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
384 prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
386 /* This may or may not be used depending on how the compile goes. */
387 prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
388 next_binding_table_offset
++;
390 /* Plane 0 is just the regular texture section */
391 prog_data
->binding_table
.plane_start
[0] = prog_data
->binding_table
.texture_start
;
393 prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
394 next_binding_table_offset
+= info
->num_textures
;
396 prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
397 next_binding_table_offset
+= info
->num_textures
;
399 /* Set the binding table size */
400 prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
402 return next_binding_table_offset
;
406 * Associate NIR uniform variables with the prog_data->param[] mechanism
407 * used by the backend. Also, decide which UBOs we'd like to push in an
408 * ideal situation (though the backend can reduce this).
411 iris_setup_uniforms(const struct brw_compiler
*compiler
,
414 struct brw_stage_prog_data
*prog_data
)
416 /* The intel compiler assumes that num_uniforms is in bytes. For
417 * scalar that means 4 bytes per uniform slot.
419 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
421 nir
->num_uniforms
*= 4;
423 prog_data
->nr_params
= 0;
424 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 1);
426 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
429 nir_builder_init(&b
, impl
);
431 b
.cursor
= nir_before_block(nir_start_block(impl
));
432 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
434 /* Turn system value intrinsics into uniforms */
435 nir_foreach_block(block
, impl
) {
436 nir_foreach_instr_safe(instr
, block
) {
437 if (instr
->type
!= nir_instr_type_intrinsic
)
440 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
442 unsigned param_idx
= prog_data
->nr_params
;
443 uint32_t *param
= NULL
;
445 switch (intrin
->intrinsic
) {
446 case nir_intrinsic_load_user_clip_plane
: {
447 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
448 param
= brw_stage_prog_data_add_params(prog_data
, 4);
449 for (int i
= 0; i
< 4; i
++) {
451 IRIS_PARAM(BUILTIN
, BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
));
459 b
.cursor
= nir_before_instr(instr
);
461 unsigned comps
= nir_intrinsic_dest_components(intrin
);
462 nir_ssa_def
*offset
= nir_imm_int(&b
, param_idx
* sizeof(uint32_t));
464 nir_intrinsic_instr
*load
=
465 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
466 load
->num_components
= comps
;
467 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
468 load
->src
[1] = nir_src_for_ssa(offset
);
469 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
470 nir_builder_instr_insert(&b
, &load
->instr
);
471 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
472 nir_src_for_ssa(&load
->dest
.ssa
));
473 nir_instr_remove(instr
);
477 nir_validate_shader(nir
, "before remapping");
479 /* Place the new params at the front of constant buffer 0. */
480 if (prog_data
->nr_params
> 0) {
481 nir_foreach_block(block
, impl
) {
482 nir_foreach_instr_safe(instr
, block
) {
483 if (instr
->type
!= nir_instr_type_intrinsic
)
486 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
488 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
491 b
.cursor
= nir_before_instr(instr
);
493 assert(load
->src
[0].is_ssa
);
495 if (load
->src
[0].ssa
== temp_ubo_name
) {
496 nir_instr_rewrite_src(instr
, &load
->src
[0],
497 nir_src_for_ssa(nir_imm_int(&b
, 0)));
498 } else if (nir_src_as_uint(load
->src
[0]) == 0) {
499 nir_ssa_def
*offset
=
500 nir_iadd(&b
, load
->src
[1].ssa
,
501 nir_imm_int(&b
, prog_data
->nr_params
));
502 nir_instr_rewrite_src(instr
, &load
->src
[1],
503 nir_src_for_ssa(offset
));
509 nir_validate_shader(nir
, "after remap");
511 // XXX: vs clip planes?
512 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
513 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
517 * If we still have regular uniforms as push constants after the backend
518 * compilation, set up a UBO range for them. This will be used to fill
519 * out the 3DSTATE_CONSTANT_* packets which cause the data to be pushed.
522 iris_setup_push_uniform_range(const struct brw_compiler
*compiler
,
523 struct brw_stage_prog_data
*prog_data
)
525 if (prog_data
->nr_params
) {
526 for (int i
= 3; i
> 0; i
--)
527 prog_data
->ubo_ranges
[i
] = prog_data
->ubo_ranges
[i
- 1];
529 prog_data
->ubo_ranges
[0] = (struct brw_ubo_range
) {
532 .length
= DIV_ROUND_UP(prog_data
->nr_params
, 8),
538 * Compile a vertex shader, and upload the assembly.
541 iris_compile_vs(struct iris_context
*ice
,
542 struct iris_uncompiled_shader
*ish
,
543 const struct brw_vs_prog_key
*key
)
545 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
546 const struct brw_compiler
*compiler
= screen
->compiler
;
547 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
548 void *mem_ctx
= ralloc_context(NULL
);
549 struct brw_vs_prog_data
*vs_prog_data
=
550 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
551 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
552 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
554 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
556 if (key
->nr_userclip_plane_consts
) {
557 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
558 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true);
559 nir_lower_io_to_temporaries(nir
, impl
, true, false);
560 nir_lower_global_vars_to_local(nir
);
561 nir_lower_vars_to_ssa(nir
);
565 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
567 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
569 brw_compute_vue_map(devinfo
,
570 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
571 nir
->info
.separate_shader
);
573 char *error_str
= NULL
;
574 const unsigned *program
=
575 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, key
, vs_prog_data
,
576 nir
, -1, &error_str
);
577 if (program
== NULL
) {
578 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
579 ralloc_free(mem_ctx
);
583 iris_setup_push_uniform_range(compiler
, prog_data
);
586 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
587 &vue_prog_data
->vue_map
);
589 iris_upload_and_bind_shader(ice
, IRIS_CACHE_VS
, key
, program
, prog_data
,
592 ralloc_free(mem_ctx
);
597 * Update the current vertex shader variant.
599 * Fill out the key, look in the cache, compile and bind if needed.
602 iris_update_compiled_vs(struct iris_context
*ice
)
604 struct iris_uncompiled_shader
*ish
=
605 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
607 struct brw_vs_prog_key key
= { .program_string_id
= ish
->program_id
};
608 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, &key
);
610 if (iris_bind_cached_shader(ice
, IRIS_CACHE_VS
, &key
))
613 UNUSED
bool success
= iris_compile_vs(ice
, ish
, &key
);
617 * Get the shader_info for a given stage, or NULL if the stage is disabled.
619 const struct shader_info
*
620 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
622 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
627 const nir_shader
*nir
= ish
->nir
;
631 // XXX: this function is gross
633 iris_get_shader_num_ubos(const struct iris_context
*ice
, gl_shader_stage stage
)
635 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
638 const nir_shader
*nir
= ish
->nir
;
639 /* see assign_common_binding_table_offsets */
640 return nir
->info
.num_ubos
+ (nir
->num_uniforms
> 0 ? 1 : 0);
646 * Get the union of TCS output and TES input slots.
648 * TCS and TES need to agree on a common URB entry layout. In particular,
649 * the data for all patch vertices is stored in a single URB entry (unlike
650 * GS which has one entry per input vertex). This means that per-vertex
651 * array indexing needs a stride.
653 * SSO requires locations to match, but doesn't require the number of
654 * outputs/inputs to match (in fact, the TCS often has extra outputs).
655 * So, we need to take the extra step of unifying these on the fly.
658 get_unified_tess_slots(const struct iris_context
*ice
,
659 uint64_t *per_vertex_slots
,
660 uint32_t *per_patch_slots
)
662 const struct shader_info
*tcs
=
663 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
664 const struct shader_info
*tes
=
665 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
667 *per_vertex_slots
= tes
->inputs_read
;
668 *per_patch_slots
= tes
->patch_inputs_read
;
671 *per_vertex_slots
|= tcs
->inputs_read
;
672 *per_patch_slots
|= tcs
->patch_inputs_read
;
677 * Compile a tessellation control shader, and upload the assembly.
680 iris_compile_tcs(struct iris_context
*ice
,
681 struct iris_uncompiled_shader
*ish
,
682 const struct brw_tcs_prog_key
*key
)
684 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
685 const struct brw_compiler
*compiler
= screen
->compiler
;
686 const struct nir_shader_compiler_options
*options
=
687 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
688 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
689 void *mem_ctx
= ralloc_context(NULL
);
690 struct brw_tcs_prog_data
*tcs_prog_data
=
691 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
692 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
693 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
698 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
700 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
701 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
703 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
705 /* Reserve space for passing the default tess levels as constants. */
706 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, 8);
707 prog_data
->nr_params
= 8;
708 prog_data
->ubo_ranges
[0].length
= 1;
711 char *error_str
= NULL
;
712 const unsigned *program
=
713 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
715 if (program
== NULL
) {
716 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
717 ralloc_free(mem_ctx
);
721 iris_setup_push_uniform_range(compiler
, prog_data
);
723 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TCS
, key
, program
, prog_data
,
726 ralloc_free(mem_ctx
);
731 * Update the current tessellation control shader variant.
733 * Fill out the key, look in the cache, compile and bind if needed.
736 iris_update_compiled_tcs(struct iris_context
*ice
)
738 struct iris_uncompiled_shader
*tcs
=
739 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
741 const struct shader_info
*tes_info
=
742 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
743 struct brw_tcs_prog_key key
= {
744 .program_string_id
= tcs
? tcs
->program_id
: 0,
745 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
746 .input_vertices
= ice
->state
.vertices_per_patch
,
748 get_unified_tess_slots(ice
, &key
.outputs_written
,
749 &key
.patch_outputs_written
);
750 ice
->vtbl
.populate_tcs_key(ice
, &key
);
752 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TCS
, &key
))
755 UNUSED
bool success
= iris_compile_tcs(ice
, tcs
, &key
);
759 * Compile a tessellation evaluation shader, and upload the assembly.
762 iris_compile_tes(struct iris_context
*ice
,
763 struct iris_uncompiled_shader
*ish
,
764 const struct brw_tes_prog_key
*key
)
766 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
767 const struct brw_compiler
*compiler
= screen
->compiler
;
768 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
769 void *mem_ctx
= ralloc_context(NULL
);
770 struct brw_tes_prog_data
*tes_prog_data
=
771 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
772 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
773 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
775 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
777 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
779 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
781 struct brw_vue_map input_vue_map
;
782 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
783 key
->patch_inputs_read
);
785 char *error_str
= NULL
;
786 const unsigned *program
=
787 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
788 tes_prog_data
, nir
, NULL
, -1, &error_str
);
789 if (program
== NULL
) {
790 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
791 ralloc_free(mem_ctx
);
795 iris_setup_push_uniform_range(compiler
, prog_data
);
798 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
799 &vue_prog_data
->vue_map
);
801 iris_upload_and_bind_shader(ice
, IRIS_CACHE_TES
, key
, program
, prog_data
,
804 ralloc_free(mem_ctx
);
809 * Update the current tessellation evaluation shader variant.
811 * Fill out the key, look in the cache, compile and bind if needed.
814 iris_update_compiled_tes(struct iris_context
*ice
)
816 struct iris_uncompiled_shader
*ish
=
817 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
819 struct brw_tes_prog_key key
= { .program_string_id
= ish
->program_id
};
820 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
821 ice
->vtbl
.populate_tes_key(ice
, &key
);
823 if (iris_bind_cached_shader(ice
, IRIS_CACHE_TES
, &key
))
826 UNUSED
bool success
= iris_compile_tes(ice
, ish
, &key
);
830 * Compile a geometry shader, and upload the assembly.
833 iris_compile_gs(struct iris_context
*ice
,
834 struct iris_uncompiled_shader
*ish
,
835 const struct brw_gs_prog_key
*key
)
837 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
838 const struct brw_compiler
*compiler
= screen
->compiler
;
839 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
840 void *mem_ctx
= ralloc_context(NULL
);
841 struct brw_gs_prog_data
*gs_prog_data
=
842 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
843 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
844 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
846 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
848 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 0);
850 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
852 brw_compute_vue_map(devinfo
,
853 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
854 nir
->info
.separate_shader
);
856 char *error_str
= NULL
;
857 const unsigned *program
=
858 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
859 NULL
, -1, &error_str
);
860 if (program
== NULL
) {
861 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
862 ralloc_free(mem_ctx
);
866 iris_setup_push_uniform_range(compiler
, prog_data
);
869 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
870 &vue_prog_data
->vue_map
);
872 iris_upload_and_bind_shader(ice
, IRIS_CACHE_GS
, key
, program
, prog_data
,
875 ralloc_free(mem_ctx
);
880 * Update the current geometry shader variant.
882 * Fill out the key, look in the cache, compile and bind if needed.
885 iris_update_compiled_gs(struct iris_context
*ice
)
887 struct iris_uncompiled_shader
*ish
=
888 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
891 iris_unbind_shader(ice
, IRIS_CACHE_GS
);
895 struct brw_gs_prog_key key
= { .program_string_id
= ish
->program_id
};
896 ice
->vtbl
.populate_gs_key(ice
, &key
);
898 if (iris_bind_cached_shader(ice
, IRIS_CACHE_GS
, &key
))
901 UNUSED
bool success
= iris_compile_gs(ice
, ish
, &key
);
905 * Compile a fragment (pixel) shader, and upload the assembly.
908 iris_compile_fs(struct iris_context
*ice
,
909 struct iris_uncompiled_shader
*ish
,
910 const struct brw_wm_prog_key
*key
,
911 struct brw_vue_map
*vue_map
)
913 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
914 const struct brw_compiler
*compiler
= screen
->compiler
;
915 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
916 void *mem_ctx
= ralloc_context(NULL
);
917 struct brw_wm_prog_data
*fs_prog_data
=
918 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
919 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
921 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
924 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
,
925 MAX2(key
->nr_color_regions
, 1));
927 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
929 char *error_str
= NULL
;
930 const unsigned *program
=
931 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
932 nir
, NULL
, -1, -1, -1, true, false, vue_map
, &error_str
);
933 if (program
== NULL
) {
934 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
935 ralloc_free(mem_ctx
);
939 //brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
941 iris_setup_push_uniform_range(compiler
, prog_data
);
943 iris_upload_and_bind_shader(ice
, IRIS_CACHE_FS
, key
, program
, prog_data
,
946 ralloc_free(mem_ctx
);
951 * Update the current fragment shader variant.
953 * Fill out the key, look in the cache, compile and bind if needed.
956 iris_update_compiled_fs(struct iris_context
*ice
)
958 struct iris_uncompiled_shader
*ish
=
959 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
960 struct brw_wm_prog_key key
= { .program_string_id
= ish
->program_id
};
961 ice
->vtbl
.populate_fs_key(ice
, &key
);
963 if (ish
->nos
& IRIS_NOS_LAST_VUE_MAP
)
964 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
966 if (iris_bind_cached_shader(ice
, IRIS_CACHE_FS
, &key
))
969 UNUSED
bool success
=
970 iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
974 * Get the compiled shader for the last enabled geometry stage.
976 * This stage is the one which will feed stream output and the rasterizer.
978 static struct iris_compiled_shader
*
979 last_vue_shader(struct iris_context
*ice
)
981 if (ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
982 return ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
984 if (ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
])
985 return ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
987 return ice
->shaders
.prog
[MESA_SHADER_VERTEX
];
991 * Update the last enabled stage's VUE map.
993 * When the shader feeding the rasterizer's output interface changes, we
994 * need to re-emit various packets.
997 update_last_vue_map(struct iris_context
*ice
,
998 struct brw_stage_prog_data
*prog_data
)
1000 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1001 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1002 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1003 const uint64_t changed_slots
=
1004 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1006 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1007 // XXX: could use ctx->Const.MaxViewports for old API efficiency
1008 ice
->state
.num_viewports
=
1009 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1010 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1011 IRIS_DIRTY_SF_CL_VIEWPORT
|
1012 IRIS_DIRTY_CC_VIEWPORT
|
1013 IRIS_DIRTY_SCISSOR_RECT
|
1014 IRIS_DIRTY_UNCOMPILED_FS
|
1015 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1016 // XXX: CC_VIEWPORT?
1019 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1020 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1023 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1027 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1029 static struct brw_vue_prog_data
*
1030 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1032 if (!ice
->shaders
.prog
[stage
])
1035 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1039 * Update the current shader variants for the given state.
1041 * This should be called on every draw call to ensure that the correct
1042 * shaders are bound. It will also flag any dirty state triggered by
1043 * swapping out those shaders.
1046 iris_update_compiled_shaders(struct iris_context
*ice
)
1048 const uint64_t dirty
= ice
->state
.dirty
;
1050 struct brw_vue_prog_data
*old_prog_datas
[4];
1051 if (!(dirty
& IRIS_DIRTY_URB
)) {
1052 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1053 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1056 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1057 struct iris_uncompiled_shader
*tes
=
1058 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1060 iris_update_compiled_tcs(ice
);
1061 iris_update_compiled_tes(ice
);
1063 iris_unbind_shader(ice
, IRIS_CACHE_TCS
);
1064 iris_unbind_shader(ice
, IRIS_CACHE_TES
);
1068 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1069 iris_update_compiled_vs(ice
);
1070 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1071 iris_update_compiled_gs(ice
);
1073 struct iris_compiled_shader
*shader
= last_vue_shader(ice
);
1074 update_last_vue_map(ice
, shader
->prog_data
);
1075 if (ice
->state
.streamout
!= shader
->streamout
) {
1076 ice
->state
.streamout
= shader
->streamout
;
1077 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1080 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1081 iris_update_compiled_fs(ice
);
1084 /* Changing shader interfaces may require a URB configuration. */
1085 if (!(dirty
& IRIS_DIRTY_URB
)) {
1086 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1087 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1088 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1089 if (!!old
!= !!new ||
1090 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1091 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1099 iris_compile_cs(struct iris_context
*ice
,
1100 struct iris_uncompiled_shader
*ish
,
1101 const struct brw_cs_prog_key
*key
)
1103 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1104 const struct brw_compiler
*compiler
= screen
->compiler
;
1105 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1106 void *mem_ctx
= ralloc_context(NULL
);
1107 struct brw_cs_prog_data
*cs_prog_data
=
1108 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1109 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1111 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1113 cs_prog_data
->binding_table
.work_groups_start
= 0;
1114 assign_common_binding_table_offsets(devinfo
, nir
, prog_data
, 1);
1116 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
);
1118 char *error_str
= NULL
;
1119 const unsigned *program
=
1120 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1121 nir
, -1, &error_str
);
1122 if (program
== NULL
) {
1123 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1124 ralloc_free(mem_ctx
);
1128 iris_upload_and_bind_shader(ice
, IRIS_CACHE_CS
, key
, program
, prog_data
,
1131 ralloc_free(mem_ctx
);
1136 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1138 struct iris_uncompiled_shader
*ish
=
1139 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1141 struct brw_cs_prog_key key
= { .program_string_id
= ish
->program_id
};
1142 ice
->vtbl
.populate_cs_key(ice
, &key
);
1144 if (iris_bind_cached_shader(ice
, IRIS_CACHE_CS
, &key
))
1147 UNUSED
bool success
= iris_compile_cs(ice
, ish
, &key
);
1151 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1154 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1155 assert(cs_prog_data
->push
.total
.size
> 0);
1156 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1157 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1158 assert(prog_data
->param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1159 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1164 * Allocate scratch BOs as needed for the given per-thread size and stage.
1166 * Returns the 32-bit "Scratch Space Base Pointer" value.
1169 iris_get_scratch_space(struct iris_context
*ice
,
1170 unsigned per_thread_scratch
,
1171 gl_shader_stage stage
)
1173 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1174 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1175 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1177 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1178 assert(encoded_size
< (1 << 16));
1180 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1182 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1184 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1185 * allocate scratch space enough so that each slice has 4 slices
1188 * According to the other driver team, this applies to compute shaders
1189 * as well. This is not currently documented at all.
1191 unsigned subslice_total
= 4 * devinfo
->num_slices
;
1192 assert(subslice_total
>= screen
->subslice_total
);
1195 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1196 uint32_t max_threads
[] = {
1197 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1198 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1199 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1200 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1201 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1202 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1205 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1207 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1210 return (*bop
)->gtt_offset
;
1214 iris_init_program_functions(struct pipe_context
*ctx
)
1216 ctx
->create_vs_state
= iris_create_shader_state
;
1217 ctx
->create_tcs_state
= iris_create_shader_state
;
1218 ctx
->create_tes_state
= iris_create_shader_state
;
1219 ctx
->create_gs_state
= iris_create_shader_state
;
1220 ctx
->create_fs_state
= iris_create_shader_state
;
1221 ctx
->create_compute_state
= iris_create_compute_state
;
1223 ctx
->delete_vs_state
= iris_delete_shader_state
;
1224 ctx
->delete_tcs_state
= iris_delete_shader_state
;
1225 ctx
->delete_tes_state
= iris_delete_shader_state
;
1226 ctx
->delete_gs_state
= iris_delete_shader_state
;
1227 ctx
->delete_fs_state
= iris_delete_shader_state
;
1228 ctx
->delete_compute_state
= iris_delete_shader_state
;
1230 ctx
->bind_vs_state
= iris_bind_vs_state
;
1231 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
1232 ctx
->bind_tes_state
= iris_bind_tes_state
;
1233 ctx
->bind_gs_state
= iris_bind_gs_state
;
1234 ctx
->bind_fs_state
= iris_bind_fs_state
;
1235 ctx
->bind_compute_state
= iris_bind_cs_state
;