2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/debug.h"
41 #include "compiler/nir/nir.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "compiler/nir/nir_serialize.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/compiler/brw_nir.h"
46 #include "iris_context.h"
47 #include "nir/tgsi_to_nir.h"
49 #define KEY_INIT_NO_ID(gen) \
50 .base.subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM, \
51 .base.tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
52 .base.tex.compressed_multisample_layout_mask = ~0, \
53 .base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
54 #define KEY_INIT(gen) .base.program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
57 get_new_program_id(struct iris_screen
*screen
)
59 return p_atomic_inc_return(&screen
->program_id
);
63 upload_state(struct u_upload_mgr
*uploader
,
64 struct iris_state_ref
*ref
,
69 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
74 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
75 struct pipe_shader_buffer
*buf
,
76 struct iris_state_ref
*surf_state
,
79 struct pipe_context
*ctx
= &ice
->ctx
;
80 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
83 upload_state(ice
->state
.surface_uploader
, surf_state
,
84 screen
->isl_dev
.ss
.size
, 64);
86 surf_state
->res
= NULL
;
90 struct iris_resource
*res
= (void *) buf
->buffer
;
91 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
92 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
94 isl_buffer_fill_state(&screen
->isl_dev
, map
,
95 .address
= res
->bo
->gtt_offset
+ res
->offset
+
97 .size_B
= buf
->buffer_size
- res
->offset
,
98 .format
= ssbo
? ISL_FORMAT_RAW
99 : ISL_FORMAT_R32G32B32A32_FLOAT
,
100 .swizzle
= ISL_SWIZZLE_IDENTITY
,
102 .mocs
= ice
->vtbl
.mocs(res
->bo
));
106 get_aoa_deref_offset(nir_builder
*b
,
107 nir_deref_instr
*deref
,
110 unsigned array_size
= elem_size
;
111 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
113 while (deref
->deref_type
!= nir_deref_type_var
) {
114 assert(deref
->deref_type
== nir_deref_type_array
);
116 /* This level's element size is the previous level's array size */
117 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
118 assert(deref
->arr
.index
.ssa
);
119 offset
= nir_iadd(b
, offset
,
120 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
122 deref
= nir_deref_instr_parent(deref
);
123 assert(glsl_type_is_array(deref
->type
));
124 array_size
*= glsl_get_length(deref
->type
);
127 /* Accessing an invalid surface index with the dataport can result in a
128 * hang. According to the spec "if the index used to select an individual
129 * element is negative or greater than or equal to the size of the array,
130 * the results of the operation are undefined but may not lead to
131 * termination" -- which is one of the possible outcomes of the hang.
132 * Clamp the index to prevent access outside of the array bounds.
134 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
138 iris_lower_storage_image_derefs(nir_shader
*nir
)
140 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
143 nir_builder_init(&b
, impl
);
145 nir_foreach_block(block
, impl
) {
146 nir_foreach_instr_safe(instr
, block
) {
147 if (instr
->type
!= nir_instr_type_intrinsic
)
150 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
151 switch (intrin
->intrinsic
) {
152 case nir_intrinsic_image_deref_load
:
153 case nir_intrinsic_image_deref_store
:
154 case nir_intrinsic_image_deref_atomic_add
:
155 case nir_intrinsic_image_deref_atomic_imin
:
156 case nir_intrinsic_image_deref_atomic_umin
:
157 case nir_intrinsic_image_deref_atomic_imax
:
158 case nir_intrinsic_image_deref_atomic_umax
:
159 case nir_intrinsic_image_deref_atomic_and
:
160 case nir_intrinsic_image_deref_atomic_or
:
161 case nir_intrinsic_image_deref_atomic_xor
:
162 case nir_intrinsic_image_deref_atomic_exchange
:
163 case nir_intrinsic_image_deref_atomic_comp_swap
:
164 case nir_intrinsic_image_deref_size
:
165 case nir_intrinsic_image_deref_samples
:
166 case nir_intrinsic_image_deref_load_raw_intel
:
167 case nir_intrinsic_image_deref_store_raw_intel
: {
168 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
169 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
171 b
.cursor
= nir_before_instr(&intrin
->instr
);
173 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
174 get_aoa_deref_offset(&b
, deref
, 1));
175 nir_rewrite_image_intrinsic(intrin
, index
, false);
186 // XXX: need unify_interfaces() at link time...
189 * Fix an uncompiled shader's stream output info.
191 * Core Gallium stores output->register_index as a "slot" number, where
192 * slots are assigned consecutively to all outputs in info->outputs_written.
193 * This naive packing of outputs doesn't work for us - we too have slots,
194 * but the layout is defined by the VUE map, which we won't have until we
195 * compile a specific shader variant. So, we remap these and simply store
196 * VARYING_SLOT_* in our copy's output->register_index fields.
198 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
199 * components of our VUE header. See brw_vue_map.c for the layout.
202 update_so_info(struct pipe_stream_output_info
*so_info
,
203 uint64_t outputs_written
)
205 uint8_t reverse_map
[64] = {};
207 while (outputs_written
) {
208 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
211 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
212 struct pipe_stream_output
*output
= &so_info
->output
[i
];
214 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
215 output
->register_index
= reverse_map
[output
->register_index
];
217 /* The VUE header contains three scalar fields packed together:
218 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
219 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
220 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
222 switch (output
->register_index
) {
223 case VARYING_SLOT_LAYER
:
224 assert(output
->num_components
== 1);
225 output
->register_index
= VARYING_SLOT_PSIZ
;
226 output
->start_component
= 1;
228 case VARYING_SLOT_VIEWPORT
:
229 assert(output
->num_components
== 1);
230 output
->register_index
= VARYING_SLOT_PSIZ
;
231 output
->start_component
= 2;
233 case VARYING_SLOT_PSIZ
:
234 assert(output
->num_components
== 1);
235 output
->start_component
= 3;
239 //info->outputs_written |= 1ull << output->register_index;
244 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
245 unsigned offset
, unsigned n
)
247 assert(offset
% sizeof(uint32_t) == 0);
249 for (unsigned i
= 0; i
< n
; ++i
)
250 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
252 for (unsigned i
= n
; i
< 4; ++i
)
253 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
257 * Associate NIR uniform variables with the prog_data->param[] mechanism
258 * used by the backend. Also, decide which UBOs we'd like to push in an
259 * ideal situation (though the backend can reduce this).
262 iris_setup_uniforms(const struct brw_compiler
*compiler
,
265 struct brw_stage_prog_data
*prog_data
,
266 enum brw_param_builtin
**out_system_values
,
267 unsigned *out_num_system_values
,
268 unsigned *out_num_cbufs
)
270 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
272 /* The intel compiler assumes that num_uniforms is in bytes. For
273 * scalar that means 4 bytes per uniform slot.
275 * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
277 nir
->num_uniforms
*= 4;
279 const unsigned IRIS_MAX_SYSTEM_VALUES
=
280 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
281 enum brw_param_builtin
*system_values
=
282 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
283 unsigned num_system_values
= 0;
285 unsigned patch_vert_idx
= -1;
286 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
287 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
288 memset(ucp_idx
, -1, sizeof(ucp_idx
));
289 memset(img_idx
, -1, sizeof(img_idx
));
291 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
294 nir_builder_init(&b
, impl
);
296 b
.cursor
= nir_before_block(nir_start_block(impl
));
297 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
298 nir_ssa_def
*temp_const_ubo_name
= NULL
;
300 /* Turn system value intrinsics into uniforms */
301 nir_foreach_block(block
, impl
) {
302 nir_foreach_instr_safe(instr
, block
) {
303 if (instr
->type
!= nir_instr_type_intrinsic
)
306 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
309 switch (intrin
->intrinsic
) {
310 case nir_intrinsic_load_constant
: {
311 /* This one is special because it reads from the shader constant
312 * data and not cbuf0 which gallium uploads for us.
314 b
.cursor
= nir_before_instr(instr
);
315 nir_ssa_def
*offset
=
316 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
317 nir_intrinsic_base(intrin
));
319 if (temp_const_ubo_name
== NULL
)
320 temp_const_ubo_name
= nir_imm_int(&b
, 0);
322 nir_intrinsic_instr
*load_ubo
=
323 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
324 load_ubo
->num_components
= intrin
->num_components
;
325 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
326 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
327 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
328 intrin
->dest
.ssa
.num_components
,
329 intrin
->dest
.ssa
.bit_size
,
330 intrin
->dest
.ssa
.name
);
331 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
333 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
334 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
335 nir_instr_remove(&intrin
->instr
);
338 case nir_intrinsic_load_user_clip_plane
: {
339 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
341 if (ucp_idx
[ucp
] == -1) {
342 ucp_idx
[ucp
] = num_system_values
;
343 num_system_values
+= 4;
346 for (int i
= 0; i
< 4; i
++) {
347 system_values
[ucp_idx
[ucp
] + i
] =
348 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
351 b
.cursor
= nir_before_instr(instr
);
352 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
355 case nir_intrinsic_load_patch_vertices_in
:
356 if (patch_vert_idx
== -1)
357 patch_vert_idx
= num_system_values
++;
359 system_values
[patch_vert_idx
] =
360 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
362 b
.cursor
= nir_before_instr(instr
);
363 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
365 case nir_intrinsic_image_deref_load_param_intel
: {
366 assert(devinfo
->gen
< 9);
367 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
368 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
370 if (img_idx
[var
->data
.binding
] == -1) {
371 /* GL only allows arrays of arrays of images. */
372 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
373 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
375 for (int i
= 0; i
< num_images
; i
++) {
376 const unsigned img
= var
->data
.binding
+ i
;
378 img_idx
[img
] = num_system_values
;
379 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
381 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
383 setup_vec4_image_sysval(
384 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
385 offsetof(struct brw_image_param
, offset
), 2);
386 setup_vec4_image_sysval(
387 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
388 offsetof(struct brw_image_param
, size
), 3);
389 setup_vec4_image_sysval(
390 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
391 offsetof(struct brw_image_param
, stride
), 4);
392 setup_vec4_image_sysval(
393 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
394 offsetof(struct brw_image_param
, tiling
), 3);
395 setup_vec4_image_sysval(
396 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
397 offsetof(struct brw_image_param
, swizzling
), 2);
401 b
.cursor
= nir_before_instr(instr
);
402 offset
= nir_iadd(&b
,
403 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
404 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
405 nir_intrinsic_base(intrin
) * 16));
412 unsigned comps
= nir_intrinsic_dest_components(intrin
);
414 nir_intrinsic_instr
*load
=
415 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
416 load
->num_components
= comps
;
417 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
418 load
->src
[1] = nir_src_for_ssa(offset
);
419 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
420 nir_builder_instr_insert(&b
, &load
->instr
);
421 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
422 nir_src_for_ssa(&load
->dest
.ssa
));
423 nir_instr_remove(instr
);
427 nir_validate_shader(nir
, "before remapping");
429 /* Uniforms are stored in constant buffer 0, the
430 * user-facing UBOs are indexed by one. So if any constant buffer is
431 * needed, the constant buffer 0 will be needed, so account for it.
433 unsigned num_cbufs
= nir
->info
.num_ubos
;
434 if (num_cbufs
|| nir
->num_uniforms
)
437 /* Place the new params in a new cbuf. */
438 if (num_system_values
> 0) {
439 unsigned sysval_cbuf_index
= num_cbufs
;
442 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
445 nir_foreach_block(block
, impl
) {
446 nir_foreach_instr_safe(instr
, block
) {
447 if (instr
->type
!= nir_instr_type_intrinsic
)
450 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
452 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
455 b
.cursor
= nir_before_instr(instr
);
457 assert(load
->src
[0].is_ssa
);
459 if (load
->src
[0].ssa
== temp_ubo_name
) {
460 nir_ssa_def
*imm
= nir_imm_int(&b
, sysval_cbuf_index
);
461 nir_instr_rewrite_src(instr
, &load
->src
[0],
462 nir_src_for_ssa(imm
));
467 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
468 nir_opt_constant_folding(nir
);
470 ralloc_free(system_values
);
471 system_values
= NULL
;
474 assert(num_cbufs
< PIPE_MAX_CONSTANT_BUFFERS
);
475 nir_validate_shader(nir
, "after remap");
477 /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
478 * about it for compute shaders, so go ahead and make some fake ones
479 * which the backend will dead code eliminate.
481 prog_data
->nr_params
= nir
->num_uniforms
/ 4;
482 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
484 /* Constant loads (if any) need to go at the end of the constant buffers so
485 * we need to know num_cbufs before we can lower to them.
487 if (temp_const_ubo_name
!= NULL
) {
488 nir_load_const_instr
*const_ubo_index
=
489 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
490 assert(const_ubo_index
->def
.bit_size
== 32);
491 const_ubo_index
->value
[0].u32
= num_cbufs
;
494 *out_system_values
= system_values
;
495 *out_num_system_values
= num_system_values
;
496 *out_num_cbufs
= num_cbufs
;
499 static const char *surface_group_names
[] = {
500 [IRIS_SURFACE_GROUP_RENDER_TARGET
] = "render target",
501 [IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = "non-coherent render target read",
502 [IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = "CS work groups",
503 [IRIS_SURFACE_GROUP_TEXTURE
] = "texture",
504 [IRIS_SURFACE_GROUP_UBO
] = "ubo",
505 [IRIS_SURFACE_GROUP_SSBO
] = "ssbo",
506 [IRIS_SURFACE_GROUP_IMAGE
] = "image",
510 iris_print_binding_table(FILE *fp
, const char *name
,
511 const struct iris_binding_table
*bt
)
513 STATIC_ASSERT(ARRAY_SIZE(surface_group_names
) == IRIS_SURFACE_GROUP_COUNT
);
516 uint32_t compacted
= 0;
518 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
519 uint32_t size
= bt
->sizes
[i
];
522 compacted
+= util_bitcount64(bt
->used_mask
[i
]);
526 fprintf(fp
, "Binding table for %s is empty\n\n", name
);
530 if (total
!= compacted
) {
531 fprintf(fp
, "Binding table for %s "
532 "(compacted to %u entries from %u entries)\n",
533 name
, compacted
, total
);
535 fprintf(fp
, "Binding table for %s (%u entries)\n", name
, total
);
539 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
540 uint64_t mask
= bt
->used_mask
[i
];
542 int index
= u_bit_scan64(&mask
);
543 fprintf(fp
, " [%u] %s #%d\n", entry
++, surface_group_names
[i
], index
);
550 /* Max elements in a surface group. */
551 SURFACE_GROUP_MAX_ELEMENTS
= 64,
555 * Map a <group, index> pair to a binding table index.
557 * For example: <UBO, 5> => binding table index 12
560 iris_group_index_to_bti(const struct iris_binding_table
*bt
,
561 enum iris_surface_group group
, uint32_t index
)
563 assert(index
< bt
->sizes
[group
]);
564 uint64_t mask
= bt
->used_mask
[group
];
565 uint64_t bit
= 1ull << index
;
567 return bt
->offsets
[group
] + util_bitcount64((bit
- 1) & mask
);
569 return IRIS_SURFACE_NOT_USED
;
574 * Map a binding table index back to a <group, index> pair.
576 * For example: binding table index 12 => <UBO, 5>
579 iris_bti_to_group_index(const struct iris_binding_table
*bt
,
580 enum iris_surface_group group
, uint32_t bti
)
582 uint64_t used_mask
= bt
->used_mask
[group
];
583 assert(bti
>= bt
->offsets
[group
]);
585 uint32_t c
= bti
- bt
->offsets
[group
];
587 int i
= u_bit_scan64(&used_mask
);
593 return IRIS_SURFACE_NOT_USED
;
597 rewrite_src_with_bti(nir_builder
*b
, struct iris_binding_table
*bt
,
598 nir_instr
*instr
, nir_src
*src
,
599 enum iris_surface_group group
)
601 assert(bt
->sizes
[group
] > 0);
603 b
->cursor
= nir_before_instr(instr
);
605 if (nir_src_is_const(*src
)) {
606 uint32_t index
= nir_src_as_uint(*src
);
607 bti
= nir_imm_intN_t(b
, iris_group_index_to_bti(bt
, group
, index
),
610 /* Indirect usage makes all the surfaces of the group to be available,
611 * so we can just add the base.
613 assert(bt
->used_mask
[group
] == BITFIELD64_MASK(bt
->sizes
[group
]));
614 bti
= nir_iadd_imm(b
, src
->ssa
, bt
->offsets
[group
]);
616 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(bti
));
620 mark_used_with_src(struct iris_binding_table
*bt
, nir_src
*src
,
621 enum iris_surface_group group
)
623 assert(bt
->sizes
[group
] > 0);
625 if (nir_src_is_const(*src
)) {
626 uint64_t index
= nir_src_as_uint(*src
);
627 assert(index
< bt
->sizes
[group
]);
628 bt
->used_mask
[group
] |= 1ull << index
;
630 /* There's an indirect usage, we need all the surfaces. */
631 bt
->used_mask
[group
] = BITFIELD64_MASK(bt
->sizes
[group
]);
636 skip_compacting_binding_tables(void)
638 static int skip
= -1;
640 skip
= env_var_as_boolean("INTEL_DISABLE_COMPACT_BINDING_TABLE", false);
645 * Set up the binding table indices and apply to the shader.
648 iris_setup_binding_table(const struct gen_device_info
*devinfo
,
649 struct nir_shader
*nir
,
650 struct iris_binding_table
*bt
,
651 unsigned num_render_targets
,
652 unsigned num_system_values
,
655 const struct shader_info
*info
= &nir
->info
;
657 memset(bt
, 0, sizeof(*bt
));
659 /* Set the sizes for each surface group. For some groups, we already know
660 * upfront how many will be used, so mark them.
662 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
663 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET
] = num_render_targets
;
664 /* All render targets used. */
665 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET
] =
666 BITFIELD64_MASK(num_render_targets
);
668 /* Setup render target read surface group inorder to support non-coherent
669 * framebuffer fetch on Gen8
671 if (devinfo
->gen
== 8 && info
->outputs_read
) {
672 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = num_render_targets
;
673 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] =
674 BITFIELD64_MASK(num_render_targets
);
676 } else if (info
->stage
== MESA_SHADER_COMPUTE
) {
677 bt
->sizes
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
680 bt
->sizes
[IRIS_SURFACE_GROUP_TEXTURE
] = util_last_bit(info
->textures_used
);
681 bt
->used_mask
[IRIS_SURFACE_GROUP_TEXTURE
] = info
->textures_used
;
683 bt
->sizes
[IRIS_SURFACE_GROUP_IMAGE
] = info
->num_images
;
685 /* Allocate an extra slot in the UBO section for NIR constants.
686 * Binding table compaction will remove it if unnecessary.
688 * We don't include them in iris_compiled_shader::num_cbufs because
689 * they are uploaded separately from shs->constbuf[], but from a shader
690 * point of view, they're another UBO (at the end of the section).
692 bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] = num_cbufs
+ 1;
694 bt
->sizes
[IRIS_SURFACE_GROUP_SSBO
] = info
->num_ssbos
;
696 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
697 assert(bt
->sizes
[i
] <= SURFACE_GROUP_MAX_ELEMENTS
);
699 /* Mark surfaces used for the cases we don't have the information available
702 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
703 nir_foreach_block (block
, impl
) {
704 nir_foreach_instr (instr
, block
) {
705 if (instr
->type
!= nir_instr_type_intrinsic
)
708 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
709 switch (intrin
->intrinsic
) {
710 case nir_intrinsic_load_num_work_groups
:
711 bt
->used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
714 case nir_intrinsic_load_output
:
715 if (devinfo
->gen
== 8) {
716 mark_used_with_src(bt
, &intrin
->src
[0],
717 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
721 case nir_intrinsic_image_size
:
722 case nir_intrinsic_image_load
:
723 case nir_intrinsic_image_store
:
724 case nir_intrinsic_image_atomic_add
:
725 case nir_intrinsic_image_atomic_imin
:
726 case nir_intrinsic_image_atomic_umin
:
727 case nir_intrinsic_image_atomic_imax
:
728 case nir_intrinsic_image_atomic_umax
:
729 case nir_intrinsic_image_atomic_and
:
730 case nir_intrinsic_image_atomic_or
:
731 case nir_intrinsic_image_atomic_xor
:
732 case nir_intrinsic_image_atomic_exchange
:
733 case nir_intrinsic_image_atomic_comp_swap
:
734 case nir_intrinsic_image_load_raw_intel
:
735 case nir_intrinsic_image_store_raw_intel
:
736 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_IMAGE
);
739 case nir_intrinsic_load_ubo
:
740 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_UBO
);
743 case nir_intrinsic_store_ssbo
:
744 mark_used_with_src(bt
, &intrin
->src
[1], IRIS_SURFACE_GROUP_SSBO
);
747 case nir_intrinsic_get_buffer_size
:
748 case nir_intrinsic_ssbo_atomic_add
:
749 case nir_intrinsic_ssbo_atomic_imin
:
750 case nir_intrinsic_ssbo_atomic_umin
:
751 case nir_intrinsic_ssbo_atomic_imax
:
752 case nir_intrinsic_ssbo_atomic_umax
:
753 case nir_intrinsic_ssbo_atomic_and
:
754 case nir_intrinsic_ssbo_atomic_or
:
755 case nir_intrinsic_ssbo_atomic_xor
:
756 case nir_intrinsic_ssbo_atomic_exchange
:
757 case nir_intrinsic_ssbo_atomic_comp_swap
:
758 case nir_intrinsic_ssbo_atomic_fmin
:
759 case nir_intrinsic_ssbo_atomic_fmax
:
760 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
761 case nir_intrinsic_load_ssbo
:
762 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_SSBO
);
771 /* When disable we just mark everything as used. */
772 if (unlikely(skip_compacting_binding_tables())) {
773 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
774 bt
->used_mask
[i
] = BITFIELD64_MASK(bt
->sizes
[i
]);
777 /* Calculate the offsets and the binding table size based on the used
778 * surfaces. After this point, the functions to go between "group indices"
779 * and binding table indices can be used.
782 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
783 if (bt
->used_mask
[i
] != 0) {
784 bt
->offsets
[i
] = next
;
785 next
+= util_bitcount64(bt
->used_mask
[i
]);
788 bt
->size_bytes
= next
* 4;
790 if (unlikely(INTEL_DEBUG
& DEBUG_BT
)) {
791 iris_print_binding_table(stderr
, gl_shader_stage_name(info
->stage
), bt
);
794 /* Apply the binding table indices. The backend compiler is not expected
795 * to change those, as we haven't set any of the *_start entries in brw
799 nir_builder_init(&b
, impl
);
801 nir_foreach_block (block
, impl
) {
802 nir_foreach_instr (instr
, block
) {
803 if (instr
->type
== nir_instr_type_tex
) {
804 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
806 iris_group_index_to_bti(bt
, IRIS_SURFACE_GROUP_TEXTURE
,
811 if (instr
->type
!= nir_instr_type_intrinsic
)
814 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
815 switch (intrin
->intrinsic
) {
816 case nir_intrinsic_image_size
:
817 case nir_intrinsic_image_load
:
818 case nir_intrinsic_image_store
:
819 case nir_intrinsic_image_atomic_add
:
820 case nir_intrinsic_image_atomic_imin
:
821 case nir_intrinsic_image_atomic_umin
:
822 case nir_intrinsic_image_atomic_imax
:
823 case nir_intrinsic_image_atomic_umax
:
824 case nir_intrinsic_image_atomic_and
:
825 case nir_intrinsic_image_atomic_or
:
826 case nir_intrinsic_image_atomic_xor
:
827 case nir_intrinsic_image_atomic_exchange
:
828 case nir_intrinsic_image_atomic_comp_swap
:
829 case nir_intrinsic_image_load_raw_intel
:
830 case nir_intrinsic_image_store_raw_intel
:
831 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
832 IRIS_SURFACE_GROUP_IMAGE
);
835 case nir_intrinsic_load_ubo
:
836 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
837 IRIS_SURFACE_GROUP_UBO
);
840 case nir_intrinsic_store_ssbo
:
841 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[1],
842 IRIS_SURFACE_GROUP_SSBO
);
845 case nir_intrinsic_load_output
:
846 if (devinfo
->gen
== 8) {
847 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
848 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
852 case nir_intrinsic_get_buffer_size
:
853 case nir_intrinsic_ssbo_atomic_add
:
854 case nir_intrinsic_ssbo_atomic_imin
:
855 case nir_intrinsic_ssbo_atomic_umin
:
856 case nir_intrinsic_ssbo_atomic_imax
:
857 case nir_intrinsic_ssbo_atomic_umax
:
858 case nir_intrinsic_ssbo_atomic_and
:
859 case nir_intrinsic_ssbo_atomic_or
:
860 case nir_intrinsic_ssbo_atomic_xor
:
861 case nir_intrinsic_ssbo_atomic_exchange
:
862 case nir_intrinsic_ssbo_atomic_comp_swap
:
863 case nir_intrinsic_ssbo_atomic_fmin
:
864 case nir_intrinsic_ssbo_atomic_fmax
:
865 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
866 case nir_intrinsic_load_ssbo
:
867 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
868 IRIS_SURFACE_GROUP_SSBO
);
879 iris_debug_recompile(struct iris_context
*ice
,
880 struct shader_info
*info
,
881 const struct brw_base_prog_key
*key
)
883 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
884 const struct brw_compiler
*c
= screen
->compiler
;
889 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
890 _mesa_shader_stage_to_string(info
->stage
),
891 info
->name
? info
->name
: "(no identifier)",
892 info
->label
? info
->label
: "");
894 const void *old_key
=
895 iris_find_previous_compile(ice
, info
->stage
, key
->program_string_id
);
897 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
901 * Get the shader for the last enabled geometry stage.
903 * This stage is the one which will feed stream output and the rasterizer.
905 static gl_shader_stage
906 last_vue_stage(struct iris_context
*ice
)
908 if (ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
909 return MESA_SHADER_GEOMETRY
;
911 if (ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
912 return MESA_SHADER_TESS_EVAL
;
914 return MESA_SHADER_VERTEX
;
918 * Compile a vertex shader, and upload the assembly.
920 static struct iris_compiled_shader
*
921 iris_compile_vs(struct iris_context
*ice
,
922 struct iris_uncompiled_shader
*ish
,
923 const struct brw_vs_prog_key
*key
)
925 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
926 const struct brw_compiler
*compiler
= screen
->compiler
;
927 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
928 void *mem_ctx
= ralloc_context(NULL
);
929 struct brw_vs_prog_data
*vs_prog_data
=
930 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
931 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
932 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
933 enum brw_param_builtin
*system_values
;
934 unsigned num_system_values
;
937 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
939 if (key
->nr_userclip_plane_consts
) {
940 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
941 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true,
943 nir_lower_io_to_temporaries(nir
, impl
, true, false);
944 nir_lower_global_vars_to_local(nir
);
945 nir_lower_vars_to_ssa(nir
);
946 nir_shader_gather_info(nir
, impl
);
949 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
951 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
952 &num_system_values
, &num_cbufs
);
954 struct iris_binding_table bt
;
955 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
956 num_system_values
, num_cbufs
);
958 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
960 brw_compute_vue_map(devinfo
,
961 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
962 nir
->info
.separate_shader
);
964 /* Don't tell the backend about our clip plane constants, we've already
965 * lowered them in NIR and we don't want it doing it again.
967 struct brw_vs_prog_key key_no_ucp
= *key
;
968 key_no_ucp
.nr_userclip_plane_consts
= 0;
970 char *error_str
= NULL
;
971 const unsigned *program
=
972 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &key_no_ucp
, vs_prog_data
,
973 nir
, -1, NULL
, &error_str
);
974 if (program
== NULL
) {
975 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
976 ralloc_free(mem_ctx
);
980 if (ish
->compiled_once
) {
981 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
983 ish
->compiled_once
= true;
987 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
988 &vue_prog_data
->vue_map
);
990 struct iris_compiled_shader
*shader
=
991 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
992 prog_data
, so_decls
, system_values
, num_system_values
,
995 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
997 ralloc_free(mem_ctx
);
1002 * Update the current vertex shader variant.
1004 * Fill out the key, look in the cache, compile and bind if needed.
1007 iris_update_compiled_vs(struct iris_context
*ice
)
1009 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1010 struct iris_uncompiled_shader
*ish
=
1011 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
1012 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1013 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1015 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1016 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1018 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
1019 struct iris_compiled_shader
*shader
=
1020 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
1023 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1026 shader
= iris_compile_vs(ice
, ish
, &key
);
1028 if (old
!= shader
) {
1029 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
1030 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
1031 IRIS_DIRTY_BINDINGS_VS
|
1032 IRIS_DIRTY_CONSTANTS_VS
|
1034 shs
->sysvals_need_upload
= true;
1036 const struct brw_vs_prog_data
*vs_prog_data
=
1037 (void *) shader
->prog_data
;
1038 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
1039 vs_prog_data
->uses_baseinstance
;
1040 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
1041 vs_prog_data
->uses_is_indexed_draw
;
1042 const bool needs_sgvs_element
= uses_draw_params
||
1043 vs_prog_data
->uses_instanceid
||
1044 vs_prog_data
->uses_vertexid
;
1045 bool needs_edge_flag
= false;
1046 nir_foreach_variable(var
, &ish
->nir
->inputs
) {
1047 if (var
->data
.location
== VERT_ATTRIB_EDGEFLAG
)
1048 needs_edge_flag
= true;
1051 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
1052 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
1053 ice
->state
.vs_needs_edge_flag
!= needs_edge_flag
) {
1054 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
1055 IRIS_DIRTY_VERTEX_ELEMENTS
;
1057 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
1058 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
1059 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
1060 ice
->state
.vs_needs_edge_flag
= needs_edge_flag
;
1065 * Get the shader_info for a given stage, or NULL if the stage is disabled.
1067 const struct shader_info
*
1068 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
1070 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
1075 const nir_shader
*nir
= ish
->nir
;
1080 * Get the union of TCS output and TES input slots.
1082 * TCS and TES need to agree on a common URB entry layout. In particular,
1083 * the data for all patch vertices is stored in a single URB entry (unlike
1084 * GS which has one entry per input vertex). This means that per-vertex
1085 * array indexing needs a stride.
1087 * SSO requires locations to match, but doesn't require the number of
1088 * outputs/inputs to match (in fact, the TCS often has extra outputs).
1089 * So, we need to take the extra step of unifying these on the fly.
1092 get_unified_tess_slots(const struct iris_context
*ice
,
1093 uint64_t *per_vertex_slots
,
1094 uint32_t *per_patch_slots
)
1096 const struct shader_info
*tcs
=
1097 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
1098 const struct shader_info
*tes
=
1099 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1101 *per_vertex_slots
= tes
->inputs_read
;
1102 *per_patch_slots
= tes
->patch_inputs_read
;
1105 *per_vertex_slots
|= tcs
->outputs_written
;
1106 *per_patch_slots
|= tcs
->patch_outputs_written
;
1111 * Compile a tessellation control shader, and upload the assembly.
1113 static struct iris_compiled_shader
*
1114 iris_compile_tcs(struct iris_context
*ice
,
1115 struct iris_uncompiled_shader
*ish
,
1116 const struct brw_tcs_prog_key
*key
)
1118 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1119 const struct brw_compiler
*compiler
= screen
->compiler
;
1120 const struct nir_shader_compiler_options
*options
=
1121 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
1122 void *mem_ctx
= ralloc_context(NULL
);
1123 struct brw_tcs_prog_data
*tcs_prog_data
=
1124 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
1125 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
1126 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1127 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1128 enum brw_param_builtin
*system_values
= NULL
;
1129 unsigned num_system_values
= 0;
1130 unsigned num_cbufs
= 0;
1134 struct iris_binding_table bt
;
1137 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1139 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1140 &num_system_values
, &num_cbufs
);
1141 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1142 num_system_values
, num_cbufs
);
1143 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1145 nir
= brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
1147 /* Reserve space for passing the default tess levels as constants. */
1149 num_system_values
= 8;
1151 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
1152 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
1153 prog_data
->nr_params
= num_system_values
;
1155 if (key
->tes_primitive_mode
== GL_QUADS
) {
1156 for (int i
= 0; i
< 4; i
++)
1157 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1159 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1160 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
1161 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
1162 for (int i
= 0; i
< 3; i
++)
1163 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1165 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1167 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
1168 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
1169 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
1172 /* Manually setup the TCS binding table. */
1173 memset(&bt
, 0, sizeof(bt
));
1174 bt
.sizes
[IRIS_SURFACE_GROUP_UBO
] = 1;
1175 bt
.used_mask
[IRIS_SURFACE_GROUP_UBO
] = 1;
1178 prog_data
->ubo_ranges
[0].length
= 1;
1181 char *error_str
= NULL
;
1182 const unsigned *program
=
1183 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, key
, tcs_prog_data
, nir
,
1184 -1, NULL
, &error_str
);
1185 if (program
== NULL
) {
1186 dbg_printf("Failed to compile control shader: %s\n", error_str
);
1187 ralloc_free(mem_ctx
);
1192 if (ish
->compiled_once
) {
1193 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1195 ish
->compiled_once
= true;
1199 struct iris_compiled_shader
*shader
=
1200 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
1201 prog_data
, NULL
, system_values
, num_system_values
,
1205 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1207 ralloc_free(mem_ctx
);
1212 * Update the current tessellation control shader variant.
1214 * Fill out the key, look in the cache, compile and bind if needed.
1217 iris_update_compiled_tcs(struct iris_context
*ice
)
1219 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
1220 struct iris_uncompiled_shader
*tcs
=
1221 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
1222 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1223 const struct brw_compiler
*compiler
= screen
->compiler
;
1224 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1226 const struct shader_info
*tes_info
=
1227 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1228 struct brw_tcs_prog_key key
= {
1229 KEY_INIT_NO_ID(devinfo
->gen
),
1230 .base
.program_string_id
= tcs
? tcs
->program_id
: 0,
1231 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
1233 !tcs
|| compiler
->use_tcs_8_patch
? ice
->state
.vertices_per_patch
: 0,
1234 .quads_workaround
= devinfo
->gen
< 9 &&
1235 tes_info
->tess
.primitive_mode
== GL_QUADS
&&
1236 tes_info
->tess
.spacing
== TESS_SPACING_EQUAL
,
1238 get_unified_tess_slots(ice
, &key
.outputs_written
,
1239 &key
.patch_outputs_written
);
1240 ice
->vtbl
.populate_tcs_key(ice
, &key
);
1242 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
1243 struct iris_compiled_shader
*shader
=
1244 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
1247 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
1250 shader
= iris_compile_tcs(ice
, tcs
, &key
);
1252 if (old
!= shader
) {
1253 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
1254 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
1255 IRIS_DIRTY_BINDINGS_TCS
|
1256 IRIS_DIRTY_CONSTANTS_TCS
;
1257 shs
->sysvals_need_upload
= true;
1262 * Compile a tessellation evaluation shader, and upload the assembly.
1264 static struct iris_compiled_shader
*
1265 iris_compile_tes(struct iris_context
*ice
,
1266 struct iris_uncompiled_shader
*ish
,
1267 const struct brw_tes_prog_key
*key
)
1269 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1270 const struct brw_compiler
*compiler
= screen
->compiler
;
1271 void *mem_ctx
= ralloc_context(NULL
);
1272 struct brw_tes_prog_data
*tes_prog_data
=
1273 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1274 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1275 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1276 enum brw_param_builtin
*system_values
;
1277 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1278 unsigned num_system_values
;
1281 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1283 if (key
->nr_userclip_plane_consts
) {
1284 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1285 nir_lower_clip_vs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, true,
1287 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1288 nir_lower_global_vars_to_local(nir
);
1289 nir_lower_vars_to_ssa(nir
);
1290 nir_shader_gather_info(nir
, impl
);
1293 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1294 &num_system_values
, &num_cbufs
);
1296 struct iris_binding_table bt
;
1297 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1298 num_system_values
, num_cbufs
);
1300 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1302 struct brw_vue_map input_vue_map
;
1303 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1304 key
->patch_inputs_read
);
1306 char *error_str
= NULL
;
1307 const unsigned *program
=
1308 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, key
, &input_vue_map
,
1309 tes_prog_data
, nir
, -1, NULL
, &error_str
);
1310 if (program
== NULL
) {
1311 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1312 ralloc_free(mem_ctx
);
1316 if (ish
->compiled_once
) {
1317 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1319 ish
->compiled_once
= true;
1322 uint32_t *so_decls
=
1323 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1324 &vue_prog_data
->vue_map
);
1327 struct iris_compiled_shader
*shader
=
1328 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1329 prog_data
, so_decls
, system_values
, num_system_values
,
1332 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1334 ralloc_free(mem_ctx
);
1339 * Update the current tessellation evaluation shader variant.
1341 * Fill out the key, look in the cache, compile and bind if needed.
1344 iris_update_compiled_tes(struct iris_context
*ice
)
1346 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
1347 struct iris_uncompiled_shader
*ish
=
1348 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1349 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1350 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1352 struct brw_tes_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1353 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1354 ice
->vtbl
.populate_tes_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1356 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1357 struct iris_compiled_shader
*shader
=
1358 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1361 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1364 shader
= iris_compile_tes(ice
, ish
, &key
);
1366 if (old
!= shader
) {
1367 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1368 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1369 IRIS_DIRTY_BINDINGS_TES
|
1370 IRIS_DIRTY_CONSTANTS_TES
;
1371 shs
->sysvals_need_upload
= true;
1374 /* TODO: Could compare and avoid flagging this. */
1375 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1376 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1377 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1378 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].sysvals_need_upload
= true;
1383 * Compile a geometry shader, and upload the assembly.
1385 static struct iris_compiled_shader
*
1386 iris_compile_gs(struct iris_context
*ice
,
1387 struct iris_uncompiled_shader
*ish
,
1388 const struct brw_gs_prog_key
*key
)
1390 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1391 const struct brw_compiler
*compiler
= screen
->compiler
;
1392 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1393 void *mem_ctx
= ralloc_context(NULL
);
1394 struct brw_gs_prog_data
*gs_prog_data
=
1395 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1396 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1397 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1398 enum brw_param_builtin
*system_values
;
1399 unsigned num_system_values
;
1402 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1404 if (key
->nr_userclip_plane_consts
) {
1405 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1406 nir_lower_clip_gs(nir
, (1 << key
->nr_userclip_plane_consts
) - 1, false);
1407 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1408 nir_lower_global_vars_to_local(nir
);
1409 nir_lower_vars_to_ssa(nir
);
1410 nir_shader_gather_info(nir
, impl
);
1413 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1414 &num_system_values
, &num_cbufs
);
1416 struct iris_binding_table bt
;
1417 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1418 num_system_values
, num_cbufs
);
1420 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1422 brw_compute_vue_map(devinfo
,
1423 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1424 nir
->info
.separate_shader
);
1426 char *error_str
= NULL
;
1427 const unsigned *program
=
1428 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, key
, gs_prog_data
, nir
,
1429 NULL
, -1, NULL
, &error_str
);
1430 if (program
== NULL
) {
1431 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1432 ralloc_free(mem_ctx
);
1436 if (ish
->compiled_once
) {
1437 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1439 ish
->compiled_once
= true;
1442 uint32_t *so_decls
=
1443 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1444 &vue_prog_data
->vue_map
);
1446 struct iris_compiled_shader
*shader
=
1447 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1448 prog_data
, so_decls
, system_values
, num_system_values
,
1451 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1453 ralloc_free(mem_ctx
);
1458 * Update the current geometry shader variant.
1460 * Fill out the key, look in the cache, compile and bind if needed.
1463 iris_update_compiled_gs(struct iris_context
*ice
)
1465 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
1466 struct iris_uncompiled_shader
*ish
=
1467 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1468 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1469 struct iris_compiled_shader
*shader
= NULL
;
1472 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1473 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1474 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1475 ice
->vtbl
.populate_gs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1478 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1481 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1484 shader
= iris_compile_gs(ice
, ish
, &key
);
1487 if (old
!= shader
) {
1488 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1489 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1490 IRIS_DIRTY_BINDINGS_GS
|
1491 IRIS_DIRTY_CONSTANTS_GS
;
1492 shs
->sysvals_need_upload
= true;
1497 * Compile a fragment (pixel) shader, and upload the assembly.
1499 static struct iris_compiled_shader
*
1500 iris_compile_fs(struct iris_context
*ice
,
1501 struct iris_uncompiled_shader
*ish
,
1502 const struct brw_wm_prog_key
*key
,
1503 struct brw_vue_map
*vue_map
)
1505 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1506 const struct brw_compiler
*compiler
= screen
->compiler
;
1507 void *mem_ctx
= ralloc_context(NULL
);
1508 struct brw_wm_prog_data
*fs_prog_data
=
1509 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1510 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1511 enum brw_param_builtin
*system_values
;
1512 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1513 unsigned num_system_values
;
1516 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1518 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1520 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1521 &num_system_values
, &num_cbufs
);
1523 /* Lower output variables to load_output intrinsics before setting up
1524 * binding tables, so iris_setup_binding_table can map any load_output
1525 * intrinsics to IRIS_SURFACE_GROUP_RENDER_TARGET_READ on Gen8 for
1526 * non-coherent framebuffer fetches.
1528 brw_nir_lower_fs_outputs(nir
);
1530 /* On Gen11+, shader RT write messages have a "Null Render Target" bit
1531 * and do not need a binding table entry with a null surface. Earlier
1532 * generations need an entry for a null surface.
1534 int null_rts
= devinfo
->gen
< 11 ? 1 : 0;
1536 struct iris_binding_table bt
;
1537 iris_setup_binding_table(devinfo
, nir
, &bt
,
1538 MAX2(key
->nr_color_regions
, null_rts
),
1539 num_system_values
, num_cbufs
);
1541 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1543 char *error_str
= NULL
;
1544 const unsigned *program
=
1545 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, key
, fs_prog_data
,
1546 nir
, -1, -1, -1, true, false, vue_map
,
1548 if (program
== NULL
) {
1549 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1550 ralloc_free(mem_ctx
);
1554 if (ish
->compiled_once
) {
1555 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1557 ish
->compiled_once
= true;
1560 struct iris_compiled_shader
*shader
=
1561 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1562 prog_data
, NULL
, system_values
, num_system_values
,
1565 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1567 ralloc_free(mem_ctx
);
1572 * Update the current fragment shader variant.
1574 * Fill out the key, look in the cache, compile and bind if needed.
1577 iris_update_compiled_fs(struct iris_context
*ice
)
1579 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1580 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1581 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_FRAGMENT
];
1582 struct iris_uncompiled_shader
*ish
=
1583 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1584 struct brw_wm_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1585 ice
->vtbl
.populate_fs_key(ice
, &ish
->nir
->info
, &key
);
1587 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1588 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1590 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1591 struct iris_compiled_shader
*shader
=
1592 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1595 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1598 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1600 if (old
!= shader
) {
1601 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1602 // toggles. might be able to avoid flagging SBE too.
1603 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1604 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1605 IRIS_DIRTY_BINDINGS_FS
|
1606 IRIS_DIRTY_CONSTANTS_FS
|
1610 shs
->sysvals_need_upload
= true;
1615 * Update the last enabled stage's VUE map.
1617 * When the shader feeding the rasterizer's output interface changes, we
1618 * need to re-emit various packets.
1621 update_last_vue_map(struct iris_context
*ice
,
1622 struct brw_stage_prog_data
*prog_data
)
1624 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1625 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1626 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1627 const uint64_t changed_slots
=
1628 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1630 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1631 ice
->state
.num_viewports
=
1632 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1633 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1634 IRIS_DIRTY_SF_CL_VIEWPORT
|
1635 IRIS_DIRTY_CC_VIEWPORT
|
1636 IRIS_DIRTY_SCISSOR_RECT
|
1637 IRIS_DIRTY_UNCOMPILED_FS
|
1638 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1641 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1642 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1645 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1649 iris_update_pull_constant_descriptors(struct iris_context
*ice
,
1650 gl_shader_stage stage
)
1652 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
1654 if (!shader
|| !shader
->prog_data
->has_ubo_pull
)
1657 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1658 bool any_new_descriptors
=
1659 shader
->num_system_values
> 0 && shs
->sysvals_need_upload
;
1661 unsigned bound_cbufs
= shs
->bound_cbufs
;
1663 while (bound_cbufs
) {
1664 const int i
= u_bit_scan(&bound_cbufs
);
1665 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
1666 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
1667 if (!surf_state
->res
&& cbuf
->buffer
) {
1668 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
1669 any_new_descriptors
= true;
1673 if (any_new_descriptors
)
1674 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1678 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1680 static struct brw_vue_prog_data
*
1681 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1683 if (!ice
->shaders
.prog
[stage
])
1686 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1689 // XXX: iris_compiled_shaders are space-leaking :(
1690 // XXX: do remember to unbind them if deleting them.
1693 * Update the current shader variants for the given state.
1695 * This should be called on every draw call to ensure that the correct
1696 * shaders are bound. It will also flag any dirty state triggered by
1697 * swapping out those shaders.
1700 iris_update_compiled_shaders(struct iris_context
*ice
)
1702 const uint64_t dirty
= ice
->state
.dirty
;
1704 struct brw_vue_prog_data
*old_prog_datas
[4];
1705 if (!(dirty
& IRIS_DIRTY_URB
)) {
1706 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1707 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1710 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1711 struct iris_uncompiled_shader
*tes
=
1712 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1714 iris_update_compiled_tcs(ice
);
1715 iris_update_compiled_tes(ice
);
1717 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1718 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1720 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1721 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1722 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1726 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1727 iris_update_compiled_vs(ice
);
1728 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1729 iris_update_compiled_gs(ice
);
1731 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1732 const struct iris_compiled_shader
*gs
=
1733 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1734 const struct iris_compiled_shader
*tes
=
1735 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1737 bool points_or_lines
= false;
1740 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1742 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1743 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1745 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1747 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1748 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1751 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1752 /* Outbound to XY Clip enables */
1753 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1754 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1758 gl_shader_stage last_stage
= last_vue_stage(ice
);
1759 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1760 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1761 update_last_vue_map(ice
, shader
->prog_data
);
1762 if (ice
->state
.streamout
!= shader
->streamout
) {
1763 ice
->state
.streamout
= shader
->streamout
;
1764 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1767 if (ice
->state
.streamout_active
) {
1768 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1769 struct iris_stream_output_target
*so
=
1770 (void *) ice
->state
.so_target
[i
];
1772 so
->stride
= ish
->stream_output
.stride
[i
] * sizeof(uint32_t);
1776 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1777 iris_update_compiled_fs(ice
);
1779 /* Changing shader interfaces may require a URB configuration. */
1780 if (!(dirty
& IRIS_DIRTY_URB
)) {
1781 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1782 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1783 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1784 if (!!old
!= !!new ||
1785 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1786 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1792 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_FRAGMENT
; i
++) {
1793 if (ice
->state
.dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< i
))
1794 iris_update_pull_constant_descriptors(ice
, i
);
1798 static struct iris_compiled_shader
*
1799 iris_compile_cs(struct iris_context
*ice
,
1800 struct iris_uncompiled_shader
*ish
,
1801 const struct brw_cs_prog_key
*key
)
1803 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1804 const struct brw_compiler
*compiler
= screen
->compiler
;
1805 void *mem_ctx
= ralloc_context(NULL
);
1806 struct brw_cs_prog_data
*cs_prog_data
=
1807 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1808 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1809 enum brw_param_builtin
*system_values
;
1810 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1811 unsigned num_system_values
;
1814 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1816 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1817 &num_system_values
, &num_cbufs
);
1819 struct iris_binding_table bt
;
1820 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1821 num_system_values
, num_cbufs
);
1823 char *error_str
= NULL
;
1824 const unsigned *program
=
1825 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, key
, cs_prog_data
,
1826 nir
, -1, NULL
, &error_str
);
1827 if (program
== NULL
) {
1828 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1829 ralloc_free(mem_ctx
);
1833 if (ish
->compiled_once
) {
1834 iris_debug_recompile(ice
, &nir
->info
, &key
->base
);
1836 ish
->compiled_once
= true;
1839 struct iris_compiled_shader
*shader
=
1840 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1841 prog_data
, NULL
, system_values
, num_system_values
,
1844 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1846 ralloc_free(mem_ctx
);
1851 iris_update_compiled_cs(struct iris_context
*ice
)
1853 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
1854 struct iris_uncompiled_shader
*ish
=
1855 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1857 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1858 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1859 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
1860 ice
->vtbl
.populate_cs_key(ice
, &key
);
1862 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1863 struct iris_compiled_shader
*shader
=
1864 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1867 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1870 shader
= iris_compile_cs(ice
, ish
, &key
);
1872 if (old
!= shader
) {
1873 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1874 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1875 IRIS_DIRTY_BINDINGS_CS
|
1876 IRIS_DIRTY_CONSTANTS_CS
;
1877 shs
->sysvals_need_upload
= true;
1882 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1884 if (ice
->state
.dirty
& IRIS_DIRTY_UNCOMPILED_CS
)
1885 iris_update_compiled_cs(ice
);
1887 if (ice
->state
.dirty
& IRIS_DIRTY_CONSTANTS_CS
)
1888 iris_update_pull_constant_descriptors(ice
, MESA_SHADER_COMPUTE
);
1892 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1895 assert(cs_prog_data
->push
.total
.size
> 0);
1896 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1897 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1898 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1899 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1904 * Allocate scratch BOs as needed for the given per-thread size and stage.
1907 iris_get_scratch_space(struct iris_context
*ice
,
1908 unsigned per_thread_scratch
,
1909 gl_shader_stage stage
)
1911 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1912 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1913 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1915 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1916 assert(encoded_size
< (1 << 16));
1918 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1920 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1922 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1923 * must allocate scratch space enough so that each slice has 4
1926 * According to the other driver team, this applies to compute shaders
1927 * as well. This is not currently documented at all.
1929 * This hack is no longer necessary on Gen11+.
1931 unsigned subslice_total
= screen
->subslice_total
;
1932 if (devinfo
->gen
< 11)
1933 subslice_total
= 4 * devinfo
->num_slices
;
1934 assert(subslice_total
>= screen
->subslice_total
);
1937 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1939 if (devinfo
->gen
>= 11) {
1940 /* The MEDIA_VFE_STATE docs say:
1942 * "Starting with this configuration, the Maximum Number of
1943 * Threads must be set to (#EU * 8) for GPGPU dispatches.
1945 * Although there are only 7 threads per EU in the configuration,
1946 * the FFTID is calculated as if there are 8 threads per EU,
1947 * which in turn requires a larger amount of Scratch Space to be
1948 * allocated by the driver."
1950 scratch_ids_per_subslice
= 8 * 8;
1953 uint32_t max_threads
[] = {
1954 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
1955 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
1956 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
1957 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
1958 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
1959 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
1962 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
1964 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
1970 /* ------------------------------------------------------------------- */
1973 * The pipe->create_[stage]_state() driver hooks.
1975 * Performs basic NIR preprocessing, records any state dependencies, and
1976 * returns an iris_uncompiled_shader as the Gallium CSO.
1978 * Actual shader compilation to assembly happens later, at first use.
1981 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
1983 const struct pipe_stream_output_info
*so_info
)
1985 struct iris_context
*ice
= (void *)ctx
;
1986 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1987 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1989 struct iris_uncompiled_shader
*ish
=
1990 calloc(1, sizeof(struct iris_uncompiled_shader
));
1994 brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
1996 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
1997 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
2001 if (nir
->constant_data_size
> 0) {
2002 unsigned data_offset
;
2003 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
2004 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
2006 struct pipe_shader_buffer psb
= {
2007 .buffer
= ish
->const_data
,
2008 .buffer_offset
= data_offset
,
2009 .buffer_size
= nir
->constant_data_size
,
2011 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
2014 ish
->program_id
= get_new_program_id(screen
);
2017 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
2018 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
2021 /* Save this now before potentially dropping nir->info.name */
2022 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
2023 ish
->use_alt_mode
= true;
2025 if (screen
->disk_cache
) {
2026 /* Serialize the NIR to a binary blob that we can hash for the disk
2027 * cache. Drop unnecessary information (like variable names)
2028 * so the serialized NIR is smaller, and also to let us detect more
2029 * isomorphic shaders when hashing, increasing cache hits.
2033 nir_serialize(&blob
, nir
, true);
2034 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
2041 static struct iris_uncompiled_shader
*
2042 iris_create_shader_state(struct pipe_context
*ctx
,
2043 const struct pipe_shader_state
*state
)
2045 struct nir_shader
*nir
;
2047 if (state
->type
== PIPE_SHADER_IR_TGSI
)
2048 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2050 nir
= state
->ir
.nir
;
2052 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
2056 iris_create_vs_state(struct pipe_context
*ctx
,
2057 const struct pipe_shader_state
*state
)
2059 struct iris_context
*ice
= (void *) ctx
;
2060 struct iris_screen
*screen
= (void *) ctx
->screen
;
2061 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2063 /* User clip planes */
2064 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2065 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2067 if (screen
->precompile
) {
2068 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2069 struct brw_vs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2071 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2072 iris_compile_vs(ice
, ish
, &key
);
2079 iris_create_tcs_state(struct pipe_context
*ctx
,
2080 const struct pipe_shader_state
*state
)
2082 struct iris_context
*ice
= (void *) ctx
;
2083 struct iris_screen
*screen
= (void *) ctx
->screen
;
2084 const struct brw_compiler
*compiler
= screen
->compiler
;
2085 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2086 struct shader_info
*info
= &ish
->nir
->info
;
2088 if (screen
->precompile
) {
2089 const unsigned _GL_TRIANGLES
= 0x0004;
2090 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2091 struct brw_tcs_prog_key key
= {
2092 KEY_INIT(devinfo
->gen
),
2093 // XXX: make sure the linker fills this out from the TES...
2094 .tes_primitive_mode
=
2095 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
2097 .outputs_written
= info
->outputs_written
,
2098 .patch_outputs_written
= info
->patch_outputs_written
,
2101 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
2102 * We don't have that information, so we randomly guess that the input
2103 * and output patches are the same size. This is a bad guess, but we
2104 * can't do much better.
2106 if (compiler
->use_tcs_8_patch
)
2107 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
2109 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2110 iris_compile_tcs(ice
, ish
, &key
);
2117 iris_create_tes_state(struct pipe_context
*ctx
,
2118 const struct pipe_shader_state
*state
)
2120 struct iris_context
*ice
= (void *) ctx
;
2121 struct iris_screen
*screen
= (void *) ctx
->screen
;
2122 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2123 struct shader_info
*info
= &ish
->nir
->info
;
2125 /* User clip planes */
2126 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2127 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2129 if (screen
->precompile
) {
2130 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2131 struct brw_tes_prog_key key
= {
2132 KEY_INIT(devinfo
->gen
),
2133 // XXX: not ideal, need TCS output/TES input unification
2134 .inputs_read
= info
->inputs_read
,
2135 .patch_inputs_read
= info
->patch_inputs_read
,
2138 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2139 iris_compile_tes(ice
, ish
, &key
);
2146 iris_create_gs_state(struct pipe_context
*ctx
,
2147 const struct pipe_shader_state
*state
)
2149 struct iris_context
*ice
= (void *) ctx
;
2150 struct iris_screen
*screen
= (void *) ctx
->screen
;
2151 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2153 /* User clip planes */
2154 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2155 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2157 if (screen
->precompile
) {
2158 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2159 struct brw_gs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2161 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2162 iris_compile_gs(ice
, ish
, &key
);
2169 iris_create_fs_state(struct pipe_context
*ctx
,
2170 const struct pipe_shader_state
*state
)
2172 struct iris_context
*ice
= (void *) ctx
;
2173 struct iris_screen
*screen
= (void *) ctx
->screen
;
2174 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2175 struct shader_info
*info
= &ish
->nir
->info
;
2177 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
2178 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
2179 (1ull << IRIS_NOS_RASTERIZER
) |
2180 (1ull << IRIS_NOS_BLEND
);
2182 /* The program key needs the VUE map if there are > 16 inputs */
2183 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
2184 BRW_FS_VARYING_INPUT_MASK
) > 16) {
2185 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
2188 if (screen
->precompile
) {
2189 const uint64_t color_outputs
= info
->outputs_written
&
2190 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
2191 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
2192 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
2194 bool can_rearrange_varyings
=
2195 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
2197 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2198 struct brw_wm_prog_key key
= {
2199 KEY_INIT(devinfo
->gen
),
2200 .nr_color_regions
= util_bitcount(color_outputs
),
2201 .coherent_fb_fetch
= devinfo
->gen
>= 9,
2202 .input_slots_valid
=
2203 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
2206 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2207 iris_compile_fs(ice
, ish
, &key
, NULL
);
2214 iris_create_compute_state(struct pipe_context
*ctx
,
2215 const struct pipe_compute_state
*state
)
2217 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
2219 struct iris_context
*ice
= (void *) ctx
;
2220 struct iris_screen
*screen
= (void *) ctx
->screen
;
2221 struct iris_uncompiled_shader
*ish
=
2222 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
2224 // XXX: disallow more than 64KB of shared variables
2226 if (screen
->precompile
) {
2227 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2228 struct brw_cs_prog_key key
= { KEY_INIT(devinfo
->gen
) };
2230 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2231 iris_compile_cs(ice
, ish
, &key
);
2238 * The pipe->delete_[stage]_state() driver hooks.
2240 * Frees the iris_uncompiled_shader.
2243 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
2245 struct iris_uncompiled_shader
*ish
= state
;
2246 struct iris_context
*ice
= (void *) ctx
;
2248 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
2249 ice
->shaders
.uncompiled
[stage
] = NULL
;
2250 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2253 if (ish
->const_data
) {
2254 pipe_resource_reference(&ish
->const_data
, NULL
);
2255 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
2258 ralloc_free(ish
->nir
);
2263 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
2265 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
2269 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
2271 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
2275 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
2277 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
2281 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
2283 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
2287 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
2289 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
2293 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
2295 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
2299 * The pipe->bind_[stage]_state() driver hook.
2301 * Binds an uncompiled shader as the current one for a particular stage.
2302 * Updates dirty tracking to account for the shader's NOS.
2305 bind_shader_state(struct iris_context
*ice
,
2306 struct iris_uncompiled_shader
*ish
,
2307 gl_shader_stage stage
)
2309 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2310 const uint64_t nos
= ish
? ish
->nos
: 0;
2312 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
2313 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
2315 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
2316 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
2317 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
2320 ice
->shaders
.uncompiled
[stage
] = ish
;
2321 ice
->state
.dirty
|= dirty_bit
;
2323 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
2324 * (or that they no longer need to do so).
2326 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
2328 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
2330 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
2335 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
2337 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2338 struct iris_uncompiled_shader
*new_ish
= state
;
2341 ice
->state
.window_space_position
!=
2342 new_ish
->nir
->info
.vs
.window_space_position
) {
2343 ice
->state
.window_space_position
=
2344 new_ish
->nir
->info
.vs
.window_space_position
;
2346 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
2348 IRIS_DIRTY_CC_VIEWPORT
;
2351 bind_shader_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
2355 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
2357 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
2361 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
2363 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2365 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2366 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
2367 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2369 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
2373 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
2375 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2377 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2378 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
2379 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2381 bind_shader_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
2385 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
2387 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2388 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2389 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2390 struct iris_uncompiled_shader
*old_ish
=
2391 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2392 struct iris_uncompiled_shader
*new_ish
= state
;
2394 const unsigned color_bits
=
2395 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
2396 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
2398 /* Fragment shader outputs influence HasWriteableRT */
2399 if (!old_ish
|| !new_ish
||
2400 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
2401 (new_ish
->nir
->info
.outputs_written
& color_bits
))
2402 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
2404 if (devinfo
->gen
== 8)
2405 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
2407 bind_shader_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
2411 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
2413 bind_shader_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
2417 iris_init_program_functions(struct pipe_context
*ctx
)
2419 ctx
->create_vs_state
= iris_create_vs_state
;
2420 ctx
->create_tcs_state
= iris_create_tcs_state
;
2421 ctx
->create_tes_state
= iris_create_tes_state
;
2422 ctx
->create_gs_state
= iris_create_gs_state
;
2423 ctx
->create_fs_state
= iris_create_fs_state
;
2424 ctx
->create_compute_state
= iris_create_compute_state
;
2426 ctx
->delete_vs_state
= iris_delete_vs_state
;
2427 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
2428 ctx
->delete_tes_state
= iris_delete_tes_state
;
2429 ctx
->delete_gs_state
= iris_delete_gs_state
;
2430 ctx
->delete_fs_state
= iris_delete_fs_state
;
2431 ctx
->delete_compute_state
= iris_delete_cs_state
;
2433 ctx
->bind_vs_state
= iris_bind_vs_state
;
2434 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2435 ctx
->bind_tes_state
= iris_bind_tes_state
;
2436 ctx
->bind_gs_state
= iris_bind_gs_state
;
2437 ctx
->bind_fs_state
= iris_bind_fs_state
;
2438 ctx
->bind_compute_state
= iris_bind_cs_state
;