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24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
37 #include "compiler/nir/nir.h"
40 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
41 * or shader image. This causes a self-dependency, where both rendering
42 * and sampling may concurrently read or write the CCS buffer, causing
46 disable_rb_aux_buffer(struct iris_context
*ice
,
47 bool *draw_aux_buffer_disabled
,
48 struct iris_resource
*tex_res
,
49 unsigned min_level
, unsigned num_levels
,
52 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
55 /* We only need to worry about color compression and fast clears. */
56 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
57 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
60 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
61 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
65 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
67 if (rb_res
->bo
== tex_res
->bo
&&
68 surf
->base
.u
.tex
.level
>= min_level
&&
69 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
70 found
= draw_aux_buffer_disabled
[i
] = true;
76 "Disabling CCS because a renderbuffer is also bound %s.\n",
84 resolve_sampler_views(struct iris_context
*ice
,
85 struct iris_batch
*batch
,
86 struct iris_shader_state
*shs
,
87 const struct shader_info
*info
,
88 bool *draw_aux_buffer_disabled
,
89 bool consider_framebuffer
)
91 uint32_t views
= info
? (shs
->bound_sampler_views
& info
->textures_used
) : 0;
93 unsigned astc5x5_wa_bits
= 0; // XXX: actual tracking
96 const int i
= u_bit_scan(&views
);
97 struct iris_sampler_view
*isv
= shs
->textures
[i
];
98 struct iris_resource
*res
= (void *) isv
->base
.texture
;
100 if (res
->base
.target
!= PIPE_BUFFER
) {
101 if (consider_framebuffer
) {
102 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
103 res
, isv
->view
.base_level
, isv
->view
.levels
,
107 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
108 isv
->view
.base_level
, isv
->view
.levels
,
109 isv
->view
.base_array_layer
,
114 iris_cache_flush_for_read(batch
, res
->bo
);
119 resolve_image_views(struct iris_context
*ice
,
120 struct iris_batch
*batch
,
121 struct iris_shader_state
*shs
,
122 bool *draw_aux_buffer_disabled
,
123 bool consider_framebuffer
)
125 /* TODO: Consider images used by program */
126 uint32_t views
= shs
->bound_image_views
;
129 const int i
= u_bit_scan(&views
);
130 struct pipe_image_view
*pview
= &shs
->image
[i
].base
;
131 struct iris_resource
*res
= (void *) pview
->resource
;
133 if (res
->base
.target
!= PIPE_BUFFER
) {
134 if (consider_framebuffer
) {
135 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
136 res
, pview
->u
.tex
.level
, 1,
137 "as a shader image");
140 unsigned num_layers
=
141 pview
->u
.tex
.last_layer
- pview
->u
.tex
.first_layer
+ 1;
143 /* The data port doesn't understand any compression */
144 iris_resource_prepare_access(ice
, batch
, res
,
145 pview
->u
.tex
.level
, 1,
146 pview
->u
.tex
.first_layer
, num_layers
,
147 ISL_AUX_USAGE_NONE
, false);
150 iris_cache_flush_for_read(batch
, res
->bo
);
156 * \brief Resolve buffers before drawing.
158 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
159 * enabled depth texture, and flush the render cache for any dirty textures.
162 iris_predraw_resolve_inputs(struct iris_context
*ice
,
163 struct iris_batch
*batch
,
164 bool *draw_aux_buffer_disabled
,
165 gl_shader_stage stage
,
166 bool consider_framebuffer
)
168 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
169 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
171 uint64_t dirty
= (IRIS_DIRTY_BINDINGS_VS
<< stage
) |
172 (consider_framebuffer
? IRIS_DIRTY_BINDINGS_FS
: 0);
174 if (ice
->state
.dirty
& dirty
) {
175 resolve_sampler_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
176 consider_framebuffer
);
177 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
178 consider_framebuffer
);
185 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
186 struct iris_batch
*batch
,
187 bool *draw_aux_buffer_disabled
)
189 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
190 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
191 struct gen_device_info
*devinfo
= &screen
->devinfo
;
192 struct iris_uncompiled_shader
*ish
=
193 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
194 const nir_shader
*nir
= ish
->nir
;
196 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
197 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
200 struct iris_resource
*z_res
, *s_res
;
201 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
202 unsigned num_layers
=
203 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
206 iris_resource_prepare_depth(ice
, batch
, z_res
,
207 zs_surf
->u
.tex
.level
,
208 zs_surf
->u
.tex
.first_layer
,
210 iris_cache_flush_for_depth(batch
, z_res
->bo
);
214 iris_cache_flush_for_depth(batch
, s_res
->bo
);
219 if (devinfo
->gen
== 8 && nir
->info
.outputs_read
!= 0) {
220 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
221 if (cso_fb
->cbufs
[i
]) {
222 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
223 struct iris_resource
*res
= (void *) cso_fb
->cbufs
[i
]->texture
;
225 iris_resource_prepare_texture(ice
, batch
, res
, surf
->view
.format
,
226 surf
->view
.base_level
, 1,
227 surf
->view
.base_array_layer
,
228 surf
->view
.array_len
,
234 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
235 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
236 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
240 struct iris_resource
*res
= (void *) surf
->base
.texture
;
242 enum isl_aux_usage aux_usage
=
243 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
244 ice
->state
.blend_enables
& (1u << i
),
245 draw_aux_buffer_disabled
[i
]);
247 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
248 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
249 /* XXX: Need to track which bindings to make dirty */
250 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
253 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
254 surf
->view
.base_array_layer
,
255 surf
->view
.array_len
,
258 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
265 * \brief Call this after drawing to mark which buffers need resolving
267 * If the depth buffer was written to and if it has an accompanying HiZ
268 * buffer, then mark that it needs a depth resolve.
270 * If the color buffer is a multisample window system buffer, then
271 * mark that it needs a downsample.
273 * Also mark any render targets which will be textured as needing a render
277 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
278 struct iris_batch
*batch
)
280 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
282 // XXX: front buffer drawing?
284 bool may_have_resolved_depth
=
285 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
286 IRIS_DIRTY_WM_DEPTH_STENCIL
);
288 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
290 struct iris_resource
*z_res
, *s_res
;
291 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
292 unsigned num_layers
=
293 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
296 if (may_have_resolved_depth
) {
297 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
298 zs_surf
->u
.tex
.first_layer
, num_layers
,
299 ice
->state
.depth_writes_enabled
);
302 if (ice
->state
.depth_writes_enabled
)
303 iris_depth_cache_add_bo(batch
, z_res
->bo
);
307 if (may_have_resolved_depth
&& ice
->state
.stencil_writes_enabled
) {
308 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
309 zs_surf
->u
.tex
.first_layer
, num_layers
,
313 if (ice
->state
.stencil_writes_enabled
)
314 iris_depth_cache_add_bo(batch
, s_res
->bo
);
318 bool may_have_resolved_color
=
319 ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
);
321 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
322 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
326 struct iris_resource
*res
= (void *) surf
->base
.texture
;
327 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
329 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
,
332 if (may_have_resolved_color
) {
333 union pipe_surface_desc
*desc
= &surf
->base
.u
;
334 unsigned num_layers
=
335 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
336 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
337 desc
->tex
.first_layer
, num_layers
,
344 * Clear the cache-tracking sets.
347 iris_cache_sets_clear(struct iris_batch
*batch
)
349 hash_table_foreach(batch
->cache
.render
, render_entry
)
350 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
352 set_foreach(batch
->cache
.depth
, depth_entry
)
353 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
357 * Emits an appropriate flush for a BO if it has been rendered to within the
358 * same batchbuffer as a read that's about to be emitted.
360 * The GPU has separate, incoherent caches for the render cache and the
361 * sampler cache, along with other caches. Usually data in the different
362 * caches don't interact (e.g. we don't render to our driver-generated
363 * immediate constant data), but for render-to-texture in FBOs we definitely
364 * do. When a batchbuffer is flushed, the kernel will ensure that everything
365 * necessary is flushed before another use of that BO, but for reuse from
366 * different caches within a batchbuffer, it's all our responsibility.
369 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
371 iris_emit_pipe_control_flush(batch
,
372 "cache tracker: render-to-texture",
373 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
374 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
375 PIPE_CONTROL_CS_STALL
);
377 iris_emit_pipe_control_flush(batch
,
378 "cache tracker: render-to-texture",
379 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
380 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
382 iris_cache_sets_clear(batch
);
386 iris_cache_flush_for_read(struct iris_batch
*batch
,
389 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
390 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
391 iris_flush_depth_and_render_caches(batch
);
395 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
397 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
401 iris_cache_flush_for_render(struct iris_batch
*batch
,
403 enum isl_format format
,
404 enum isl_aux_usage aux_usage
)
406 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
407 iris_flush_depth_and_render_caches(batch
);
409 /* Check to see if this bo has been used by a previous rendering operation
410 * but with a different format or aux usage. If it has, flush the render
411 * cache so we ensure that it's only in there with one format or aux usage
414 * Even though it's not obvious, this can easily happen in practice.
415 * Suppose a client is blending on a surface with sRGB encode enabled on
416 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
417 * then disables sRGB decode and continues blending we will flip on
418 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
419 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
420 * that we have fragments in-flight which are rendering with UNORM+CCS_E
421 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
422 * same time and the pixel scoreboard and color blender are trying to sort
423 * it all out. This ends badly (i.e. GPU hangs).
425 * To date, we have never observed GPU hangs or even corruption to be
426 * associated with switching the format, only the aux usage. However,
427 * there are comments in various docs which indicate that the render cache
428 * isn't 100% resilient to format changes. We may as well be conservative
429 * and flush on format changes too. We can always relax this later if we
430 * find it to be a performance problem.
432 struct hash_entry
*entry
=
433 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
434 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
435 iris_flush_depth_and_render_caches(batch
);
439 iris_render_cache_add_bo(struct iris_batch
*batch
,
441 enum isl_format format
,
442 enum isl_aux_usage aux_usage
)
445 struct hash_entry
*entry
=
446 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
448 /* Otherwise, someone didn't do a flush_for_render and that would be
451 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
455 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
456 format_aux_tuple(format
, aux_usage
));
460 iris_cache_flush_for_depth(struct iris_batch
*batch
,
463 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
464 iris_flush_depth_and_render_caches(batch
);
468 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
470 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
474 iris_resolve_color(struct iris_context
*ice
,
475 struct iris_batch
*batch
,
476 struct iris_resource
*res
,
477 unsigned level
, unsigned layer
,
478 enum isl_aux_op resolve_op
)
480 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
482 struct blorp_surf surf
;
483 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
486 iris_batch_maybe_flush(batch
, 1500);
488 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
490 * "Any transition from any value in {Clear, Render, Resolve} to a
491 * different value in {Clear, Render, Resolve} requires end of pipe
494 * In other words, fast clear ops are not properly synchronized with
495 * other drawing. We need to use a PIPE_CONTROL to ensure that the
496 * contents of the previous draw hit the render target before we resolve
497 * and again afterwards to ensure that the resolve is complete before we
498 * do any more regular drawing.
500 iris_emit_end_of_pipe_sync(batch
, "color resolve: pre-flush",
501 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
503 struct blorp_batch blorp_batch
;
504 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
505 /* On Gen >= 12, Stencil buffer with lossless compression needs to be
506 * resolve with WM_HZ_OP packet.
508 if (isl_surf_usage_is_stencil(res
->surf
.usage
)) {
509 blorp_hiz_stencil_op(&blorp_batch
, &surf
, level
, layer
,
512 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
513 isl_format_srgb_to_linear(res
->surf
.format
),
516 blorp_batch_finish(&blorp_batch
);
518 /* See comment above */
519 iris_emit_end_of_pipe_sync(batch
, "color resolve: post-flush",
520 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
524 iris_mcs_partial_resolve(struct iris_context
*ice
,
525 struct iris_batch
*batch
,
526 struct iris_resource
*res
,
527 uint32_t start_layer
,
530 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
531 //start_layer, start_layer + num_layers - 1);
533 assert(isl_aux_usage_has_mcs(res
->aux
.usage
));
535 struct blorp_surf surf
;
536 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
539 struct blorp_batch blorp_batch
;
540 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
541 blorp_mcs_partial_resolve(&blorp_batch
, &surf
,
542 isl_format_srgb_to_linear(res
->surf
.format
),
543 start_layer
, num_layers
);
544 blorp_batch_finish(&blorp_batch
);
549 * Return true if the format that will be used to access the resource is
550 * CCS_E-compatible with the resource's linear/non-sRGB format.
552 * Why use the linear format? Well, although the resourcemay be specified
553 * with an sRGB format, the usage of that color space/format can be toggled.
554 * Since our HW tends to support more linear formats than sRGB ones, we use
555 * this format variant for check for CCS_E compatibility.
558 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
559 const struct iris_resource
*res
,
560 enum isl_format access_format
)
562 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
564 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
565 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
569 sample_with_depth_aux(const struct gen_device_info
*devinfo
,
570 const struct iris_resource
*res
)
572 switch (res
->aux
.usage
) {
573 case ISL_AUX_USAGE_HIZ
:
574 if (devinfo
->has_sample_with_hiz
)
577 case ISL_AUX_USAGE_HIZ_CCS
:
578 /* Write through mode must have been enabled for prior writes. */
579 if (isl_surf_supports_hiz_ccs_wt(devinfo
, &res
->surf
, res
->aux
.usage
))
586 /* It seems the hardware won't fallback to the depth buffer if some of the
587 * mipmap levels aren't available in the HiZ buffer. So we need all levels
588 * of the texture to be HiZ enabled.
590 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
591 if (!iris_resource_level_has_hiz(res
, level
))
595 /* If compressed multisampling is enabled, then we use it for the auxiliary
598 * From the BDW PRM (Volume 2d: Command Reference: Structures
599 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
601 * "If this field is set to AUX_HIZ, Number of Multisamples must be
602 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
604 * There is no such blurb for 1D textures, but there is sufficient evidence
605 * that this is broken on SKL+.
607 // XXX: i965 disables this for arrays too, is that reasonable?
608 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
612 * Perform a HiZ or depth resolve operation.
614 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
615 * PRM, Volume 1, Part 2:
616 * - 7.5.3.1 Depth Buffer Clear
617 * - 7.5.3.2 Depth Buffer Resolve
618 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
621 iris_hiz_exec(struct iris_context
*ice
,
622 struct iris_batch
*batch
,
623 struct iris_resource
*res
,
624 unsigned int level
, unsigned int start_layer
,
625 unsigned int num_layers
, enum isl_aux_op op
,
626 bool update_clear_depth
)
628 assert(iris_resource_level_has_hiz(res
, level
));
629 assert(op
!= ISL_AUX_OP_NONE
);
630 UNUSED
const char *name
= NULL
;
633 case ISL_AUX_OP_FULL_RESOLVE
:
634 name
= "depth resolve";
636 case ISL_AUX_OP_AMBIGUATE
:
637 name
= "hiz ambiguate";
639 case ISL_AUX_OP_FAST_CLEAR
:
640 name
= "depth clear";
642 case ISL_AUX_OP_PARTIAL_RESOLVE
:
643 case ISL_AUX_OP_NONE
:
644 unreachable("Invalid HiZ op");
647 //DBG("%s %s to mt %p level %d layers %d-%d\n",
648 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
650 /* The following stalls and flushes are only documented to be required
651 * for HiZ clear operations. However, they also seem to be required for
652 * resolve operations.
654 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
656 * "If other rendering operations have preceded this clear, a
657 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
658 * enabled must be issued before the rectangle primitive used for
659 * the depth buffer clear operation."
661 * Same applies for Gen8 and Gen9.
663 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
664 * PIPE_CONTROL, Depth Cache Flush Enable:
666 * "This bit must not be set when Depth Stall Enable bit is set in
669 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
671 * Therefore issue two pipe control flushes, one for cache flush and
672 * another for depth stall.
674 iris_emit_pipe_control_flush(batch
,
675 "hiz op: pre-flushes (1/2)",
676 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
677 PIPE_CONTROL_CS_STALL
);
679 iris_emit_pipe_control_flush(batch
, "hiz op: pre-flushes (2/2)",
680 PIPE_CONTROL_DEPTH_STALL
);
682 assert(isl_aux_usage_has_hiz(res
->aux
.usage
) && res
->aux
.bo
);
684 iris_batch_maybe_flush(batch
, 1500);
686 struct blorp_surf surf
;
687 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
,
688 res
->aux
.usage
, level
, true);
690 struct blorp_batch blorp_batch
;
691 enum blorp_batch_flags flags
= 0;
692 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
693 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
694 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
695 blorp_batch_finish(&blorp_batch
);
697 /* The following stalls and flushes are only documented to be required
698 * for HiZ clear operations. However, they also seem to be required for
699 * resolve operations.
701 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
703 * "Depth buffer clear pass using any of the methods (WM_STATE,
704 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
705 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
706 * "set" before starting to render. DepthStall and DepthFlush are
707 * not needed between consecutive depth clear passes nor is it
708 * required if the depth clear pass was done with
709 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
711 * TODO: Such as the spec says, this could be conditional.
713 iris_emit_pipe_control_flush(batch
,
714 "hiz op: post flush",
715 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
716 PIPE_CONTROL_DEPTH_STALL
);
720 * Does the resource's slice have hiz enabled?
723 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
725 iris_resource_check_level_layer(res
, level
, 0);
726 return res
->aux
.has_hiz
& 1 << level
;
729 /** \brief Assert that the level and layer are valid for the resource. */
731 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
732 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
734 assert(level
< res
->surf
.levels
);
735 assert(layer
< util_num_layers(&res
->base
, level
));
738 static inline uint32_t
739 miptree_level_range_length(const struct iris_resource
*res
,
740 uint32_t start_level
, uint32_t num_levels
)
742 assert(start_level
< res
->surf
.levels
);
744 if (num_levels
== INTEL_REMAINING_LAYERS
)
745 num_levels
= res
->surf
.levels
;
747 /* Check for overflow */
748 assert(start_level
+ num_levels
>= start_level
);
749 assert(start_level
+ num_levels
<= res
->surf
.levels
);
754 static inline uint32_t
755 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
756 uint32_t start_layer
, uint32_t num_layers
)
758 assert(level
<= res
->base
.last_level
);
760 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
761 assert(start_layer
< total_num_layers
);
762 if (num_layers
== INTEL_REMAINING_LAYERS
)
763 num_layers
= total_num_layers
- start_layer
;
764 /* Check for overflow */
765 assert(start_layer
+ num_layers
>= start_layer
);
766 assert(start_layer
+ num_layers
<= total_num_layers
);
772 iris_has_color_unresolved(const struct iris_resource
*res
,
773 unsigned start_level
, unsigned num_levels
,
774 unsigned start_layer
, unsigned num_layers
)
779 /* Clamp the level range to fit the resource */
780 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
782 for (uint32_t l
= 0; l
< num_levels
; l
++) {
783 const uint32_t level
= start_level
+ l
;
784 const uint32_t level_layers
=
785 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
786 for (unsigned a
= 0; a
< level_layers
; a
++) {
787 enum isl_aux_state aux_state
=
788 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
789 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
790 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
798 static enum isl_aux_op
799 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
800 enum isl_aux_usage aux_usage
,
801 bool fast_clear_supported
)
803 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
805 const bool ccs_supported
=
806 (aux_usage
== ISL_AUX_USAGE_CCS_D
) && fast_clear_supported
;
809 case ISL_AUX_STATE_CLEAR
:
810 case ISL_AUX_STATE_PARTIAL_CLEAR
:
812 return ISL_AUX_OP_FULL_RESOLVE
;
814 return ISL_AUX_OP_NONE
;
816 case ISL_AUX_STATE_PASS_THROUGH
:
817 return ISL_AUX_OP_NONE
;
819 case ISL_AUX_STATE_RESOLVED
:
820 case ISL_AUX_STATE_AUX_INVALID
:
821 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
822 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
826 unreachable("Invalid aux state for CCS_D");
829 static enum isl_aux_op
830 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
831 enum isl_aux_usage aux_usage
,
832 bool fast_clear_supported
)
834 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
835 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
836 aux_usage
== ISL_AUX_USAGE_CCS_D
||
837 aux_usage
== ISL_AUX_USAGE_CCS_E
);
840 case ISL_AUX_STATE_CLEAR
:
841 case ISL_AUX_STATE_PARTIAL_CLEAR
:
842 if (fast_clear_supported
)
843 return ISL_AUX_OP_NONE
;
844 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
845 return ISL_AUX_OP_PARTIAL_RESOLVE
;
847 return ISL_AUX_OP_FULL_RESOLVE
;
849 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
850 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
851 return ISL_AUX_OP_FULL_RESOLVE
;
852 else if (!fast_clear_supported
)
853 return ISL_AUX_OP_PARTIAL_RESOLVE
;
855 return ISL_AUX_OP_NONE
;
857 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
858 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
859 return ISL_AUX_OP_FULL_RESOLVE
;
861 return ISL_AUX_OP_NONE
;
863 case ISL_AUX_STATE_PASS_THROUGH
:
864 return ISL_AUX_OP_NONE
;
866 case ISL_AUX_STATE_RESOLVED
:
867 case ISL_AUX_STATE_AUX_INVALID
:
871 unreachable("Invalid aux state for CCS_E");
875 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
876 struct iris_batch
*batch
,
877 struct iris_resource
*res
,
878 uint32_t level
, uint32_t layer
,
879 enum isl_aux_usage aux_usage
,
880 bool fast_clear_supported
)
882 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
884 enum isl_aux_op resolve_op
;
885 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
886 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
887 fast_clear_supported
);
889 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
890 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
891 fast_clear_supported
);
894 if (resolve_op
!= ISL_AUX_OP_NONE
) {
895 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
897 switch (resolve_op
) {
898 case ISL_AUX_OP_FULL_RESOLVE
:
899 /* The CCS full resolve operation destroys the CCS and sets it to the
900 * pass-through state. (You can also think of this as being both a
901 * resolve and an ambiguate in one operation.)
903 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
904 ISL_AUX_STATE_PASS_THROUGH
);
907 case ISL_AUX_OP_PARTIAL_RESOLVE
:
908 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
909 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
913 unreachable("Invalid resolve op");
919 iris_resource_finish_ccs_write(struct iris_context
*ice
,
920 struct iris_resource
*res
,
921 uint32_t level
, uint32_t layer
,
922 enum isl_aux_usage aux_usage
)
924 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
925 aux_usage
== ISL_AUX_USAGE_CCS_D
||
926 aux_usage
== ISL_AUX_USAGE_CCS_E
);
928 enum isl_aux_state aux_state
=
929 iris_resource_get_aux_state(res
, level
, layer
);
931 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
933 case ISL_AUX_STATE_CLEAR
:
934 case ISL_AUX_STATE_PARTIAL_CLEAR
:
935 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
936 aux_usage
== ISL_AUX_USAGE_CCS_D
);
938 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
939 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
940 ISL_AUX_STATE_COMPRESSED_CLEAR
);
941 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
942 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
943 ISL_AUX_STATE_PARTIAL_CLEAR
);
947 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
948 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
949 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
950 break; /* Nothing to do */
952 case ISL_AUX_STATE_PASS_THROUGH
:
953 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
954 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
955 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
961 case ISL_AUX_STATE_RESOLVED
:
962 case ISL_AUX_STATE_AUX_INVALID
:
963 unreachable("Invalid aux state for CCS_E");
966 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
967 /* CCS_D is a bit simpler */
969 case ISL_AUX_STATE_CLEAR
:
970 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
971 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
972 ISL_AUX_STATE_PARTIAL_CLEAR
);
975 case ISL_AUX_STATE_PARTIAL_CLEAR
:
976 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
977 break; /* Nothing to do */
979 case ISL_AUX_STATE_PASS_THROUGH
:
983 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
984 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
985 case ISL_AUX_STATE_RESOLVED
:
986 case ISL_AUX_STATE_AUX_INVALID
:
987 unreachable("Invalid aux state for CCS_D");
993 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
994 struct iris_batch
*batch
,
995 struct iris_resource
*res
,
997 enum isl_aux_usage aux_usage
,
998 bool fast_clear_supported
)
1000 assert(isl_aux_usage_has_mcs(aux_usage
));
1002 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
1003 case ISL_AUX_STATE_CLEAR
:
1004 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1005 if (!fast_clear_supported
) {
1006 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
1007 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
1008 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1012 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1013 break; /* Nothing to do */
1015 case ISL_AUX_STATE_RESOLVED
:
1016 case ISL_AUX_STATE_PASS_THROUGH
:
1017 case ISL_AUX_STATE_AUX_INVALID
:
1018 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1019 unreachable("Invalid aux state for MCS");
1024 iris_resource_finish_mcs_write(struct iris_context
*ice
,
1025 struct iris_resource
*res
,
1027 enum isl_aux_usage aux_usage
)
1029 assert(isl_aux_usage_has_mcs(aux_usage
));
1031 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
1032 case ISL_AUX_STATE_CLEAR
:
1033 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
1034 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1037 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1038 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1039 break; /* Nothing to do */
1041 case ISL_AUX_STATE_RESOLVED
:
1042 case ISL_AUX_STATE_PASS_THROUGH
:
1043 case ISL_AUX_STATE_AUX_INVALID
:
1044 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1045 unreachable("Invalid aux state for MCS");
1050 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
1051 struct iris_batch
*batch
,
1052 struct iris_resource
*res
,
1053 uint32_t level
, uint32_t layer
,
1054 enum isl_aux_usage aux_usage
,
1055 bool fast_clear_supported
)
1057 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1058 aux_usage
== ISL_AUX_USAGE_HIZ
||
1059 aux_usage
== ISL_AUX_USAGE_HIZ_CCS
||
1060 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1062 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
1063 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1064 case ISL_AUX_STATE_CLEAR
:
1065 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1066 if (aux_usage
== ISL_AUX_USAGE_NONE
|| !fast_clear_supported
)
1067 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1070 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1071 if (aux_usage
== ISL_AUX_USAGE_NONE
)
1072 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1075 case ISL_AUX_STATE_PASS_THROUGH
:
1076 case ISL_AUX_STATE_RESOLVED
:
1079 case ISL_AUX_STATE_AUX_INVALID
:
1080 if (aux_usage
!= ISL_AUX_USAGE_NONE
)
1081 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
1084 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1085 unreachable("Invalid HiZ state");
1088 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1089 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
, false);
1092 case ISL_AUX_OP_FULL_RESOLVE
:
1093 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1094 ISL_AUX_STATE_RESOLVED
);
1097 case ISL_AUX_OP_AMBIGUATE
:
1098 /* The HiZ resolve operation is actually an ambiguate */
1099 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1100 ISL_AUX_STATE_PASS_THROUGH
);
1104 unreachable("Invalid HiZ op");
1110 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1111 struct iris_resource
*res
,
1112 uint32_t level
, uint32_t layer
,
1113 enum isl_aux_usage aux_usage
)
1115 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1116 isl_aux_usage_has_hiz(aux_usage
));
1118 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1119 case ISL_AUX_STATE_CLEAR
:
1120 assert(isl_aux_usage_has_hiz(aux_usage
));
1121 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1122 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1125 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1126 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1127 assert(isl_aux_usage_has_hiz(aux_usage
));
1128 break; /* Nothing to do */
1130 case ISL_AUX_STATE_RESOLVED
:
1131 if (isl_aux_usage_has_hiz(aux_usage
)) {
1132 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1133 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1135 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1136 ISL_AUX_STATE_AUX_INVALID
);
1140 case ISL_AUX_STATE_PASS_THROUGH
:
1141 if (isl_aux_usage_has_hiz(aux_usage
)) {
1142 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1143 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1147 case ISL_AUX_STATE_AUX_INVALID
:
1148 assert(!isl_aux_usage_has_hiz(aux_usage
));
1151 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1152 unreachable("Invalid HiZ state");
1157 iris_resource_prepare_access(struct iris_context
*ice
,
1158 struct iris_batch
*batch
,
1159 struct iris_resource
*res
,
1160 uint32_t start_level
, uint32_t num_levels
,
1161 uint32_t start_layer
, uint32_t num_layers
,
1162 enum isl_aux_usage aux_usage
,
1163 bool fast_clear_supported
)
1165 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1167 switch (res
->aux
.usage
) {
1168 case ISL_AUX_USAGE_NONE
:
1172 case ISL_AUX_USAGE_MCS
:
1173 case ISL_AUX_USAGE_MCS_CCS
:
1174 assert(start_level
== 0 && num_levels
== 1);
1175 const uint32_t level_layers
=
1176 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1177 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1178 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1179 aux_usage
, fast_clear_supported
);
1183 case ISL_AUX_USAGE_CCS_D
:
1184 case ISL_AUX_USAGE_CCS_E
:
1185 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1186 const uint32_t level
= start_level
+ l
;
1187 const uint32_t level_layers
=
1188 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1189 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1190 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1192 aux_usage
, fast_clear_supported
);
1197 case ISL_AUX_USAGE_HIZ
:
1198 case ISL_AUX_USAGE_HIZ_CCS
:
1199 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1200 const uint32_t level
= start_level
+ l
;
1201 if (!iris_resource_level_has_hiz(res
, level
))
1204 const uint32_t level_layers
=
1205 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1206 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1207 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1208 start_layer
+ a
, aux_usage
,
1209 fast_clear_supported
);
1215 unreachable("Invalid aux usage");
1220 iris_resource_finish_write(struct iris_context
*ice
,
1221 struct iris_resource
*res
, uint32_t level
,
1222 uint32_t start_layer
, uint32_t num_layers
,
1223 enum isl_aux_usage aux_usage
)
1225 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1227 switch (res
->aux
.usage
) {
1228 case ISL_AUX_USAGE_NONE
:
1231 case ISL_AUX_USAGE_MCS
:
1232 case ISL_AUX_USAGE_MCS_CCS
:
1233 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1234 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1239 case ISL_AUX_USAGE_CCS_D
:
1240 case ISL_AUX_USAGE_CCS_E
:
1241 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1242 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1247 case ISL_AUX_USAGE_HIZ
:
1248 case ISL_AUX_USAGE_HIZ_CCS
:
1249 if (!iris_resource_level_has_hiz(res
, level
))
1252 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1253 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1259 unreachable("Invavlid aux usage");
1264 iris_resource_get_aux_state(const struct iris_resource
*res
,
1265 uint32_t level
, uint32_t layer
)
1267 iris_resource_check_level_layer(res
, level
, layer
);
1269 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1270 assert(iris_resource_level_has_hiz(res
, level
));
1272 assert(res
->surf
.samples
== 1 ||
1273 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1276 return res
->aux
.state
[level
][layer
];
1280 iris_resource_set_aux_state(struct iris_context
*ice
,
1281 struct iris_resource
*res
, uint32_t level
,
1282 uint32_t start_layer
, uint32_t num_layers
,
1283 enum isl_aux_state aux_state
)
1285 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1287 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1288 assert(iris_resource_level_has_hiz(res
, level
));
1290 assert(res
->surf
.samples
== 1 ||
1291 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1294 for (unsigned a
= 0; a
< num_layers
; a
++) {
1295 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1296 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1297 /* XXX: Need to track which bindings to make dirty */
1298 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1303 /* On Gen9 color buffers may be compressed by the hardware (lossless
1304 * compression). There are, however, format restrictions and care needs to be
1305 * taken that the sampler engine is capable for re-interpreting a buffer with
1306 * format different the buffer was originally written with.
1308 * For example, SRGB formats are not compressible and the sampler engine isn't
1309 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1310 * color buffer needs to be resolved so that the sampling surface can be
1311 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1315 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1316 struct pipe_debug_callback
*dbg
,
1317 const struct iris_resource
*res
,
1318 enum isl_format view_format
)
1320 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1323 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1324 const struct isl_format_layout
*res_fmtl
=
1325 isl_format_get_layout(res
->surf
.format
);
1326 const struct isl_format_layout
*view_fmtl
=
1327 isl_format_get_layout(view_format
);
1329 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1330 view_fmtl
->name
, res_fmtl
->name
);
1339 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1340 const struct iris_resource
*res
,
1341 enum isl_format view_format
,
1342 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1344 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1345 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1347 assert(devinfo
->gen
== 9 || astc5x5_wa_bits
== 0);
1349 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
1350 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
1353 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
1354 res
->aux
.usage
!= ISL_AUX_USAGE_MCS
)
1355 return ISL_AUX_USAGE_NONE
;
1357 switch (res
->aux
.usage
) {
1358 case ISL_AUX_USAGE_HIZ
:
1359 if (sample_with_depth_aux(devinfo
, res
))
1360 return ISL_AUX_USAGE_HIZ
;
1363 case ISL_AUX_USAGE_HIZ_CCS
:
1364 if (sample_with_depth_aux(devinfo
, res
))
1365 return ISL_AUX_USAGE_CCS_E
;
1368 case ISL_AUX_USAGE_MCS
:
1369 case ISL_AUX_USAGE_MCS_CCS
:
1370 return res
->aux
.usage
;
1372 case ISL_AUX_USAGE_CCS_D
:
1373 case ISL_AUX_USAGE_CCS_E
:
1374 /* If we don't have any unresolved color, report an aux usage of
1375 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1376 * aux surface and we can save some bandwidth.
1378 if (!iris_has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1379 0, INTEL_REMAINING_LAYERS
))
1380 return ISL_AUX_USAGE_NONE
;
1382 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1383 return ISL_AUX_USAGE_CCS_E
;
1390 return ISL_AUX_USAGE_NONE
;
1394 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1396 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1397 * values so sRGB curve application was a no-op for all fast-clearable
1400 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1401 * values, the hardware interprets the floats, not as what would be
1402 * returned from the sampler (or written by the shader), but as being
1403 * between format conversion and sRGB curve application. This means that
1404 * we can switch between sRGB and UNORM without having to whack the clear
1407 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1411 iris_resource_prepare_texture(struct iris_context
*ice
,
1412 struct iris_batch
*batch
,
1413 struct iris_resource
*res
,
1414 enum isl_format view_format
,
1415 uint32_t start_level
, uint32_t num_levels
,
1416 uint32_t start_layer
, uint32_t num_layers
,
1417 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1419 enum isl_aux_usage aux_usage
=
1420 iris_resource_texture_aux_usage(ice
, res
, view_format
, astc5x5_wa_bits
);
1422 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1424 /* Clear color is specified as ints or floats and the conversion is done by
1425 * the sampler. If we have a texture view, we would have to perform the
1426 * clear color conversion manually. Just disable clear color.
1428 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1429 clear_supported
= false;
1431 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1432 start_layer
, num_layers
,
1433 aux_usage
, clear_supported
);
1437 iris_resource_render_aux_usage(struct iris_context
*ice
,
1438 struct iris_resource
*res
,
1439 enum isl_format render_format
,
1441 bool draw_aux_disabled
)
1443 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1444 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1446 if (draw_aux_disabled
)
1447 return ISL_AUX_USAGE_NONE
;
1449 switch (res
->aux
.usage
) {
1450 case ISL_AUX_USAGE_MCS
:
1451 case ISL_AUX_USAGE_MCS_CCS
:
1452 return res
->aux
.usage
;
1454 case ISL_AUX_USAGE_CCS_D
:
1455 case ISL_AUX_USAGE_CCS_E
:
1456 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1457 * formats. However, there are issues with blending where it doesn't
1458 * properly apply the sRGB curve to the clear color when blending.
1460 if (devinfo
->gen
>= 9 && blend_enabled
&&
1461 isl_format_is_srgb(render_format
) &&
1462 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1463 return ISL_AUX_USAGE_NONE
;
1465 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1466 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1467 return ISL_AUX_USAGE_CCS_E
;
1469 /* Otherwise, we try to fall back to CCS_D */
1470 if (isl_format_supports_ccs_d(devinfo
, render_format
))
1471 return ISL_AUX_USAGE_CCS_D
;
1474 return ISL_AUX_USAGE_NONE
;
1479 iris_resource_prepare_render(struct iris_context
*ice
,
1480 struct iris_batch
*batch
,
1481 struct iris_resource
*res
, uint32_t level
,
1482 uint32_t start_layer
, uint32_t layer_count
,
1483 enum isl_aux_usage aux_usage
)
1485 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1486 layer_count
, aux_usage
,
1487 aux_usage
!= ISL_AUX_USAGE_NONE
);
1491 iris_resource_finish_render(struct iris_context
*ice
,
1492 struct iris_resource
*res
, uint32_t level
,
1493 uint32_t start_layer
, uint32_t layer_count
,
1494 enum isl_aux_usage aux_usage
)
1496 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1501 iris_resource_prepare_depth(struct iris_context
*ice
,
1502 struct iris_batch
*batch
,
1503 struct iris_resource
*res
, uint32_t level
,
1504 uint32_t start_layer
, uint32_t layer_count
)
1506 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1507 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1511 iris_resource_finish_depth(struct iris_context
*ice
,
1512 struct iris_resource
*res
, uint32_t level
,
1513 uint32_t start_layer
, uint32_t layer_count
,
1516 if (depth_written
) {
1517 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,