2 * Copyright © 2017 Intel Corporation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
39 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
40 * or shader image. This causes a self-dependency, where both rendering
41 * and sampling may concurrently read or write the CCS buffer, causing
45 disable_rb_aux_buffer(struct iris_context
*ice
,
46 bool *draw_aux_buffer_disabled
,
47 struct iris_resource
*tex_res
,
48 unsigned min_level
, unsigned num_levels
,
51 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
54 /* We only need to worry about color compression and fast clears. */
55 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
56 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
59 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
60 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
64 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
66 if (rb_res
->bo
== tex_res
->bo
&&
67 surf
->base
.u
.tex
.level
>= min_level
&&
68 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
69 found
= draw_aux_buffer_disabled
[i
] = true;
75 "Disabling CCS because a renderbuffer is also bound %s.\n",
83 resolve_sampler_views(struct iris_context
*ice
,
84 struct iris_batch
*batch
,
85 struct iris_shader_state
*shs
,
86 bool *draw_aux_buffer_disabled
,
87 bool consider_framebuffer
)
89 uint32_t views
= shs
->bound_sampler_views
;
91 unsigned astc5x5_wa_bits
= 0; // XXX: actual tracking
94 const int i
= u_bit_scan(&views
);
95 struct iris_sampler_view
*isv
= shs
->textures
[i
];
96 struct iris_resource
*res
= (void *) isv
->base
.texture
;
98 if (res
->base
.target
!= PIPE_BUFFER
) {
99 if (consider_framebuffer
) {
100 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
101 res
, isv
->view
.base_level
, isv
->view
.levels
,
105 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
106 isv
->view
.base_level
, isv
->view
.levels
,
107 isv
->view
.base_array_layer
,
112 iris_cache_flush_for_read(batch
, res
->bo
);
117 resolve_image_views(struct iris_context
*ice
,
118 struct iris_batch
*batch
,
119 struct iris_shader_state
*shs
,
120 bool *draw_aux_buffer_disabled
,
121 bool consider_framebuffer
)
123 uint32_t views
= shs
->bound_image_views
;
126 const int i
= u_bit_scan(&views
);
127 struct iris_resource
*res
= (void *) shs
->image
[i
].res
;
129 if (res
->base
.target
!= PIPE_BUFFER
) {
130 if (consider_framebuffer
) {
131 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
132 res
, 0, ~0, "as a shader image");
135 iris_resource_prepare_image(ice
, batch
, res
);
138 iris_cache_flush_for_read(batch
, res
->bo
);
144 * \brief Resolve buffers before drawing.
146 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
147 * enabled depth texture, and flush the render cache for any dirty textures.
150 iris_predraw_resolve_inputs(struct iris_context
*ice
,
151 struct iris_batch
*batch
,
152 bool *draw_aux_buffer_disabled
,
153 gl_shader_stage stage
,
154 bool consider_framebuffer
)
156 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
158 uint64_t dirty
= (IRIS_DIRTY_BINDINGS_VS
<< stage
) |
159 (consider_framebuffer
? IRIS_DIRTY_BINDINGS_FS
: 0);
161 if (ice
->state
.dirty
& dirty
) {
162 resolve_sampler_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
163 consider_framebuffer
);
164 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
165 consider_framebuffer
);
172 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
173 struct iris_batch
*batch
,
174 bool *draw_aux_buffer_disabled
)
176 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
178 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
179 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
182 struct iris_resource
*z_res
, *s_res
;
183 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
184 unsigned num_layers
=
185 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
188 iris_resource_prepare_depth(ice
, batch
, z_res
,
189 zs_surf
->u
.tex
.level
,
190 zs_surf
->u
.tex
.first_layer
,
192 iris_cache_flush_for_depth(batch
, z_res
->bo
);
196 iris_cache_flush_for_depth(batch
, s_res
->bo
);
201 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
202 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
203 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
207 struct iris_resource
*res
= (void *) surf
->base
.texture
;
209 enum isl_aux_usage aux_usage
=
210 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
211 ice
->state
.blend_enables
& (1u << i
),
212 draw_aux_buffer_disabled
[i
]);
214 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
215 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
216 /* XXX: Need to track which bindings to make dirty */
217 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
220 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
221 surf
->view
.base_array_layer
,
222 surf
->view
.array_len
,
225 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
232 * \brief Call this after drawing to mark which buffers need resolving
234 * If the depth buffer was written to and if it has an accompanying HiZ
235 * buffer, then mark that it needs a depth resolve.
237 * If the color buffer is a multisample window system buffer, then
238 * mark that it needs a downsample.
240 * Also mark any render targets which will be textured as needing a render
244 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
245 struct iris_batch
*batch
)
247 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
249 // XXX: front buffer drawing?
251 bool may_have_resolved_depth
=
252 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
253 IRIS_DIRTY_WM_DEPTH_STENCIL
);
255 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
257 struct iris_resource
*z_res
, *s_res
;
258 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
259 unsigned num_layers
=
260 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
263 if (may_have_resolved_depth
) {
264 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
265 zs_surf
->u
.tex
.first_layer
, num_layers
,
266 ice
->state
.depth_writes_enabled
);
269 if (ice
->state
.depth_writes_enabled
)
270 iris_depth_cache_add_bo(batch
, z_res
->bo
);
274 if (may_have_resolved_depth
) {
275 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
276 zs_surf
->u
.tex
.first_layer
, num_layers
,
280 if (ice
->state
.stencil_writes_enabled
)
281 iris_depth_cache_add_bo(batch
, s_res
->bo
);
285 bool may_have_resolved_color
=
286 ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
);
288 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
289 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
293 struct iris_resource
*res
= (void *) surf
->base
.texture
;
294 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
296 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
,
299 if (may_have_resolved_color
) {
300 union pipe_surface_desc
*desc
= &surf
->base
.u
;
301 unsigned num_layers
=
302 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
303 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
304 desc
->tex
.first_layer
, num_layers
,
311 * Clear the cache-tracking sets.
314 iris_cache_sets_clear(struct iris_batch
*batch
)
316 hash_table_foreach(batch
->cache
.render
, render_entry
)
317 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
319 set_foreach(batch
->cache
.depth
, depth_entry
)
320 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
324 * Emits an appropriate flush for a BO if it has been rendered to within the
325 * same batchbuffer as a read that's about to be emitted.
327 * The GPU has separate, incoherent caches for the render cache and the
328 * sampler cache, along with other caches. Usually data in the different
329 * caches don't interact (e.g. we don't render to our driver-generated
330 * immediate constant data), but for render-to-texture in FBOs we definitely
331 * do. When a batchbuffer is flushed, the kernel will ensure that everything
332 * necessary is flushed before another use of that BO, but for reuse from
333 * different caches within a batchbuffer, it's all our responsibility.
336 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
338 iris_emit_pipe_control_flush(batch
,
339 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
340 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
341 PIPE_CONTROL_CS_STALL
);
343 iris_emit_pipe_control_flush(batch
,
344 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
345 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
347 iris_cache_sets_clear(batch
);
351 iris_cache_flush_for_read(struct iris_batch
*batch
,
354 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
355 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
356 iris_flush_depth_and_render_caches(batch
);
360 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
362 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
366 iris_cache_flush_for_render(struct iris_batch
*batch
,
368 enum isl_format format
,
369 enum isl_aux_usage aux_usage
)
371 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
372 iris_flush_depth_and_render_caches(batch
);
374 /* Check to see if this bo has been used by a previous rendering operation
375 * but with a different format or aux usage. If it has, flush the render
376 * cache so we ensure that it's only in there with one format or aux usage
379 * Even though it's not obvious, this can easily happen in practice.
380 * Suppose a client is blending on a surface with sRGB encode enabled on
381 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
382 * then disables sRGB decode and continues blending we will flip on
383 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
384 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
385 * that we have fragments in-flight which are rendering with UNORM+CCS_E
386 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
387 * same time and the pixel scoreboard and color blender are trying to sort
388 * it all out. This ends badly (i.e. GPU hangs).
390 * To date, we have never observed GPU hangs or even corruption to be
391 * associated with switching the format, only the aux usage. However,
392 * there are comments in various docs which indicate that the render cache
393 * isn't 100% resilient to format changes. We may as well be conservative
394 * and flush on format changes too. We can always relax this later if we
395 * find it to be a performance problem.
397 struct hash_entry
*entry
=
398 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
399 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
400 iris_flush_depth_and_render_caches(batch
);
404 iris_render_cache_add_bo(struct iris_batch
*batch
,
406 enum isl_format format
,
407 enum isl_aux_usage aux_usage
)
410 struct hash_entry
*entry
=
411 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
413 /* Otherwise, someone didn't do a flush_for_render and that would be
416 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
420 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
421 format_aux_tuple(format
, aux_usage
));
425 iris_cache_flush_for_depth(struct iris_batch
*batch
,
428 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
429 iris_flush_depth_and_render_caches(batch
);
433 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
435 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
439 iris_resolve_color(struct iris_context
*ice
,
440 struct iris_batch
*batch
,
441 struct iris_resource
*res
,
442 unsigned level
, unsigned layer
,
443 enum isl_aux_op resolve_op
)
445 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
447 struct blorp_surf surf
;
448 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
451 iris_batch_maybe_flush(batch
, 1500);
453 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
455 * "Any transition from any value in {Clear, Render, Resolve} to a
456 * different value in {Clear, Render, Resolve} requires end of pipe
459 * In other words, fast clear ops are not properly synchronized with
460 * other drawing. We need to use a PIPE_CONTROL to ensure that the
461 * contents of the previous draw hit the render target before we resolve
462 * and again afterwards to ensure that the resolve is complete before we
463 * do any more regular drawing.
465 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
467 struct blorp_batch blorp_batch
;
468 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
469 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
470 isl_format_srgb_to_linear(res
->surf
.format
),
472 blorp_batch_finish(&blorp_batch
);
474 /* See comment above */
475 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
479 iris_mcs_partial_resolve(struct iris_context
*ice
,
480 struct iris_batch
*batch
,
481 struct iris_resource
*res
,
482 uint32_t start_layer
,
485 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
486 //start_layer, start_layer + num_layers - 1);
488 assert(res
->aux
.usage
== ISL_AUX_USAGE_MCS
);
490 struct blorp_surf surf
;
491 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
494 struct blorp_batch blorp_batch
;
495 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
496 blorp_mcs_partial_resolve(&blorp_batch
, &surf
, res
->surf
.format
,
497 start_layer
, num_layers
);
498 blorp_batch_finish(&blorp_batch
);
503 * Return true if the format that will be used to access the resource is
504 * CCS_E-compatible with the resource's linear/non-sRGB format.
506 * Why use the linear format? Well, although the resourcemay be specified
507 * with an sRGB format, the usage of that color space/format can be toggled.
508 * Since our HW tends to support more linear formats than sRGB ones, we use
509 * this format variant for check for CCS_E compatibility.
512 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
513 const struct iris_resource
*res
,
514 enum isl_format access_format
)
516 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
518 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
519 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
523 sample_with_hiz(const struct gen_device_info
*devinfo
,
524 const struct iris_resource
*res
)
526 if (!devinfo
->has_sample_with_hiz
)
529 if (res
->aux
.usage
!= ISL_AUX_USAGE_HIZ
)
532 /* It seems the hardware won't fallback to the depth buffer if some of the
533 * mipmap levels aren't available in the HiZ buffer. So we need all levels
534 * of the texture to be HiZ enabled.
536 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
537 if (!iris_resource_level_has_hiz(res
, level
))
541 /* If compressed multisampling is enabled, then we use it for the auxiliary
544 * From the BDW PRM (Volume 2d: Command Reference: Structures
545 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
547 * "If this field is set to AUX_HIZ, Number of Multisamples must be
548 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
550 * There is no such blurb for 1D textures, but there is sufficient evidence
551 * that this is broken on SKL+.
553 // XXX: i965 disables this for arrays too, is that reasonable?
554 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
558 * Perform a HiZ or depth resolve operation.
560 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
561 * PRM, Volume 1, Part 2:
562 * - 7.5.3.1 Depth Buffer Clear
563 * - 7.5.3.2 Depth Buffer Resolve
564 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
567 iris_hiz_exec(struct iris_context
*ice
,
568 struct iris_batch
*batch
,
569 struct iris_resource
*res
,
570 unsigned int level
, unsigned int start_layer
,
571 unsigned int num_layers
, enum isl_aux_op op
,
572 bool update_clear_depth
)
574 assert(iris_resource_level_has_hiz(res
, level
));
575 assert(op
!= ISL_AUX_OP_NONE
);
576 UNUSED
const char *name
= NULL
;
579 case ISL_AUX_OP_FULL_RESOLVE
:
580 name
= "depth resolve";
582 case ISL_AUX_OP_AMBIGUATE
:
583 name
= "hiz ambiguate";
585 case ISL_AUX_OP_FAST_CLEAR
:
586 name
= "depth clear";
588 case ISL_AUX_OP_PARTIAL_RESOLVE
:
589 case ISL_AUX_OP_NONE
:
590 unreachable("Invalid HiZ op");
593 //DBG("%s %s to mt %p level %d layers %d-%d\n",
594 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
596 /* The following stalls and flushes are only documented to be required
597 * for HiZ clear operations. However, they also seem to be required for
598 * resolve operations.
600 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
602 * "If other rendering operations have preceded this clear, a
603 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
604 * enabled must be issued before the rectangle primitive used for
605 * the depth buffer clear operation."
607 * Same applies for Gen8 and Gen9.
609 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
610 * PIPE_CONTROL, Depth Cache Flush Enable:
612 * "This bit must not be set when Depth Stall Enable bit is set in
615 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
617 * Therefore issue two pipe control flushes, one for cache flush and
618 * another for depth stall.
620 iris_emit_pipe_control_flush(batch
,
621 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
622 PIPE_CONTROL_CS_STALL
);
624 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_DEPTH_STALL
);
626 assert(res
->aux
.usage
== ISL_AUX_USAGE_HIZ
&& res
->aux
.bo
);
628 iris_batch_maybe_flush(batch
, 1500);
630 struct blorp_surf surf
;
631 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
,
632 ISL_AUX_USAGE_HIZ
, level
, true);
634 struct blorp_batch blorp_batch
;
635 enum blorp_batch_flags flags
= 0;
636 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
637 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
638 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
639 blorp_batch_finish(&blorp_batch
);
641 /* The following stalls and flushes are only documented to be required
642 * for HiZ clear operations. However, they also seem to be required for
643 * resolve operations.
645 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
647 * "Depth buffer clear pass using any of the methods (WM_STATE,
648 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
649 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
650 * "set" before starting to render. DepthStall and DepthFlush are
651 * not needed between consecutive depth clear passes nor is it
652 * required if the depth clear pass was done with
653 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
655 * TODO: Such as the spec says, this could be conditional.
657 iris_emit_pipe_control_flush(batch
,
658 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
659 PIPE_CONTROL_DEPTH_STALL
);
663 * Does the resource's slice have hiz enabled?
666 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
668 iris_resource_check_level_layer(res
, level
, 0);
669 return res
->aux
.has_hiz
& 1 << level
;
672 /** \brief Assert that the level and layer are valid for the resource. */
674 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
675 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
677 assert(level
< res
->surf
.levels
);
678 assert(layer
< util_num_layers(&res
->base
, level
));
681 static inline uint32_t
682 miptree_level_range_length(const struct iris_resource
*res
,
683 uint32_t start_level
, uint32_t num_levels
)
685 assert(start_level
< res
->surf
.levels
);
687 if (num_levels
== INTEL_REMAINING_LAYERS
)
688 num_levels
= res
->surf
.levels
;
690 /* Check for overflow */
691 assert(start_level
+ num_levels
>= start_level
);
692 assert(start_level
+ num_levels
<= res
->surf
.levels
);
697 static inline uint32_t
698 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
699 uint32_t start_layer
, uint32_t num_layers
)
701 assert(level
<= res
->base
.last_level
);
703 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
704 assert(start_layer
< total_num_layers
);
705 if (num_layers
== INTEL_REMAINING_LAYERS
)
706 num_layers
= total_num_layers
- start_layer
;
707 /* Check for overflow */
708 assert(start_layer
+ num_layers
>= start_layer
);
709 assert(start_layer
+ num_layers
<= total_num_layers
);
715 has_color_unresolved(const struct iris_resource
*res
,
716 unsigned start_level
, unsigned num_levels
,
717 unsigned start_layer
, unsigned num_layers
)
722 /* Clamp the level range to fit the resource */
723 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
725 for (uint32_t l
= 0; l
< num_levels
; l
++) {
726 const uint32_t level
= start_level
+ l
;
727 const uint32_t level_layers
=
728 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
729 for (unsigned a
= 0; a
< level_layers
; a
++) {
730 enum isl_aux_state aux_state
=
731 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
732 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
733 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
741 static enum isl_aux_op
742 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
743 enum isl_aux_usage aux_usage
,
744 bool fast_clear_supported
)
746 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
748 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
750 assert(ccs_supported
== fast_clear_supported
);
753 case ISL_AUX_STATE_CLEAR
:
754 case ISL_AUX_STATE_PARTIAL_CLEAR
:
756 return ISL_AUX_OP_FULL_RESOLVE
;
758 return ISL_AUX_OP_NONE
;
760 case ISL_AUX_STATE_PASS_THROUGH
:
761 return ISL_AUX_OP_NONE
;
763 case ISL_AUX_STATE_RESOLVED
:
764 case ISL_AUX_STATE_AUX_INVALID
:
765 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
766 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
770 unreachable("Invalid aux state for CCS_D");
773 static enum isl_aux_op
774 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
775 enum isl_aux_usage aux_usage
,
776 bool fast_clear_supported
)
778 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
779 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
780 aux_usage
== ISL_AUX_USAGE_CCS_D
||
781 aux_usage
== ISL_AUX_USAGE_CCS_E
);
783 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
784 assert(fast_clear_supported
);
787 case ISL_AUX_STATE_CLEAR
:
788 case ISL_AUX_STATE_PARTIAL_CLEAR
:
789 if (fast_clear_supported
)
790 return ISL_AUX_OP_NONE
;
791 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
792 return ISL_AUX_OP_PARTIAL_RESOLVE
;
794 return ISL_AUX_OP_FULL_RESOLVE
;
796 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
797 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
798 return ISL_AUX_OP_FULL_RESOLVE
;
799 else if (!fast_clear_supported
)
800 return ISL_AUX_OP_PARTIAL_RESOLVE
;
802 return ISL_AUX_OP_NONE
;
804 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
805 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
806 return ISL_AUX_OP_FULL_RESOLVE
;
808 return ISL_AUX_OP_NONE
;
810 case ISL_AUX_STATE_PASS_THROUGH
:
811 return ISL_AUX_OP_NONE
;
813 case ISL_AUX_STATE_RESOLVED
:
814 case ISL_AUX_STATE_AUX_INVALID
:
818 unreachable("Invalid aux state for CCS_E");
822 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
823 struct iris_batch
*batch
,
824 struct iris_resource
*res
,
825 uint32_t level
, uint32_t layer
,
826 enum isl_aux_usage aux_usage
,
827 bool fast_clear_supported
)
829 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
831 enum isl_aux_op resolve_op
;
832 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
833 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
834 fast_clear_supported
);
836 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
837 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
838 fast_clear_supported
);
841 if (resolve_op
!= ISL_AUX_OP_NONE
) {
842 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
844 switch (resolve_op
) {
845 case ISL_AUX_OP_FULL_RESOLVE
:
846 /* The CCS full resolve operation destroys the CCS and sets it to the
847 * pass-through state. (You can also think of this as being both a
848 * resolve and an ambiguate in one operation.)
850 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
851 ISL_AUX_STATE_PASS_THROUGH
);
854 case ISL_AUX_OP_PARTIAL_RESOLVE
:
855 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
856 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
860 unreachable("Invalid resolve op");
866 iris_resource_finish_ccs_write(struct iris_context
*ice
,
867 struct iris_resource
*res
,
868 uint32_t level
, uint32_t layer
,
869 enum isl_aux_usage aux_usage
)
871 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
872 aux_usage
== ISL_AUX_USAGE_CCS_D
||
873 aux_usage
== ISL_AUX_USAGE_CCS_E
);
875 enum isl_aux_state aux_state
=
876 iris_resource_get_aux_state(res
, level
, layer
);
878 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
880 case ISL_AUX_STATE_CLEAR
:
881 case ISL_AUX_STATE_PARTIAL_CLEAR
:
882 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
883 aux_usage
== ISL_AUX_USAGE_CCS_D
);
885 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
886 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
887 ISL_AUX_STATE_COMPRESSED_CLEAR
);
888 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
889 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
890 ISL_AUX_STATE_PARTIAL_CLEAR
);
894 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
895 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
896 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
897 break; /* Nothing to do */
899 case ISL_AUX_STATE_PASS_THROUGH
:
900 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
901 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
902 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
908 case ISL_AUX_STATE_RESOLVED
:
909 case ISL_AUX_STATE_AUX_INVALID
:
910 unreachable("Invalid aux state for CCS_E");
913 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
914 /* CCS_D is a bit simpler */
916 case ISL_AUX_STATE_CLEAR
:
917 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
918 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
919 ISL_AUX_STATE_PARTIAL_CLEAR
);
922 case ISL_AUX_STATE_PARTIAL_CLEAR
:
923 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
924 break; /* Nothing to do */
926 case ISL_AUX_STATE_PASS_THROUGH
:
930 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
931 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
932 case ISL_AUX_STATE_RESOLVED
:
933 case ISL_AUX_STATE_AUX_INVALID
:
934 unreachable("Invalid aux state for CCS_D");
940 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
941 struct iris_batch
*batch
,
942 struct iris_resource
*res
,
944 enum isl_aux_usage aux_usage
,
945 bool fast_clear_supported
)
947 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
949 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
950 case ISL_AUX_STATE_CLEAR
:
951 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
952 if (!fast_clear_supported
) {
953 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
954 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
955 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
959 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
960 break; /* Nothing to do */
962 case ISL_AUX_STATE_RESOLVED
:
963 case ISL_AUX_STATE_PASS_THROUGH
:
964 case ISL_AUX_STATE_AUX_INVALID
:
965 case ISL_AUX_STATE_PARTIAL_CLEAR
:
966 unreachable("Invalid aux state for MCS");
971 iris_resource_finish_mcs_write(struct iris_context
*ice
,
972 struct iris_resource
*res
,
974 enum isl_aux_usage aux_usage
)
976 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
978 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
979 case ISL_AUX_STATE_CLEAR
:
980 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
981 ISL_AUX_STATE_COMPRESSED_CLEAR
);
984 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
985 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
986 break; /* Nothing to do */
988 case ISL_AUX_STATE_RESOLVED
:
989 case ISL_AUX_STATE_PASS_THROUGH
:
990 case ISL_AUX_STATE_AUX_INVALID
:
991 case ISL_AUX_STATE_PARTIAL_CLEAR
:
992 unreachable("Invalid aux state for MCS");
997 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
998 struct iris_batch
*batch
,
999 struct iris_resource
*res
,
1000 uint32_t level
, uint32_t layer
,
1001 enum isl_aux_usage aux_usage
,
1002 bool fast_clear_supported
)
1004 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1006 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
1007 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1008 case ISL_AUX_STATE_CLEAR
:
1009 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1010 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
1011 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1014 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1015 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
1016 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1019 case ISL_AUX_STATE_PASS_THROUGH
:
1020 case ISL_AUX_STATE_RESOLVED
:
1023 case ISL_AUX_STATE_AUX_INVALID
:
1024 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1025 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
1028 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1029 unreachable("Invalid HiZ state");
1032 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1033 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
, false);
1036 case ISL_AUX_OP_FULL_RESOLVE
:
1037 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1038 ISL_AUX_STATE_RESOLVED
);
1041 case ISL_AUX_OP_AMBIGUATE
:
1042 /* The HiZ resolve operation is actually an ambiguate */
1043 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1044 ISL_AUX_STATE_PASS_THROUGH
);
1048 unreachable("Invalid HiZ op");
1054 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1055 struct iris_resource
*res
,
1056 uint32_t level
, uint32_t layer
,
1057 enum isl_aux_usage aux_usage
)
1059 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1061 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1062 case ISL_AUX_STATE_CLEAR
:
1063 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1064 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1065 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1068 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1069 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1070 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1071 break; /* Nothing to do */
1073 case ISL_AUX_STATE_RESOLVED
:
1074 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1075 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1076 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1078 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1079 ISL_AUX_STATE_AUX_INVALID
);
1083 case ISL_AUX_STATE_PASS_THROUGH
:
1084 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1085 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1086 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1090 case ISL_AUX_STATE_AUX_INVALID
:
1091 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
1094 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1095 unreachable("Invalid HiZ state");
1100 iris_resource_prepare_access(struct iris_context
*ice
,
1101 struct iris_batch
*batch
,
1102 struct iris_resource
*res
,
1103 uint32_t start_level
, uint32_t num_levels
,
1104 uint32_t start_layer
, uint32_t num_layers
,
1105 enum isl_aux_usage aux_usage
,
1106 bool fast_clear_supported
)
1108 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1110 switch (res
->aux
.usage
) {
1111 case ISL_AUX_USAGE_NONE
:
1115 case ISL_AUX_USAGE_MCS
:
1116 assert(start_level
== 0 && num_levels
== 1);
1117 const uint32_t level_layers
=
1118 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1119 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1120 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1121 aux_usage
, fast_clear_supported
);
1125 case ISL_AUX_USAGE_CCS_D
:
1126 case ISL_AUX_USAGE_CCS_E
:
1127 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1128 const uint32_t level
= start_level
+ l
;
1129 const uint32_t level_layers
=
1130 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1131 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1132 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1134 aux_usage
, fast_clear_supported
);
1139 case ISL_AUX_USAGE_HIZ
:
1140 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1141 const uint32_t level
= start_level
+ l
;
1142 if (!iris_resource_level_has_hiz(res
, level
))
1145 const uint32_t level_layers
=
1146 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1147 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1148 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1149 start_layer
+ a
, aux_usage
,
1150 fast_clear_supported
);
1156 unreachable("Invalid aux usage");
1161 iris_resource_finish_write(struct iris_context
*ice
,
1162 struct iris_resource
*res
, uint32_t level
,
1163 uint32_t start_layer
, uint32_t num_layers
,
1164 enum isl_aux_usage aux_usage
)
1166 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1168 switch (res
->aux
.usage
) {
1169 case ISL_AUX_USAGE_NONE
:
1172 case ISL_AUX_USAGE_MCS
:
1173 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1174 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1179 case ISL_AUX_USAGE_CCS_D
:
1180 case ISL_AUX_USAGE_CCS_E
:
1181 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1182 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1187 case ISL_AUX_USAGE_HIZ
:
1188 if (!iris_resource_level_has_hiz(res
, level
))
1191 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1192 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1198 unreachable("Invavlid aux usage");
1203 iris_resource_get_aux_state(const struct iris_resource
*res
,
1204 uint32_t level
, uint32_t layer
)
1206 iris_resource_check_level_layer(res
, level
, layer
);
1208 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1209 assert(iris_resource_level_has_hiz(res
, level
));
1210 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1211 unreachable("Cannot get aux state for stencil");
1213 assert(res
->surf
.samples
== 1 ||
1214 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1217 return res
->aux
.state
[level
][layer
];
1221 iris_resource_set_aux_state(struct iris_context
*ice
,
1222 struct iris_resource
*res
, uint32_t level
,
1223 uint32_t start_layer
, uint32_t num_layers
,
1224 enum isl_aux_state aux_state
)
1226 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1228 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1229 assert(iris_resource_level_has_hiz(res
, level
));
1230 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1231 unreachable("Cannot set aux state for stencil");
1233 assert(res
->surf
.samples
== 1 ||
1234 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1237 for (unsigned a
= 0; a
< num_layers
; a
++) {
1238 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1239 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1240 /* XXX: Need to track which bindings to make dirty */
1241 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1246 /* On Gen9 color buffers may be compressed by the hardware (lossless
1247 * compression). There are, however, format restrictions and care needs to be
1248 * taken that the sampler engine is capable for re-interpreting a buffer with
1249 * format different the buffer was originally written with.
1251 * For example, SRGB formats are not compressible and the sampler engine isn't
1252 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1253 * color buffer needs to be resolved so that the sampling surface can be
1254 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1258 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1259 struct pipe_debug_callback
*dbg
,
1260 const struct iris_resource
*res
,
1261 enum isl_format view_format
)
1263 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1266 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1267 const struct isl_format_layout
*res_fmtl
=
1268 isl_format_get_layout(res
->surf
.format
);
1269 const struct isl_format_layout
*view_fmtl
=
1270 isl_format_get_layout(view_format
);
1272 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1273 view_fmtl
->name
, res_fmtl
->name
);
1282 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1283 const struct iris_resource
*res
,
1284 enum isl_format view_format
,
1285 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1287 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1288 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1290 assert(devinfo
->gen
== 9 || astc5x5_wa_bits
== 0);
1292 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
1293 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
1296 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
1297 res
->aux
.usage
!= ISL_AUX_USAGE_MCS
)
1298 return ISL_AUX_USAGE_NONE
;
1300 switch (res
->aux
.usage
) {
1301 case ISL_AUX_USAGE_HIZ
:
1302 if (sample_with_hiz(devinfo
, res
))
1303 return ISL_AUX_USAGE_HIZ
;
1306 case ISL_AUX_USAGE_MCS
:
1307 return ISL_AUX_USAGE_MCS
;
1309 case ISL_AUX_USAGE_CCS_D
:
1310 case ISL_AUX_USAGE_CCS_E
:
1311 /* If we don't have any unresolved color, report an aux usage of
1312 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1313 * aux surface and we can save some bandwidth.
1315 if (!has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1316 0, INTEL_REMAINING_LAYERS
))
1317 return ISL_AUX_USAGE_NONE
;
1319 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1320 return ISL_AUX_USAGE_CCS_E
;
1327 return ISL_AUX_USAGE_NONE
;
1331 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1333 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1334 * values so sRGB curve application was a no-op for all fast-clearable
1337 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1338 * values, the hardware interprets the floats, not as what would be
1339 * returned from the sampler (or written by the shader), but as being
1340 * between format conversion and sRGB curve application. This means that
1341 * we can switch between sRGB and UNORM without having to whack the clear
1344 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1348 iris_resource_prepare_texture(struct iris_context
*ice
,
1349 struct iris_batch
*batch
,
1350 struct iris_resource
*res
,
1351 enum isl_format view_format
,
1352 uint32_t start_level
, uint32_t num_levels
,
1353 uint32_t start_layer
, uint32_t num_layers
,
1354 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1356 enum isl_aux_usage aux_usage
=
1357 iris_resource_texture_aux_usage(ice
, res
, view_format
, astc5x5_wa_bits
);
1359 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1361 /* Clear color is specified as ints or floats and the conversion is done by
1362 * the sampler. If we have a texture view, we would have to perform the
1363 * clear color conversion manually. Just disable clear color.
1365 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1366 clear_supported
= false;
1368 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1369 start_layer
, num_layers
,
1370 aux_usage
, clear_supported
);
1374 iris_resource_prepare_image(struct iris_context
*ice
,
1375 struct iris_batch
*batch
,
1376 struct iris_resource
*res
)
1378 /* The data port doesn't understand any compression */
1379 iris_resource_prepare_access(ice
, batch
, res
, 0, INTEL_REMAINING_LEVELS
,
1380 0, INTEL_REMAINING_LAYERS
,
1381 ISL_AUX_USAGE_NONE
, false);
1385 iris_resource_render_aux_usage(struct iris_context
*ice
,
1386 struct iris_resource
*res
,
1387 enum isl_format render_format
,
1389 bool draw_aux_disabled
)
1391 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1392 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1394 if (draw_aux_disabled
)
1395 return ISL_AUX_USAGE_NONE
;
1397 switch (res
->aux
.usage
) {
1398 case ISL_AUX_USAGE_MCS
:
1399 return ISL_AUX_USAGE_MCS
;
1401 case ISL_AUX_USAGE_CCS_D
:
1402 case ISL_AUX_USAGE_CCS_E
:
1403 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1404 * formats. However, there are issues with blending where it doesn't
1405 * properly apply the sRGB curve to the clear color when blending.
1407 if (devinfo
->gen
>= 9 && blend_enabled
&&
1408 isl_format_is_srgb(render_format
) &&
1409 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1410 return ISL_AUX_USAGE_NONE
;
1412 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1413 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1414 return ISL_AUX_USAGE_CCS_E
;
1416 /* Otherwise, we have to fall back to CCS_D */
1417 return ISL_AUX_USAGE_CCS_D
;
1420 return ISL_AUX_USAGE_NONE
;
1425 iris_resource_prepare_render(struct iris_context
*ice
,
1426 struct iris_batch
*batch
,
1427 struct iris_resource
*res
, uint32_t level
,
1428 uint32_t start_layer
, uint32_t layer_count
,
1429 enum isl_aux_usage aux_usage
)
1431 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1432 layer_count
, aux_usage
,
1433 aux_usage
!= ISL_AUX_USAGE_NONE
);
1437 iris_resource_finish_render(struct iris_context
*ice
,
1438 struct iris_resource
*res
, uint32_t level
,
1439 uint32_t start_layer
, uint32_t layer_count
,
1440 enum isl_aux_usage aux_usage
)
1442 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1447 iris_resource_prepare_depth(struct iris_context
*ice
,
1448 struct iris_batch
*batch
,
1449 struct iris_resource
*res
, uint32_t level
,
1450 uint32_t start_layer
, uint32_t layer_count
)
1452 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1453 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1457 iris_resource_finish_depth(struct iris_context
*ice
,
1458 struct iris_resource
*res
, uint32_t level
,
1459 uint32_t start_layer
, uint32_t layer_count
,
1462 if (depth_written
) {
1463 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,