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11 * The above copyright notice and this permission notice shall be included
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
39 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
40 * or shader image. This causes a self-dependency, where both rendering
41 * and sampling may concurrently read or write the CCS buffer, causing
45 disable_rb_aux_buffer(struct iris_context
*ice
,
46 bool *draw_aux_buffer_disabled
,
47 struct iris_resource
*tex_res
,
48 unsigned min_level
, unsigned num_levels
,
51 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
54 /* We only need to worry about color compression and fast clears. */
55 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
56 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
59 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
60 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
64 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
66 if (rb_res
->bo
== tex_res
->bo
&&
67 surf
->base
.u
.tex
.level
>= min_level
&&
68 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
69 found
= draw_aux_buffer_disabled
[i
] = true;
75 "Disabling CCS because a renderbuffer is also bound %s.\n",
83 resolve_sampler_views(struct iris_context
*ice
,
84 struct iris_batch
*batch
,
85 struct iris_shader_state
*shs
,
86 bool *draw_aux_buffer_disabled
,
87 bool consider_framebuffer
)
89 uint32_t views
= shs
->bound_sampler_views
;
91 unsigned astc5x5_wa_bits
= 0; // XXX: actual tracking
94 const int i
= u_bit_scan(&views
);
95 struct iris_sampler_view
*isv
= shs
->textures
[i
];
96 struct iris_resource
*res
= (void *) isv
->base
.texture
;
98 if (res
->base
.target
!= PIPE_BUFFER
) {
99 if (consider_framebuffer
) {
100 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
101 res
, isv
->view
.base_level
, isv
->view
.levels
,
105 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
106 isv
->view
.base_level
, isv
->view
.levels
,
107 isv
->view
.base_array_layer
,
112 iris_cache_flush_for_read(batch
, res
->bo
);
117 resolve_image_views(struct iris_context
*ice
,
118 struct iris_batch
*batch
,
119 struct iris_shader_state
*shs
,
120 bool *draw_aux_buffer_disabled
,
121 bool consider_framebuffer
)
123 uint32_t views
= shs
->bound_image_views
;
126 const int i
= u_bit_scan(&views
);
127 struct iris_resource
*res
= (void *) shs
->image
[i
].res
;
129 if (res
->base
.target
!= PIPE_BUFFER
) {
130 if (consider_framebuffer
) {
131 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
132 res
, 0, ~0, "as a shader image");
135 iris_resource_prepare_image(ice
, batch
, res
);
138 iris_cache_flush_for_read(batch
, res
->bo
);
144 * \brief Resolve buffers before drawing.
146 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
147 * enabled depth texture, and flush the render cache for any dirty textures.
150 iris_predraw_resolve_inputs(struct iris_context
*ice
,
151 struct iris_batch
*batch
,
152 bool *draw_aux_buffer_disabled
,
153 gl_shader_stage stage
,
154 bool consider_framebuffer
)
156 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
158 uint64_t dirty
= (IRIS_DIRTY_BINDINGS_VS
<< stage
) |
159 (consider_framebuffer
? IRIS_DIRTY_BINDINGS_FS
: 0);
161 if (ice
->state
.dirty
& dirty
) {
162 resolve_sampler_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
163 consider_framebuffer
);
164 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
165 consider_framebuffer
);
172 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
173 struct iris_batch
*batch
,
174 bool *draw_aux_buffer_disabled
)
176 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
178 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
179 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
182 struct iris_resource
*z_res
, *s_res
;
183 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
184 unsigned num_layers
=
185 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
188 iris_resource_prepare_depth(ice
, batch
, z_res
,
189 zs_surf
->u
.tex
.level
,
190 zs_surf
->u
.tex
.first_layer
,
192 iris_cache_flush_for_depth(batch
, z_res
->bo
);
196 iris_cache_flush_for_depth(batch
, s_res
->bo
);
201 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
202 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
203 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
207 struct iris_resource
*res
= (void *) surf
->base
.texture
;
209 enum isl_aux_usage aux_usage
=
210 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
211 ice
->state
.blend_enables
& (1u << i
),
212 draw_aux_buffer_disabled
[i
]);
214 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
215 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
216 /* XXX: Need to track which bindings to make dirty */
217 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
220 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
221 surf
->view
.base_array_layer
,
222 surf
->view
.array_len
,
225 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
232 * \brief Call this after drawing to mark which buffers need resolving
234 * If the depth buffer was written to and if it has an accompanying HiZ
235 * buffer, then mark that it needs a depth resolve.
237 * If the color buffer is a multisample window system buffer, then
238 * mark that it needs a downsample.
240 * Also mark any render targets which will be textured as needing a render
244 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
245 struct iris_batch
*batch
)
247 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
249 // XXX: front buffer drawing?
251 if (ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
252 IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
253 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
255 struct iris_resource
*z_res
, *s_res
;
256 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
257 unsigned num_layers
=
258 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
261 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
262 zs_surf
->u
.tex
.first_layer
, num_layers
,
263 ice
->state
.depth_writes_enabled
);
265 if (ice
->state
.depth_writes_enabled
)
266 iris_depth_cache_add_bo(batch
, z_res
->bo
);
270 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
271 zs_surf
->u
.tex
.first_layer
, num_layers
,
274 if (ice
->state
.stencil_writes_enabled
)
275 iris_depth_cache_add_bo(batch
, s_res
->bo
);
280 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
281 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
282 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
286 struct iris_resource
*res
= (void *) surf
->base
.texture
;
287 union pipe_surface_desc
*desc
= &surf
->base
.u
;
288 unsigned num_layers
=
289 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
290 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
292 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
,
295 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
296 desc
->tex
.first_layer
, num_layers
,
303 * Clear the cache-tracking sets.
306 iris_cache_sets_clear(struct iris_batch
*batch
)
308 hash_table_foreach(batch
->cache
.render
, render_entry
)
309 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
311 set_foreach(batch
->cache
.depth
, depth_entry
)
312 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
316 * Emits an appropriate flush for a BO if it has been rendered to within the
317 * same batchbuffer as a read that's about to be emitted.
319 * The GPU has separate, incoherent caches for the render cache and the
320 * sampler cache, along with other caches. Usually data in the different
321 * caches don't interact (e.g. we don't render to our driver-generated
322 * immediate constant data), but for render-to-texture in FBOs we definitely
323 * do. When a batchbuffer is flushed, the kernel will ensure that everything
324 * necessary is flushed before another use of that BO, but for reuse from
325 * different caches within a batchbuffer, it's all our responsibility.
328 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
330 iris_emit_pipe_control_flush(batch
,
331 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
332 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
333 PIPE_CONTROL_CS_STALL
);
335 iris_emit_pipe_control_flush(batch
,
336 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
337 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
339 iris_cache_sets_clear(batch
);
343 iris_cache_flush_for_read(struct iris_batch
*batch
,
346 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
347 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
348 iris_flush_depth_and_render_caches(batch
);
352 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
354 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
358 iris_cache_flush_for_render(struct iris_batch
*batch
,
360 enum isl_format format
,
361 enum isl_aux_usage aux_usage
)
363 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
364 iris_flush_depth_and_render_caches(batch
);
366 /* Check to see if this bo has been used by a previous rendering operation
367 * but with a different format or aux usage. If it has, flush the render
368 * cache so we ensure that it's only in there with one format or aux usage
371 * Even though it's not obvious, this can easily happen in practice.
372 * Suppose a client is blending on a surface with sRGB encode enabled on
373 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
374 * then disables sRGB decode and continues blending we will flip on
375 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
376 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
377 * that we have fragments in-flight which are rendering with UNORM+CCS_E
378 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
379 * same time and the pixel scoreboard and color blender are trying to sort
380 * it all out. This ends badly (i.e. GPU hangs).
382 * To date, we have never observed GPU hangs or even corruption to be
383 * associated with switching the format, only the aux usage. However,
384 * there are comments in various docs which indicate that the render cache
385 * isn't 100% resilient to format changes. We may as well be conservative
386 * and flush on format changes too. We can always relax this later if we
387 * find it to be a performance problem.
389 struct hash_entry
*entry
=
390 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
391 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
392 iris_flush_depth_and_render_caches(batch
);
396 iris_render_cache_add_bo(struct iris_batch
*batch
,
398 enum isl_format format
,
399 enum isl_aux_usage aux_usage
)
402 struct hash_entry
*entry
=
403 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
405 /* Otherwise, someone didn't do a flush_for_render and that would be
408 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
412 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
413 format_aux_tuple(format
, aux_usage
));
417 iris_cache_flush_for_depth(struct iris_batch
*batch
,
420 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
421 iris_flush_depth_and_render_caches(batch
);
425 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
427 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
431 iris_resolve_color(struct iris_context
*ice
,
432 struct iris_batch
*batch
,
433 struct iris_resource
*res
,
434 unsigned level
, unsigned layer
,
435 enum isl_aux_op resolve_op
)
437 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
439 struct blorp_surf surf
;
440 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
443 iris_batch_maybe_flush(batch
, 1500);
445 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
447 * "Any transition from any value in {Clear, Render, Resolve} to a
448 * different value in {Clear, Render, Resolve} requires end of pipe
451 * In other words, fast clear ops are not properly synchronized with
452 * other drawing. We need to use a PIPE_CONTROL to ensure that the
453 * contents of the previous draw hit the render target before we resolve
454 * and again afterwards to ensure that the resolve is complete before we
455 * do any more regular drawing.
457 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
459 struct blorp_batch blorp_batch
;
460 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
461 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
462 isl_format_srgb_to_linear(res
->surf
.format
),
464 blorp_batch_finish(&blorp_batch
);
466 /* See comment above */
467 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
471 iris_mcs_partial_resolve(struct iris_context
*ice
,
472 struct iris_batch
*batch
,
473 struct iris_resource
*res
,
474 uint32_t start_layer
,
477 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
478 //start_layer, start_layer + num_layers - 1);
480 assert(res
->aux
.usage
== ISL_AUX_USAGE_MCS
);
482 struct blorp_surf surf
;
483 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
486 struct blorp_batch blorp_batch
;
487 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
488 blorp_mcs_partial_resolve(&blorp_batch
, &surf
, res
->surf
.format
,
489 start_layer
, num_layers
);
490 blorp_batch_finish(&blorp_batch
);
495 * Return true if the format that will be used to access the resource is
496 * CCS_E-compatible with the resource's linear/non-sRGB format.
498 * Why use the linear format? Well, although the resourcemay be specified
499 * with an sRGB format, the usage of that color space/format can be toggled.
500 * Since our HW tends to support more linear formats than sRGB ones, we use
501 * this format variant for check for CCS_E compatibility.
504 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
505 const struct iris_resource
*res
,
506 enum isl_format access_format
)
508 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
510 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
511 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
515 sample_with_hiz(const struct gen_device_info
*devinfo
,
516 const struct iris_resource
*res
)
518 if (!devinfo
->has_sample_with_hiz
)
521 if (res
->aux
.usage
!= ISL_AUX_USAGE_HIZ
)
524 /* It seems the hardware won't fallback to the depth buffer if some of the
525 * mipmap levels aren't available in the HiZ buffer. So we need all levels
526 * of the texture to be HiZ enabled.
528 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
529 if (!iris_resource_level_has_hiz(res
, level
))
533 /* If compressed multisampling is enabled, then we use it for the auxiliary
536 * From the BDW PRM (Volume 2d: Command Reference: Structures
537 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
539 * "If this field is set to AUX_HIZ, Number of Multisamples must be
540 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
542 * There is no such blurb for 1D textures, but there is sufficient evidence
543 * that this is broken on SKL+.
545 // XXX: i965 disables this for arrays too, is that reasonable?
546 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
550 * Perform a HiZ or depth resolve operation.
552 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
553 * PRM, Volume 1, Part 2:
554 * - 7.5.3.1 Depth Buffer Clear
555 * - 7.5.3.2 Depth Buffer Resolve
556 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
559 iris_hiz_exec(struct iris_context
*ice
,
560 struct iris_batch
*batch
,
561 struct iris_resource
*res
,
562 unsigned int level
, unsigned int start_layer
,
563 unsigned int num_layers
, enum isl_aux_op op
,
564 bool update_clear_depth
)
566 assert(iris_resource_level_has_hiz(res
, level
));
567 assert(op
!= ISL_AUX_OP_NONE
);
568 UNUSED
const char *name
= NULL
;
571 case ISL_AUX_OP_FULL_RESOLVE
:
572 name
= "depth resolve";
574 case ISL_AUX_OP_AMBIGUATE
:
575 name
= "hiz ambiguate";
577 case ISL_AUX_OP_FAST_CLEAR
:
578 name
= "depth clear";
580 case ISL_AUX_OP_PARTIAL_RESOLVE
:
581 case ISL_AUX_OP_NONE
:
582 unreachable("Invalid HiZ op");
585 //DBG("%s %s to mt %p level %d layers %d-%d\n",
586 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
588 /* The following stalls and flushes are only documented to be required
589 * for HiZ clear operations. However, they also seem to be required for
590 * resolve operations.
592 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
594 * "If other rendering operations have preceded this clear, a
595 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
596 * enabled must be issued before the rectangle primitive used for
597 * the depth buffer clear operation."
599 * Same applies for Gen8 and Gen9.
601 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
602 * PIPE_CONTROL, Depth Cache Flush Enable:
604 * "This bit must not be set when Depth Stall Enable bit is set in
607 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
609 * Therefore issue two pipe control flushes, one for cache flush and
610 * another for depth stall.
612 iris_emit_pipe_control_flush(batch
,
613 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
614 PIPE_CONTROL_CS_STALL
);
616 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_DEPTH_STALL
);
618 assert(res
->aux
.usage
== ISL_AUX_USAGE_HIZ
&& res
->aux
.bo
);
620 iris_batch_maybe_flush(batch
, 1500);
622 struct blorp_surf surf
;
623 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
,
624 ISL_AUX_USAGE_HIZ
, level
, true);
626 struct blorp_batch blorp_batch
;
627 enum blorp_batch_flags flags
= 0;
628 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
629 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
630 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
631 blorp_batch_finish(&blorp_batch
);
633 /* The following stalls and flushes are only documented to be required
634 * for HiZ clear operations. However, they also seem to be required for
635 * resolve operations.
637 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
639 * "Depth buffer clear pass using any of the methods (WM_STATE,
640 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
641 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
642 * "set" before starting to render. DepthStall and DepthFlush are
643 * not needed between consecutive depth clear passes nor is it
644 * required if the depth clear pass was done with
645 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
647 * TODO: Such as the spec says, this could be conditional.
649 iris_emit_pipe_control_flush(batch
,
650 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
651 PIPE_CONTROL_DEPTH_STALL
);
655 * Does the resource's slice have hiz enabled?
658 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
660 iris_resource_check_level_layer(res
, level
, 0);
661 return res
->aux
.has_hiz
& 1 << level
;
664 /** \brief Assert that the level and layer are valid for the resource. */
666 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
667 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
669 assert(level
< res
->surf
.levels
);
670 assert(layer
< util_num_layers(&res
->base
, level
));
673 static inline uint32_t
674 miptree_level_range_length(const struct iris_resource
*res
,
675 uint32_t start_level
, uint32_t num_levels
)
677 assert(start_level
< res
->surf
.levels
);
679 if (num_levels
== INTEL_REMAINING_LAYERS
)
680 num_levels
= res
->surf
.levels
;
682 /* Check for overflow */
683 assert(start_level
+ num_levels
>= start_level
);
684 assert(start_level
+ num_levels
<= res
->surf
.levels
);
689 static inline uint32_t
690 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
691 uint32_t start_layer
, uint32_t num_layers
)
693 assert(level
<= res
->base
.last_level
);
695 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
696 assert(start_layer
< total_num_layers
);
697 if (num_layers
== INTEL_REMAINING_LAYERS
)
698 num_layers
= total_num_layers
- start_layer
;
699 /* Check for overflow */
700 assert(start_layer
+ num_layers
>= start_layer
);
701 assert(start_layer
+ num_layers
<= total_num_layers
);
707 has_color_unresolved(const struct iris_resource
*res
,
708 unsigned start_level
, unsigned num_levels
,
709 unsigned start_layer
, unsigned num_layers
)
714 /* Clamp the level range to fit the resource */
715 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
717 for (uint32_t l
= 0; l
< num_levels
; l
++) {
718 const uint32_t level
= start_level
+ l
;
719 const uint32_t level_layers
=
720 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
721 for (unsigned a
= 0; a
< level_layers
; a
++) {
722 enum isl_aux_state aux_state
=
723 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
724 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
725 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
733 static enum isl_aux_op
734 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
735 enum isl_aux_usage aux_usage
,
736 bool fast_clear_supported
)
738 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
740 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
742 assert(ccs_supported
== fast_clear_supported
);
745 case ISL_AUX_STATE_CLEAR
:
746 case ISL_AUX_STATE_PARTIAL_CLEAR
:
748 return ISL_AUX_OP_FULL_RESOLVE
;
750 return ISL_AUX_OP_NONE
;
752 case ISL_AUX_STATE_PASS_THROUGH
:
753 return ISL_AUX_OP_NONE
;
755 case ISL_AUX_STATE_RESOLVED
:
756 case ISL_AUX_STATE_AUX_INVALID
:
757 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
758 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
762 unreachable("Invalid aux state for CCS_D");
765 static enum isl_aux_op
766 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
767 enum isl_aux_usage aux_usage
,
768 bool fast_clear_supported
)
770 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
771 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
772 aux_usage
== ISL_AUX_USAGE_CCS_D
||
773 aux_usage
== ISL_AUX_USAGE_CCS_E
);
775 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
776 assert(fast_clear_supported
);
779 case ISL_AUX_STATE_CLEAR
:
780 case ISL_AUX_STATE_PARTIAL_CLEAR
:
781 if (fast_clear_supported
)
782 return ISL_AUX_OP_NONE
;
783 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
784 return ISL_AUX_OP_PARTIAL_RESOLVE
;
786 return ISL_AUX_OP_FULL_RESOLVE
;
788 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
789 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
790 return ISL_AUX_OP_FULL_RESOLVE
;
791 else if (!fast_clear_supported
)
792 return ISL_AUX_OP_PARTIAL_RESOLVE
;
794 return ISL_AUX_OP_NONE
;
796 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
797 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
798 return ISL_AUX_OP_FULL_RESOLVE
;
800 return ISL_AUX_OP_NONE
;
802 case ISL_AUX_STATE_PASS_THROUGH
:
803 return ISL_AUX_OP_NONE
;
805 case ISL_AUX_STATE_RESOLVED
:
806 case ISL_AUX_STATE_AUX_INVALID
:
810 unreachable("Invalid aux state for CCS_E");
814 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
815 struct iris_batch
*batch
,
816 struct iris_resource
*res
,
817 uint32_t level
, uint32_t layer
,
818 enum isl_aux_usage aux_usage
,
819 bool fast_clear_supported
)
821 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
823 enum isl_aux_op resolve_op
;
824 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
825 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
826 fast_clear_supported
);
828 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
829 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
830 fast_clear_supported
);
833 if (resolve_op
!= ISL_AUX_OP_NONE
) {
834 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
836 switch (resolve_op
) {
837 case ISL_AUX_OP_FULL_RESOLVE
:
838 /* The CCS full resolve operation destroys the CCS and sets it to the
839 * pass-through state. (You can also think of this as being both a
840 * resolve and an ambiguate in one operation.)
842 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
843 ISL_AUX_STATE_PASS_THROUGH
);
846 case ISL_AUX_OP_PARTIAL_RESOLVE
:
847 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
848 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
852 unreachable("Invalid resolve op");
858 iris_resource_finish_ccs_write(struct iris_context
*ice
,
859 struct iris_resource
*res
,
860 uint32_t level
, uint32_t layer
,
861 enum isl_aux_usage aux_usage
)
863 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
864 aux_usage
== ISL_AUX_USAGE_CCS_D
||
865 aux_usage
== ISL_AUX_USAGE_CCS_E
);
867 enum isl_aux_state aux_state
=
868 iris_resource_get_aux_state(res
, level
, layer
);
870 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
872 case ISL_AUX_STATE_CLEAR
:
873 case ISL_AUX_STATE_PARTIAL_CLEAR
:
874 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
875 aux_usage
== ISL_AUX_USAGE_CCS_D
);
877 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
878 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
879 ISL_AUX_STATE_COMPRESSED_CLEAR
);
880 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
881 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
882 ISL_AUX_STATE_PARTIAL_CLEAR
);
886 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
887 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
888 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
889 break; /* Nothing to do */
891 case ISL_AUX_STATE_PASS_THROUGH
:
892 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
893 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
894 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
900 case ISL_AUX_STATE_RESOLVED
:
901 case ISL_AUX_STATE_AUX_INVALID
:
902 unreachable("Invalid aux state for CCS_E");
905 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
906 /* CCS_D is a bit simpler */
908 case ISL_AUX_STATE_CLEAR
:
909 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
910 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
911 ISL_AUX_STATE_PARTIAL_CLEAR
);
914 case ISL_AUX_STATE_PARTIAL_CLEAR
:
915 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
916 break; /* Nothing to do */
918 case ISL_AUX_STATE_PASS_THROUGH
:
922 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
923 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
924 case ISL_AUX_STATE_RESOLVED
:
925 case ISL_AUX_STATE_AUX_INVALID
:
926 unreachable("Invalid aux state for CCS_D");
932 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
933 struct iris_batch
*batch
,
934 struct iris_resource
*res
,
936 enum isl_aux_usage aux_usage
,
937 bool fast_clear_supported
)
939 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
941 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
942 case ISL_AUX_STATE_CLEAR
:
943 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
944 if (!fast_clear_supported
) {
945 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
946 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
947 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
951 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
952 break; /* Nothing to do */
954 case ISL_AUX_STATE_RESOLVED
:
955 case ISL_AUX_STATE_PASS_THROUGH
:
956 case ISL_AUX_STATE_AUX_INVALID
:
957 case ISL_AUX_STATE_PARTIAL_CLEAR
:
958 unreachable("Invalid aux state for MCS");
963 iris_resource_finish_mcs_write(struct iris_context
*ice
,
964 struct iris_resource
*res
,
966 enum isl_aux_usage aux_usage
)
968 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
970 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
971 case ISL_AUX_STATE_CLEAR
:
972 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
973 ISL_AUX_STATE_COMPRESSED_CLEAR
);
976 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
977 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
978 break; /* Nothing to do */
980 case ISL_AUX_STATE_RESOLVED
:
981 case ISL_AUX_STATE_PASS_THROUGH
:
982 case ISL_AUX_STATE_AUX_INVALID
:
983 case ISL_AUX_STATE_PARTIAL_CLEAR
:
984 unreachable("Invalid aux state for MCS");
989 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
990 struct iris_batch
*batch
,
991 struct iris_resource
*res
,
992 uint32_t level
, uint32_t layer
,
993 enum isl_aux_usage aux_usage
,
994 bool fast_clear_supported
)
996 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
998 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
999 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1000 case ISL_AUX_STATE_CLEAR
:
1001 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1002 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
1003 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1006 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1007 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
1008 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1011 case ISL_AUX_STATE_PASS_THROUGH
:
1012 case ISL_AUX_STATE_RESOLVED
:
1015 case ISL_AUX_STATE_AUX_INVALID
:
1016 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1017 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
1020 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1021 unreachable("Invalid HiZ state");
1024 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1025 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
, false);
1028 case ISL_AUX_OP_FULL_RESOLVE
:
1029 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1030 ISL_AUX_STATE_RESOLVED
);
1033 case ISL_AUX_OP_AMBIGUATE
:
1034 /* The HiZ resolve operation is actually an ambiguate */
1035 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1036 ISL_AUX_STATE_PASS_THROUGH
);
1040 unreachable("Invalid HiZ op");
1046 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1047 struct iris_resource
*res
,
1048 uint32_t level
, uint32_t layer
,
1049 enum isl_aux_usage aux_usage
)
1051 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1053 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1054 case ISL_AUX_STATE_CLEAR
:
1055 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1056 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1057 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1060 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1061 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1062 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1063 break; /* Nothing to do */
1065 case ISL_AUX_STATE_RESOLVED
:
1066 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1067 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1068 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1070 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1071 ISL_AUX_STATE_AUX_INVALID
);
1075 case ISL_AUX_STATE_PASS_THROUGH
:
1076 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1077 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1078 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1082 case ISL_AUX_STATE_AUX_INVALID
:
1083 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
1086 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1087 unreachable("Invalid HiZ state");
1092 iris_resource_prepare_access(struct iris_context
*ice
,
1093 struct iris_batch
*batch
,
1094 struct iris_resource
*res
,
1095 uint32_t start_level
, uint32_t num_levels
,
1096 uint32_t start_layer
, uint32_t num_layers
,
1097 enum isl_aux_usage aux_usage
,
1098 bool fast_clear_supported
)
1100 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1102 switch (res
->aux
.usage
) {
1103 case ISL_AUX_USAGE_NONE
:
1107 case ISL_AUX_USAGE_MCS
:
1108 assert(start_level
== 0 && num_levels
== 1);
1109 const uint32_t level_layers
=
1110 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1111 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1112 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1113 aux_usage
, fast_clear_supported
);
1117 case ISL_AUX_USAGE_CCS_D
:
1118 case ISL_AUX_USAGE_CCS_E
:
1119 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1120 const uint32_t level
= start_level
+ l
;
1121 const uint32_t level_layers
=
1122 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1123 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1124 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1126 aux_usage
, fast_clear_supported
);
1131 case ISL_AUX_USAGE_HIZ
:
1132 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1133 const uint32_t level
= start_level
+ l
;
1134 if (!iris_resource_level_has_hiz(res
, level
))
1137 const uint32_t level_layers
=
1138 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1139 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1140 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1141 start_layer
+ a
, aux_usage
,
1142 fast_clear_supported
);
1148 unreachable("Invalid aux usage");
1153 iris_resource_finish_write(struct iris_context
*ice
,
1154 struct iris_resource
*res
, uint32_t level
,
1155 uint32_t start_layer
, uint32_t num_layers
,
1156 enum isl_aux_usage aux_usage
)
1158 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1160 switch (res
->aux
.usage
) {
1161 case ISL_AUX_USAGE_NONE
:
1164 case ISL_AUX_USAGE_MCS
:
1165 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1166 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1171 case ISL_AUX_USAGE_CCS_D
:
1172 case ISL_AUX_USAGE_CCS_E
:
1173 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1174 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1179 case ISL_AUX_USAGE_HIZ
:
1180 if (!iris_resource_level_has_hiz(res
, level
))
1183 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1184 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1190 unreachable("Invavlid aux usage");
1195 iris_resource_get_aux_state(const struct iris_resource
*res
,
1196 uint32_t level
, uint32_t layer
)
1198 iris_resource_check_level_layer(res
, level
, layer
);
1200 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1201 assert(iris_resource_level_has_hiz(res
, level
));
1202 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1203 unreachable("Cannot get aux state for stencil");
1205 assert(res
->surf
.samples
== 1 ||
1206 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1209 return res
->aux
.state
[level
][layer
];
1213 iris_resource_set_aux_state(struct iris_context
*ice
,
1214 struct iris_resource
*res
, uint32_t level
,
1215 uint32_t start_layer
, uint32_t num_layers
,
1216 enum isl_aux_state aux_state
)
1218 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1220 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1221 assert(iris_resource_level_has_hiz(res
, level
));
1222 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1223 unreachable("Cannot set aux state for stencil");
1225 assert(res
->surf
.samples
== 1 ||
1226 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1229 for (unsigned a
= 0; a
< num_layers
; a
++) {
1230 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1231 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1232 /* XXX: Need to track which bindings to make dirty */
1233 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1238 /* On Gen9 color buffers may be compressed by the hardware (lossless
1239 * compression). There are, however, format restrictions and care needs to be
1240 * taken that the sampler engine is capable for re-interpreting a buffer with
1241 * format different the buffer was originally written with.
1243 * For example, SRGB formats are not compressible and the sampler engine isn't
1244 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1245 * color buffer needs to be resolved so that the sampling surface can be
1246 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1250 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1251 struct pipe_debug_callback
*dbg
,
1252 const struct iris_resource
*res
,
1253 enum isl_format view_format
)
1255 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1258 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1259 const struct isl_format_layout
*res_fmtl
=
1260 isl_format_get_layout(res
->surf
.format
);
1261 const struct isl_format_layout
*view_fmtl
=
1262 isl_format_get_layout(view_format
);
1264 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1265 view_fmtl
->name
, res_fmtl
->name
);
1274 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1275 const struct iris_resource
*res
,
1276 enum isl_format view_format
,
1277 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1279 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1280 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1282 assert(devinfo
->gen
== 9 || astc5x5_wa_bits
== 0);
1284 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
1285 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
1288 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
1289 res
->aux
.usage
!= ISL_AUX_USAGE_MCS
)
1290 return ISL_AUX_USAGE_NONE
;
1292 switch (res
->aux
.usage
) {
1293 case ISL_AUX_USAGE_HIZ
:
1294 if (sample_with_hiz(devinfo
, res
))
1295 return ISL_AUX_USAGE_HIZ
;
1298 case ISL_AUX_USAGE_MCS
:
1299 return ISL_AUX_USAGE_MCS
;
1301 case ISL_AUX_USAGE_CCS_D
:
1302 case ISL_AUX_USAGE_CCS_E
:
1303 /* If we don't have any unresolved color, report an aux usage of
1304 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1305 * aux surface and we can save some bandwidth.
1307 if (!has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1308 0, INTEL_REMAINING_LAYERS
))
1309 return ISL_AUX_USAGE_NONE
;
1311 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1312 return ISL_AUX_USAGE_CCS_E
;
1319 return ISL_AUX_USAGE_NONE
;
1323 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1325 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1326 * values so sRGB curve application was a no-op for all fast-clearable
1329 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1330 * values, the hardware interprets the floats, not as what would be
1331 * returned from the sampler (or written by the shader), but as being
1332 * between format conversion and sRGB curve application. This means that
1333 * we can switch between sRGB and UNORM without having to whack the clear
1336 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1340 iris_resource_prepare_texture(struct iris_context
*ice
,
1341 struct iris_batch
*batch
,
1342 struct iris_resource
*res
,
1343 enum isl_format view_format
,
1344 uint32_t start_level
, uint32_t num_levels
,
1345 uint32_t start_layer
, uint32_t num_layers
,
1346 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1348 enum isl_aux_usage aux_usage
=
1349 iris_resource_texture_aux_usage(ice
, res
, view_format
, astc5x5_wa_bits
);
1351 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1353 /* Clear color is specified as ints or floats and the conversion is done by
1354 * the sampler. If we have a texture view, we would have to perform the
1355 * clear color conversion manually. Just disable clear color.
1357 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1358 clear_supported
= false;
1360 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1361 start_layer
, num_layers
,
1362 aux_usage
, clear_supported
);
1366 iris_resource_prepare_image(struct iris_context
*ice
,
1367 struct iris_batch
*batch
,
1368 struct iris_resource
*res
)
1370 /* The data port doesn't understand any compression */
1371 iris_resource_prepare_access(ice
, batch
, res
, 0, INTEL_REMAINING_LEVELS
,
1372 0, INTEL_REMAINING_LAYERS
,
1373 ISL_AUX_USAGE_NONE
, false);
1377 iris_resource_render_aux_usage(struct iris_context
*ice
,
1378 struct iris_resource
*res
,
1379 enum isl_format render_format
,
1381 bool draw_aux_disabled
)
1383 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1384 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1386 if (draw_aux_disabled
)
1387 return ISL_AUX_USAGE_NONE
;
1389 switch (res
->aux
.usage
) {
1390 case ISL_AUX_USAGE_MCS
:
1391 return ISL_AUX_USAGE_MCS
;
1393 case ISL_AUX_USAGE_CCS_D
:
1394 case ISL_AUX_USAGE_CCS_E
:
1395 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1396 * formats. However, there are issues with blending where it doesn't
1397 * properly apply the sRGB curve to the clear color when blending.
1399 if (devinfo
->gen
>= 9 && blend_enabled
&&
1400 isl_format_is_srgb(render_format
) &&
1401 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1402 return ISL_AUX_USAGE_NONE
;
1404 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1405 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1406 return ISL_AUX_USAGE_CCS_E
;
1408 /* Otherwise, we have to fall back to CCS_D */
1409 return ISL_AUX_USAGE_CCS_D
;
1412 return ISL_AUX_USAGE_NONE
;
1417 iris_resource_prepare_render(struct iris_context
*ice
,
1418 struct iris_batch
*batch
,
1419 struct iris_resource
*res
, uint32_t level
,
1420 uint32_t start_layer
, uint32_t layer_count
,
1421 enum isl_aux_usage aux_usage
)
1423 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1424 layer_count
, aux_usage
,
1425 aux_usage
!= ISL_AUX_USAGE_NONE
);
1429 iris_resource_finish_render(struct iris_context
*ice
,
1430 struct iris_resource
*res
, uint32_t level
,
1431 uint32_t start_layer
, uint32_t layer_count
,
1432 enum isl_aux_usage aux_usage
)
1434 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1439 iris_resource_prepare_depth(struct iris_context
*ice
,
1440 struct iris_batch
*batch
,
1441 struct iris_resource
*res
, uint32_t level
,
1442 uint32_t start_layer
, uint32_t layer_count
)
1444 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1445 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1449 iris_resource_finish_depth(struct iris_context
*ice
,
1450 struct iris_resource
*res
, uint32_t level
,
1451 uint32_t start_layer
, uint32_t layer_count
,
1454 if (depth_written
) {
1455 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,