2 * Copyright © 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
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14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
37 #include "compiler/nir/nir.h"
40 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
41 * or shader image. This causes a self-dependency, where both rendering
42 * and sampling may concurrently read or write the CCS buffer, causing
46 disable_rb_aux_buffer(struct iris_context
*ice
,
47 bool *draw_aux_buffer_disabled
,
48 struct iris_resource
*tex_res
,
49 unsigned min_level
, unsigned num_levels
,
52 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
55 /* We only need to worry about color compression and fast clears. */
56 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
57 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
60 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
61 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
65 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
67 if (rb_res
->bo
== tex_res
->bo
&&
68 surf
->base
.u
.tex
.level
>= min_level
&&
69 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
70 found
= draw_aux_buffer_disabled
[i
] = true;
76 "Disabling CCS because a renderbuffer is also bound %s.\n",
84 resolve_sampler_views(struct iris_context
*ice
,
85 struct iris_batch
*batch
,
86 struct iris_shader_state
*shs
,
87 const struct shader_info
*info
,
88 bool *draw_aux_buffer_disabled
,
89 bool consider_framebuffer
)
91 uint32_t views
= info
? (shs
->bound_sampler_views
& info
->textures_used
) : 0;
93 unsigned astc5x5_wa_bits
= 0; // XXX: actual tracking
96 const int i
= u_bit_scan(&views
);
97 struct iris_sampler_view
*isv
= shs
->textures
[i
];
98 struct iris_resource
*res
= (void *) isv
->base
.texture
;
100 if (res
->base
.target
!= PIPE_BUFFER
) {
101 if (consider_framebuffer
) {
102 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
103 res
, isv
->view
.base_level
, isv
->view
.levels
,
107 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
108 isv
->view
.base_level
, isv
->view
.levels
,
109 isv
->view
.base_array_layer
,
114 iris_cache_flush_for_read(batch
, res
->bo
);
119 resolve_image_views(struct iris_context
*ice
,
120 struct iris_batch
*batch
,
121 struct iris_shader_state
*shs
,
122 bool *draw_aux_buffer_disabled
,
123 bool consider_framebuffer
)
125 /* TODO: Consider images used by program */
126 uint32_t views
= shs
->bound_image_views
;
129 const int i
= u_bit_scan(&views
);
130 struct iris_resource
*res
= (void *) shs
->image
[i
].base
.resource
;
132 if (res
->base
.target
!= PIPE_BUFFER
) {
133 if (consider_framebuffer
) {
134 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
135 res
, 0, ~0, "as a shader image");
138 iris_resource_prepare_image(ice
, batch
, res
);
141 iris_cache_flush_for_read(batch
, res
->bo
);
147 * \brief Resolve buffers before drawing.
149 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
150 * enabled depth texture, and flush the render cache for any dirty textures.
153 iris_predraw_resolve_inputs(struct iris_context
*ice
,
154 struct iris_batch
*batch
,
155 bool *draw_aux_buffer_disabled
,
156 gl_shader_stage stage
,
157 bool consider_framebuffer
)
159 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
160 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
162 uint64_t dirty
= (IRIS_DIRTY_BINDINGS_VS
<< stage
) |
163 (consider_framebuffer
? IRIS_DIRTY_BINDINGS_FS
: 0);
165 if (ice
->state
.dirty
& dirty
) {
166 resolve_sampler_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
167 consider_framebuffer
);
168 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
169 consider_framebuffer
);
176 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
177 struct iris_batch
*batch
,
178 bool *draw_aux_buffer_disabled
)
180 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
181 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
182 struct gen_device_info
*devinfo
= &screen
->devinfo
;
183 struct iris_uncompiled_shader
*ish
=
184 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
185 const nir_shader
*nir
= ish
->nir
;
187 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
188 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
191 struct iris_resource
*z_res
, *s_res
;
192 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
193 unsigned num_layers
=
194 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
197 iris_resource_prepare_depth(ice
, batch
, z_res
,
198 zs_surf
->u
.tex
.level
,
199 zs_surf
->u
.tex
.first_layer
,
201 iris_cache_flush_for_depth(batch
, z_res
->bo
);
205 iris_cache_flush_for_depth(batch
, s_res
->bo
);
210 if (devinfo
->gen
== 8 && nir
->info
.outputs_read
!= 0) {
211 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
212 if (cso_fb
->cbufs
[i
]) {
213 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
214 struct iris_resource
*res
= (void *) cso_fb
->cbufs
[i
]->texture
;
216 iris_resource_prepare_texture(ice
, batch
, res
, surf
->view
.format
,
217 surf
->view
.base_level
, 1,
218 surf
->view
.base_array_layer
,
219 surf
->view
.array_len
,
225 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
226 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
227 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
231 struct iris_resource
*res
= (void *) surf
->base
.texture
;
233 enum isl_aux_usage aux_usage
=
234 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
235 ice
->state
.blend_enables
& (1u << i
),
236 draw_aux_buffer_disabled
[i
]);
238 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
239 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
240 /* XXX: Need to track which bindings to make dirty */
241 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
244 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
245 surf
->view
.base_array_layer
,
246 surf
->view
.array_len
,
249 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
256 * \brief Call this after drawing to mark which buffers need resolving
258 * If the depth buffer was written to and if it has an accompanying HiZ
259 * buffer, then mark that it needs a depth resolve.
261 * If the color buffer is a multisample window system buffer, then
262 * mark that it needs a downsample.
264 * Also mark any render targets which will be textured as needing a render
268 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
269 struct iris_batch
*batch
)
271 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
273 // XXX: front buffer drawing?
275 bool may_have_resolved_depth
=
276 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
277 IRIS_DIRTY_WM_DEPTH_STENCIL
);
279 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
281 struct iris_resource
*z_res
, *s_res
;
282 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
283 unsigned num_layers
=
284 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
287 if (may_have_resolved_depth
) {
288 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
289 zs_surf
->u
.tex
.first_layer
, num_layers
,
290 ice
->state
.depth_writes_enabled
);
293 if (ice
->state
.depth_writes_enabled
)
294 iris_depth_cache_add_bo(batch
, z_res
->bo
);
298 if (may_have_resolved_depth
) {
299 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
300 zs_surf
->u
.tex
.first_layer
, num_layers
,
304 if (ice
->state
.stencil_writes_enabled
)
305 iris_depth_cache_add_bo(batch
, s_res
->bo
);
309 bool may_have_resolved_color
=
310 ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
);
312 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
313 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
317 struct iris_resource
*res
= (void *) surf
->base
.texture
;
318 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
320 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
,
323 if (may_have_resolved_color
) {
324 union pipe_surface_desc
*desc
= &surf
->base
.u
;
325 unsigned num_layers
=
326 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
327 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
328 desc
->tex
.first_layer
, num_layers
,
335 * Clear the cache-tracking sets.
338 iris_cache_sets_clear(struct iris_batch
*batch
)
340 hash_table_foreach(batch
->cache
.render
, render_entry
)
341 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
343 set_foreach(batch
->cache
.depth
, depth_entry
)
344 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
348 * Emits an appropriate flush for a BO if it has been rendered to within the
349 * same batchbuffer as a read that's about to be emitted.
351 * The GPU has separate, incoherent caches for the render cache and the
352 * sampler cache, along with other caches. Usually data in the different
353 * caches don't interact (e.g. we don't render to our driver-generated
354 * immediate constant data), but for render-to-texture in FBOs we definitely
355 * do. When a batchbuffer is flushed, the kernel will ensure that everything
356 * necessary is flushed before another use of that BO, but for reuse from
357 * different caches within a batchbuffer, it's all our responsibility.
360 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
362 iris_emit_pipe_control_flush(batch
,
363 "cache tracker: render-to-texture",
364 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
365 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
366 PIPE_CONTROL_CS_STALL
);
368 iris_emit_pipe_control_flush(batch
,
369 "cache tracker: render-to-texture",
370 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
371 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
373 iris_cache_sets_clear(batch
);
377 iris_cache_flush_for_read(struct iris_batch
*batch
,
380 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
381 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
382 iris_flush_depth_and_render_caches(batch
);
386 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
388 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
392 iris_cache_flush_for_render(struct iris_batch
*batch
,
394 enum isl_format format
,
395 enum isl_aux_usage aux_usage
)
397 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
398 iris_flush_depth_and_render_caches(batch
);
400 /* Check to see if this bo has been used by a previous rendering operation
401 * but with a different format or aux usage. If it has, flush the render
402 * cache so we ensure that it's only in there with one format or aux usage
405 * Even though it's not obvious, this can easily happen in practice.
406 * Suppose a client is blending on a surface with sRGB encode enabled on
407 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
408 * then disables sRGB decode and continues blending we will flip on
409 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
410 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
411 * that we have fragments in-flight which are rendering with UNORM+CCS_E
412 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
413 * same time and the pixel scoreboard and color blender are trying to sort
414 * it all out. This ends badly (i.e. GPU hangs).
416 * To date, we have never observed GPU hangs or even corruption to be
417 * associated with switching the format, only the aux usage. However,
418 * there are comments in various docs which indicate that the render cache
419 * isn't 100% resilient to format changes. We may as well be conservative
420 * and flush on format changes too. We can always relax this later if we
421 * find it to be a performance problem.
423 struct hash_entry
*entry
=
424 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
425 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
426 iris_flush_depth_and_render_caches(batch
);
430 iris_render_cache_add_bo(struct iris_batch
*batch
,
432 enum isl_format format
,
433 enum isl_aux_usage aux_usage
)
436 struct hash_entry
*entry
=
437 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
439 /* Otherwise, someone didn't do a flush_for_render and that would be
442 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
446 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
447 format_aux_tuple(format
, aux_usage
));
451 iris_cache_flush_for_depth(struct iris_batch
*batch
,
454 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
455 iris_flush_depth_and_render_caches(batch
);
459 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
461 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
465 iris_resolve_color(struct iris_context
*ice
,
466 struct iris_batch
*batch
,
467 struct iris_resource
*res
,
468 unsigned level
, unsigned layer
,
469 enum isl_aux_op resolve_op
)
471 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
473 struct blorp_surf surf
;
474 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
477 iris_batch_maybe_flush(batch
, 1500);
479 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
481 * "Any transition from any value in {Clear, Render, Resolve} to a
482 * different value in {Clear, Render, Resolve} requires end of pipe
485 * In other words, fast clear ops are not properly synchronized with
486 * other drawing. We need to use a PIPE_CONTROL to ensure that the
487 * contents of the previous draw hit the render target before we resolve
488 * and again afterwards to ensure that the resolve is complete before we
489 * do any more regular drawing.
491 iris_emit_end_of_pipe_sync(batch
, "color resolve: pre-flush",
492 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
494 struct blorp_batch blorp_batch
;
495 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
496 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
497 isl_format_srgb_to_linear(res
->surf
.format
),
499 blorp_batch_finish(&blorp_batch
);
501 /* See comment above */
502 iris_emit_end_of_pipe_sync(batch
, "color resolve: post-flush",
503 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
507 iris_mcs_partial_resolve(struct iris_context
*ice
,
508 struct iris_batch
*batch
,
509 struct iris_resource
*res
,
510 uint32_t start_layer
,
513 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
514 //start_layer, start_layer + num_layers - 1);
516 assert(res
->aux
.usage
== ISL_AUX_USAGE_MCS
);
518 struct blorp_surf surf
;
519 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
522 struct blorp_batch blorp_batch
;
523 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
524 blorp_mcs_partial_resolve(&blorp_batch
, &surf
,
525 isl_format_srgb_to_linear(res
->surf
.format
),
526 start_layer
, num_layers
);
527 blorp_batch_finish(&blorp_batch
);
532 * Return true if the format that will be used to access the resource is
533 * CCS_E-compatible with the resource's linear/non-sRGB format.
535 * Why use the linear format? Well, although the resourcemay be specified
536 * with an sRGB format, the usage of that color space/format can be toggled.
537 * Since our HW tends to support more linear formats than sRGB ones, we use
538 * this format variant for check for CCS_E compatibility.
541 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
542 const struct iris_resource
*res
,
543 enum isl_format access_format
)
545 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
547 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
548 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
552 sample_with_hiz(const struct gen_device_info
*devinfo
,
553 const struct iris_resource
*res
)
555 if (!devinfo
->has_sample_with_hiz
)
558 if (res
->aux
.usage
!= ISL_AUX_USAGE_HIZ
)
561 /* It seems the hardware won't fallback to the depth buffer if some of the
562 * mipmap levels aren't available in the HiZ buffer. So we need all levels
563 * of the texture to be HiZ enabled.
565 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
566 if (!iris_resource_level_has_hiz(res
, level
))
570 /* If compressed multisampling is enabled, then we use it for the auxiliary
573 * From the BDW PRM (Volume 2d: Command Reference: Structures
574 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
576 * "If this field is set to AUX_HIZ, Number of Multisamples must be
577 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
579 * There is no such blurb for 1D textures, but there is sufficient evidence
580 * that this is broken on SKL+.
582 // XXX: i965 disables this for arrays too, is that reasonable?
583 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
587 * Perform a HiZ or depth resolve operation.
589 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
590 * PRM, Volume 1, Part 2:
591 * - 7.5.3.1 Depth Buffer Clear
592 * - 7.5.3.2 Depth Buffer Resolve
593 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
596 iris_hiz_exec(struct iris_context
*ice
,
597 struct iris_batch
*batch
,
598 struct iris_resource
*res
,
599 unsigned int level
, unsigned int start_layer
,
600 unsigned int num_layers
, enum isl_aux_op op
,
601 bool update_clear_depth
)
603 assert(iris_resource_level_has_hiz(res
, level
));
604 assert(op
!= ISL_AUX_OP_NONE
);
605 UNUSED
const char *name
= NULL
;
608 case ISL_AUX_OP_FULL_RESOLVE
:
609 name
= "depth resolve";
611 case ISL_AUX_OP_AMBIGUATE
:
612 name
= "hiz ambiguate";
614 case ISL_AUX_OP_FAST_CLEAR
:
615 name
= "depth clear";
617 case ISL_AUX_OP_PARTIAL_RESOLVE
:
618 case ISL_AUX_OP_NONE
:
619 unreachable("Invalid HiZ op");
622 //DBG("%s %s to mt %p level %d layers %d-%d\n",
623 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
625 /* The following stalls and flushes are only documented to be required
626 * for HiZ clear operations. However, they also seem to be required for
627 * resolve operations.
629 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
631 * "If other rendering operations have preceded this clear, a
632 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
633 * enabled must be issued before the rectangle primitive used for
634 * the depth buffer clear operation."
636 * Same applies for Gen8 and Gen9.
638 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
639 * PIPE_CONTROL, Depth Cache Flush Enable:
641 * "This bit must not be set when Depth Stall Enable bit is set in
644 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
646 * Therefore issue two pipe control flushes, one for cache flush and
647 * another for depth stall.
649 iris_emit_pipe_control_flush(batch
,
650 "hiz op: pre-flushes (1/2)",
651 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
652 PIPE_CONTROL_CS_STALL
);
654 iris_emit_pipe_control_flush(batch
, "hiz op: pre-flushes (2/2)",
655 PIPE_CONTROL_DEPTH_STALL
);
657 assert(res
->aux
.usage
== ISL_AUX_USAGE_HIZ
&& res
->aux
.bo
);
659 iris_batch_maybe_flush(batch
, 1500);
661 struct blorp_surf surf
;
662 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
,
663 ISL_AUX_USAGE_HIZ
, level
, true);
665 struct blorp_batch blorp_batch
;
666 enum blorp_batch_flags flags
= 0;
667 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
668 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
669 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
670 blorp_batch_finish(&blorp_batch
);
672 /* The following stalls and flushes are only documented to be required
673 * for HiZ clear operations. However, they also seem to be required for
674 * resolve operations.
676 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
678 * "Depth buffer clear pass using any of the methods (WM_STATE,
679 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
680 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
681 * "set" before starting to render. DepthStall and DepthFlush are
682 * not needed between consecutive depth clear passes nor is it
683 * required if the depth clear pass was done with
684 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
686 * TODO: Such as the spec says, this could be conditional.
688 iris_emit_pipe_control_flush(batch
,
689 "hiz op: post flush",
690 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
691 PIPE_CONTROL_DEPTH_STALL
);
695 * Does the resource's slice have hiz enabled?
698 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
700 iris_resource_check_level_layer(res
, level
, 0);
701 return res
->aux
.has_hiz
& 1 << level
;
704 /** \brief Assert that the level and layer are valid for the resource. */
706 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
707 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
709 assert(level
< res
->surf
.levels
);
710 assert(layer
< util_num_layers(&res
->base
, level
));
713 static inline uint32_t
714 miptree_level_range_length(const struct iris_resource
*res
,
715 uint32_t start_level
, uint32_t num_levels
)
717 assert(start_level
< res
->surf
.levels
);
719 if (num_levels
== INTEL_REMAINING_LAYERS
)
720 num_levels
= res
->surf
.levels
;
722 /* Check for overflow */
723 assert(start_level
+ num_levels
>= start_level
);
724 assert(start_level
+ num_levels
<= res
->surf
.levels
);
729 static inline uint32_t
730 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
731 uint32_t start_layer
, uint32_t num_layers
)
733 assert(level
<= res
->base
.last_level
);
735 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
736 assert(start_layer
< total_num_layers
);
737 if (num_layers
== INTEL_REMAINING_LAYERS
)
738 num_layers
= total_num_layers
- start_layer
;
739 /* Check for overflow */
740 assert(start_layer
+ num_layers
>= start_layer
);
741 assert(start_layer
+ num_layers
<= total_num_layers
);
747 iris_has_color_unresolved(const struct iris_resource
*res
,
748 unsigned start_level
, unsigned num_levels
,
749 unsigned start_layer
, unsigned num_layers
)
754 /* Clamp the level range to fit the resource */
755 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
757 for (uint32_t l
= 0; l
< num_levels
; l
++) {
758 const uint32_t level
= start_level
+ l
;
759 const uint32_t level_layers
=
760 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
761 for (unsigned a
= 0; a
< level_layers
; a
++) {
762 enum isl_aux_state aux_state
=
763 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
764 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
765 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
773 static enum isl_aux_op
774 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
775 enum isl_aux_usage aux_usage
,
776 bool fast_clear_supported
)
778 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
780 const bool ccs_supported
=
781 (aux_usage
== ISL_AUX_USAGE_CCS_D
) && fast_clear_supported
;
784 case ISL_AUX_STATE_CLEAR
:
785 case ISL_AUX_STATE_PARTIAL_CLEAR
:
787 return ISL_AUX_OP_FULL_RESOLVE
;
789 return ISL_AUX_OP_NONE
;
791 case ISL_AUX_STATE_PASS_THROUGH
:
792 return ISL_AUX_OP_NONE
;
794 case ISL_AUX_STATE_RESOLVED
:
795 case ISL_AUX_STATE_AUX_INVALID
:
796 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
797 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
801 unreachable("Invalid aux state for CCS_D");
804 static enum isl_aux_op
805 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
806 enum isl_aux_usage aux_usage
,
807 bool fast_clear_supported
)
809 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
810 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
811 aux_usage
== ISL_AUX_USAGE_CCS_D
||
812 aux_usage
== ISL_AUX_USAGE_CCS_E
);
815 case ISL_AUX_STATE_CLEAR
:
816 case ISL_AUX_STATE_PARTIAL_CLEAR
:
817 if (fast_clear_supported
)
818 return ISL_AUX_OP_NONE
;
819 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
820 return ISL_AUX_OP_PARTIAL_RESOLVE
;
822 return ISL_AUX_OP_FULL_RESOLVE
;
824 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
825 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
826 return ISL_AUX_OP_FULL_RESOLVE
;
827 else if (!fast_clear_supported
)
828 return ISL_AUX_OP_PARTIAL_RESOLVE
;
830 return ISL_AUX_OP_NONE
;
832 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
833 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
834 return ISL_AUX_OP_FULL_RESOLVE
;
836 return ISL_AUX_OP_NONE
;
838 case ISL_AUX_STATE_PASS_THROUGH
:
839 return ISL_AUX_OP_NONE
;
841 case ISL_AUX_STATE_RESOLVED
:
842 case ISL_AUX_STATE_AUX_INVALID
:
846 unreachable("Invalid aux state for CCS_E");
850 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
851 struct iris_batch
*batch
,
852 struct iris_resource
*res
,
853 uint32_t level
, uint32_t layer
,
854 enum isl_aux_usage aux_usage
,
855 bool fast_clear_supported
)
857 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
859 enum isl_aux_op resolve_op
;
860 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
861 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
862 fast_clear_supported
);
864 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
865 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
866 fast_clear_supported
);
869 if (resolve_op
!= ISL_AUX_OP_NONE
) {
870 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
872 switch (resolve_op
) {
873 case ISL_AUX_OP_FULL_RESOLVE
:
874 /* The CCS full resolve operation destroys the CCS and sets it to the
875 * pass-through state. (You can also think of this as being both a
876 * resolve and an ambiguate in one operation.)
878 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
879 ISL_AUX_STATE_PASS_THROUGH
);
882 case ISL_AUX_OP_PARTIAL_RESOLVE
:
883 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
884 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
888 unreachable("Invalid resolve op");
894 iris_resource_finish_ccs_write(struct iris_context
*ice
,
895 struct iris_resource
*res
,
896 uint32_t level
, uint32_t layer
,
897 enum isl_aux_usage aux_usage
)
899 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
900 aux_usage
== ISL_AUX_USAGE_CCS_D
||
901 aux_usage
== ISL_AUX_USAGE_CCS_E
);
903 enum isl_aux_state aux_state
=
904 iris_resource_get_aux_state(res
, level
, layer
);
906 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
908 case ISL_AUX_STATE_CLEAR
:
909 case ISL_AUX_STATE_PARTIAL_CLEAR
:
910 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
911 aux_usage
== ISL_AUX_USAGE_CCS_D
);
913 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
914 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
915 ISL_AUX_STATE_COMPRESSED_CLEAR
);
916 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
917 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
918 ISL_AUX_STATE_PARTIAL_CLEAR
);
922 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
923 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
924 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
925 break; /* Nothing to do */
927 case ISL_AUX_STATE_PASS_THROUGH
:
928 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
929 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
930 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
936 case ISL_AUX_STATE_RESOLVED
:
937 case ISL_AUX_STATE_AUX_INVALID
:
938 unreachable("Invalid aux state for CCS_E");
941 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
942 /* CCS_D is a bit simpler */
944 case ISL_AUX_STATE_CLEAR
:
945 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
946 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
947 ISL_AUX_STATE_PARTIAL_CLEAR
);
950 case ISL_AUX_STATE_PARTIAL_CLEAR
:
951 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
952 break; /* Nothing to do */
954 case ISL_AUX_STATE_PASS_THROUGH
:
958 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
959 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
960 case ISL_AUX_STATE_RESOLVED
:
961 case ISL_AUX_STATE_AUX_INVALID
:
962 unreachable("Invalid aux state for CCS_D");
968 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
969 struct iris_batch
*batch
,
970 struct iris_resource
*res
,
972 enum isl_aux_usage aux_usage
,
973 bool fast_clear_supported
)
975 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
977 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
978 case ISL_AUX_STATE_CLEAR
:
979 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
980 if (!fast_clear_supported
) {
981 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
982 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
983 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
987 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
988 break; /* Nothing to do */
990 case ISL_AUX_STATE_RESOLVED
:
991 case ISL_AUX_STATE_PASS_THROUGH
:
992 case ISL_AUX_STATE_AUX_INVALID
:
993 case ISL_AUX_STATE_PARTIAL_CLEAR
:
994 unreachable("Invalid aux state for MCS");
999 iris_resource_finish_mcs_write(struct iris_context
*ice
,
1000 struct iris_resource
*res
,
1002 enum isl_aux_usage aux_usage
)
1004 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
1006 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
1007 case ISL_AUX_STATE_CLEAR
:
1008 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
1009 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1012 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1013 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1014 break; /* Nothing to do */
1016 case ISL_AUX_STATE_RESOLVED
:
1017 case ISL_AUX_STATE_PASS_THROUGH
:
1018 case ISL_AUX_STATE_AUX_INVALID
:
1019 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1020 unreachable("Invalid aux state for MCS");
1025 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
1026 struct iris_batch
*batch
,
1027 struct iris_resource
*res
,
1028 uint32_t level
, uint32_t layer
,
1029 enum isl_aux_usage aux_usage
,
1030 bool fast_clear_supported
)
1032 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1034 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
1035 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1036 case ISL_AUX_STATE_CLEAR
:
1037 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1038 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
1039 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1042 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1043 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
1044 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1047 case ISL_AUX_STATE_PASS_THROUGH
:
1048 case ISL_AUX_STATE_RESOLVED
:
1051 case ISL_AUX_STATE_AUX_INVALID
:
1052 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1053 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
1056 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1057 unreachable("Invalid HiZ state");
1060 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1061 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
, false);
1064 case ISL_AUX_OP_FULL_RESOLVE
:
1065 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1066 ISL_AUX_STATE_RESOLVED
);
1069 case ISL_AUX_OP_AMBIGUATE
:
1070 /* The HiZ resolve operation is actually an ambiguate */
1071 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1072 ISL_AUX_STATE_PASS_THROUGH
);
1076 unreachable("Invalid HiZ op");
1082 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1083 struct iris_resource
*res
,
1084 uint32_t level
, uint32_t layer
,
1085 enum isl_aux_usage aux_usage
)
1087 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1089 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1090 case ISL_AUX_STATE_CLEAR
:
1091 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1092 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1093 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1096 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1097 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1098 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1099 break; /* Nothing to do */
1101 case ISL_AUX_STATE_RESOLVED
:
1102 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1103 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1104 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1106 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1107 ISL_AUX_STATE_AUX_INVALID
);
1111 case ISL_AUX_STATE_PASS_THROUGH
:
1112 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1113 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1114 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1118 case ISL_AUX_STATE_AUX_INVALID
:
1119 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
1122 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1123 unreachable("Invalid HiZ state");
1128 iris_resource_prepare_access(struct iris_context
*ice
,
1129 struct iris_batch
*batch
,
1130 struct iris_resource
*res
,
1131 uint32_t start_level
, uint32_t num_levels
,
1132 uint32_t start_layer
, uint32_t num_layers
,
1133 enum isl_aux_usage aux_usage
,
1134 bool fast_clear_supported
)
1136 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1138 switch (res
->aux
.usage
) {
1139 case ISL_AUX_USAGE_NONE
:
1143 case ISL_AUX_USAGE_MCS
:
1144 assert(start_level
== 0 && num_levels
== 1);
1145 const uint32_t level_layers
=
1146 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1147 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1148 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1149 aux_usage
, fast_clear_supported
);
1153 case ISL_AUX_USAGE_CCS_D
:
1154 case ISL_AUX_USAGE_CCS_E
:
1155 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1156 const uint32_t level
= start_level
+ l
;
1157 const uint32_t level_layers
=
1158 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1159 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1160 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1162 aux_usage
, fast_clear_supported
);
1167 case ISL_AUX_USAGE_HIZ
:
1168 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1169 const uint32_t level
= start_level
+ l
;
1170 if (!iris_resource_level_has_hiz(res
, level
))
1173 const uint32_t level_layers
=
1174 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1175 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1176 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1177 start_layer
+ a
, aux_usage
,
1178 fast_clear_supported
);
1184 unreachable("Invalid aux usage");
1189 iris_resource_finish_write(struct iris_context
*ice
,
1190 struct iris_resource
*res
, uint32_t level
,
1191 uint32_t start_layer
, uint32_t num_layers
,
1192 enum isl_aux_usage aux_usage
)
1194 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1196 switch (res
->aux
.usage
) {
1197 case ISL_AUX_USAGE_NONE
:
1200 case ISL_AUX_USAGE_MCS
:
1201 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1202 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1207 case ISL_AUX_USAGE_CCS_D
:
1208 case ISL_AUX_USAGE_CCS_E
:
1209 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1210 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1215 case ISL_AUX_USAGE_HIZ
:
1216 if (!iris_resource_level_has_hiz(res
, level
))
1219 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1220 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1226 unreachable("Invavlid aux usage");
1231 iris_resource_get_aux_state(const struct iris_resource
*res
,
1232 uint32_t level
, uint32_t layer
)
1234 iris_resource_check_level_layer(res
, level
, layer
);
1236 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1237 assert(iris_resource_level_has_hiz(res
, level
));
1238 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1239 unreachable("Cannot get aux state for stencil");
1241 assert(res
->surf
.samples
== 1 ||
1242 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1245 return res
->aux
.state
[level
][layer
];
1249 iris_resource_set_aux_state(struct iris_context
*ice
,
1250 struct iris_resource
*res
, uint32_t level
,
1251 uint32_t start_layer
, uint32_t num_layers
,
1252 enum isl_aux_state aux_state
)
1254 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1256 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1257 assert(iris_resource_level_has_hiz(res
, level
));
1258 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1259 unreachable("Cannot set aux state for stencil");
1261 assert(res
->surf
.samples
== 1 ||
1262 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1265 for (unsigned a
= 0; a
< num_layers
; a
++) {
1266 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1267 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1268 /* XXX: Need to track which bindings to make dirty */
1269 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1274 /* On Gen9 color buffers may be compressed by the hardware (lossless
1275 * compression). There are, however, format restrictions and care needs to be
1276 * taken that the sampler engine is capable for re-interpreting a buffer with
1277 * format different the buffer was originally written with.
1279 * For example, SRGB formats are not compressible and the sampler engine isn't
1280 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1281 * color buffer needs to be resolved so that the sampling surface can be
1282 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1286 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1287 struct pipe_debug_callback
*dbg
,
1288 const struct iris_resource
*res
,
1289 enum isl_format view_format
)
1291 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1294 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1295 const struct isl_format_layout
*res_fmtl
=
1296 isl_format_get_layout(res
->surf
.format
);
1297 const struct isl_format_layout
*view_fmtl
=
1298 isl_format_get_layout(view_format
);
1300 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1301 view_fmtl
->name
, res_fmtl
->name
);
1310 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1311 const struct iris_resource
*res
,
1312 enum isl_format view_format
,
1313 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1315 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1316 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1318 assert(devinfo
->gen
== 9 || astc5x5_wa_bits
== 0);
1320 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
1321 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
1324 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
1325 res
->aux
.usage
!= ISL_AUX_USAGE_MCS
)
1326 return ISL_AUX_USAGE_NONE
;
1328 switch (res
->aux
.usage
) {
1329 case ISL_AUX_USAGE_HIZ
:
1330 if (sample_with_hiz(devinfo
, res
))
1331 return ISL_AUX_USAGE_HIZ
;
1334 case ISL_AUX_USAGE_MCS
:
1335 return ISL_AUX_USAGE_MCS
;
1337 case ISL_AUX_USAGE_CCS_D
:
1338 case ISL_AUX_USAGE_CCS_E
:
1339 /* If we don't have any unresolved color, report an aux usage of
1340 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1341 * aux surface and we can save some bandwidth.
1343 if (!iris_has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1344 0, INTEL_REMAINING_LAYERS
))
1345 return ISL_AUX_USAGE_NONE
;
1347 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1348 return ISL_AUX_USAGE_CCS_E
;
1355 return ISL_AUX_USAGE_NONE
;
1359 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1361 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1362 * values so sRGB curve application was a no-op for all fast-clearable
1365 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1366 * values, the hardware interprets the floats, not as what would be
1367 * returned from the sampler (or written by the shader), but as being
1368 * between format conversion and sRGB curve application. This means that
1369 * we can switch between sRGB and UNORM without having to whack the clear
1372 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1376 iris_resource_prepare_texture(struct iris_context
*ice
,
1377 struct iris_batch
*batch
,
1378 struct iris_resource
*res
,
1379 enum isl_format view_format
,
1380 uint32_t start_level
, uint32_t num_levels
,
1381 uint32_t start_layer
, uint32_t num_layers
,
1382 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1384 enum isl_aux_usage aux_usage
=
1385 iris_resource_texture_aux_usage(ice
, res
, view_format
, astc5x5_wa_bits
);
1387 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1389 /* Clear color is specified as ints or floats and the conversion is done by
1390 * the sampler. If we have a texture view, we would have to perform the
1391 * clear color conversion manually. Just disable clear color.
1393 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1394 clear_supported
= false;
1396 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1397 start_layer
, num_layers
,
1398 aux_usage
, clear_supported
);
1402 iris_resource_prepare_image(struct iris_context
*ice
,
1403 struct iris_batch
*batch
,
1404 struct iris_resource
*res
)
1406 /* The data port doesn't understand any compression */
1407 iris_resource_prepare_access(ice
, batch
, res
, 0, INTEL_REMAINING_LEVELS
,
1408 0, INTEL_REMAINING_LAYERS
,
1409 ISL_AUX_USAGE_NONE
, false);
1413 iris_resource_render_aux_usage(struct iris_context
*ice
,
1414 struct iris_resource
*res
,
1415 enum isl_format render_format
,
1417 bool draw_aux_disabled
)
1419 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1420 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1422 if (draw_aux_disabled
)
1423 return ISL_AUX_USAGE_NONE
;
1425 switch (res
->aux
.usage
) {
1426 case ISL_AUX_USAGE_MCS
:
1427 return ISL_AUX_USAGE_MCS
;
1429 case ISL_AUX_USAGE_CCS_D
:
1430 case ISL_AUX_USAGE_CCS_E
:
1431 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1432 * formats. However, there are issues with blending where it doesn't
1433 * properly apply the sRGB curve to the clear color when blending.
1435 if (devinfo
->gen
>= 9 && blend_enabled
&&
1436 isl_format_is_srgb(render_format
) &&
1437 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1438 return ISL_AUX_USAGE_NONE
;
1440 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1441 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1442 return ISL_AUX_USAGE_CCS_E
;
1444 /* Otherwise, we have to fall back to CCS_D */
1445 return ISL_AUX_USAGE_CCS_D
;
1448 return ISL_AUX_USAGE_NONE
;
1453 iris_resource_prepare_render(struct iris_context
*ice
,
1454 struct iris_batch
*batch
,
1455 struct iris_resource
*res
, uint32_t level
,
1456 uint32_t start_layer
, uint32_t layer_count
,
1457 enum isl_aux_usage aux_usage
)
1459 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1460 layer_count
, aux_usage
,
1461 aux_usage
!= ISL_AUX_USAGE_NONE
);
1465 iris_resource_finish_render(struct iris_context
*ice
,
1466 struct iris_resource
*res
, uint32_t level
,
1467 uint32_t start_layer
, uint32_t layer_count
,
1468 enum isl_aux_usage aux_usage
)
1470 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1475 iris_resource_prepare_depth(struct iris_context
*ice
,
1476 struct iris_batch
*batch
,
1477 struct iris_resource
*res
, uint32_t level
,
1478 uint32_t start_layer
, uint32_t layer_count
)
1480 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1481 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1485 iris_resource_finish_depth(struct iris_context
*ice
,
1486 struct iris_resource
*res
, uint32_t level
,
1487 uint32_t start_layer
, uint32_t layer_count
,
1490 if (depth_written
) {
1491 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,