2 * Copyright © 2017 Intel Corporation
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
39 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
40 * or shader image. This causes a self-dependency, where both rendering
41 * and sampling may concurrently read or write the CCS buffer, causing
45 disable_rb_aux_buffer(struct iris_context
*ice
,
46 bool *draw_aux_buffer_disabled
,
47 struct iris_resource
*tex_res
,
48 unsigned min_level
, unsigned num_levels
,
51 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
54 /* We only need to worry about color compression and fast clears. */
55 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
56 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
59 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
60 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
64 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
66 if (rb_res
->bo
== tex_res
->bo
&&
67 surf
->base
.u
.tex
.level
>= min_level
&&
68 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
69 found
= draw_aux_buffer_disabled
[i
] = true;
75 "Disabling CCS because a renderbuffer is also bound %s.\n",
83 resolve_sampler_views(struct iris_context
*ice
,
84 struct iris_batch
*batch
,
85 struct iris_shader_state
*shs
,
86 const struct shader_info
*info
,
87 bool *draw_aux_buffer_disabled
,
88 bool consider_framebuffer
)
90 uint32_t views
= info
? (shs
->bound_sampler_views
& info
->textures_used
) : 0;
92 unsigned astc5x5_wa_bits
= 0; // XXX: actual tracking
95 const int i
= u_bit_scan(&views
);
96 struct iris_sampler_view
*isv
= shs
->textures
[i
];
97 struct iris_resource
*res
= (void *) isv
->base
.texture
;
99 if (res
->base
.target
!= PIPE_BUFFER
) {
100 if (consider_framebuffer
) {
101 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
102 res
, isv
->view
.base_level
, isv
->view
.levels
,
106 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
107 isv
->view
.base_level
, isv
->view
.levels
,
108 isv
->view
.base_array_layer
,
113 iris_cache_flush_for_read(batch
, res
->bo
);
118 resolve_image_views(struct iris_context
*ice
,
119 struct iris_batch
*batch
,
120 struct iris_shader_state
*shs
,
121 bool *draw_aux_buffer_disabled
,
122 bool consider_framebuffer
)
124 /* TODO: Consider images used by program */
125 uint32_t views
= shs
->bound_image_views
;
128 const int i
= u_bit_scan(&views
);
129 struct iris_resource
*res
= (void *) shs
->image
[i
].base
.resource
;
131 if (res
->base
.target
!= PIPE_BUFFER
) {
132 if (consider_framebuffer
) {
133 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
134 res
, 0, ~0, "as a shader image");
137 iris_resource_prepare_image(ice
, batch
, res
);
140 iris_cache_flush_for_read(batch
, res
->bo
);
146 * \brief Resolve buffers before drawing.
148 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
149 * enabled depth texture, and flush the render cache for any dirty textures.
152 iris_predraw_resolve_inputs(struct iris_context
*ice
,
153 struct iris_batch
*batch
,
154 bool *draw_aux_buffer_disabled
,
155 gl_shader_stage stage
,
156 bool consider_framebuffer
)
158 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
159 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
161 uint64_t dirty
= (IRIS_DIRTY_BINDINGS_VS
<< stage
) |
162 (consider_framebuffer
? IRIS_DIRTY_BINDINGS_FS
: 0);
164 if (ice
->state
.dirty
& dirty
) {
165 resolve_sampler_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
166 consider_framebuffer
);
167 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
168 consider_framebuffer
);
175 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
176 struct iris_batch
*batch
,
177 bool *draw_aux_buffer_disabled
)
179 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
181 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
182 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
185 struct iris_resource
*z_res
, *s_res
;
186 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
187 unsigned num_layers
=
188 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
191 iris_resource_prepare_depth(ice
, batch
, z_res
,
192 zs_surf
->u
.tex
.level
,
193 zs_surf
->u
.tex
.first_layer
,
195 iris_cache_flush_for_depth(batch
, z_res
->bo
);
199 iris_cache_flush_for_depth(batch
, s_res
->bo
);
204 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
205 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
206 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
210 struct iris_resource
*res
= (void *) surf
->base
.texture
;
212 enum isl_aux_usage aux_usage
=
213 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
214 ice
->state
.blend_enables
& (1u << i
),
215 draw_aux_buffer_disabled
[i
]);
217 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
218 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
219 /* XXX: Need to track which bindings to make dirty */
220 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
223 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
224 surf
->view
.base_array_layer
,
225 surf
->view
.array_len
,
228 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
235 * \brief Call this after drawing to mark which buffers need resolving
237 * If the depth buffer was written to and if it has an accompanying HiZ
238 * buffer, then mark that it needs a depth resolve.
240 * If the color buffer is a multisample window system buffer, then
241 * mark that it needs a downsample.
243 * Also mark any render targets which will be textured as needing a render
247 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
248 struct iris_batch
*batch
)
250 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
252 // XXX: front buffer drawing?
254 bool may_have_resolved_depth
=
255 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
256 IRIS_DIRTY_WM_DEPTH_STENCIL
);
258 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
260 struct iris_resource
*z_res
, *s_res
;
261 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
262 unsigned num_layers
=
263 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
266 if (may_have_resolved_depth
) {
267 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
268 zs_surf
->u
.tex
.first_layer
, num_layers
,
269 ice
->state
.depth_writes_enabled
);
272 if (ice
->state
.depth_writes_enabled
)
273 iris_depth_cache_add_bo(batch
, z_res
->bo
);
277 if (may_have_resolved_depth
) {
278 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
279 zs_surf
->u
.tex
.first_layer
, num_layers
,
283 if (ice
->state
.stencil_writes_enabled
)
284 iris_depth_cache_add_bo(batch
, s_res
->bo
);
288 bool may_have_resolved_color
=
289 ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
);
291 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
292 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
296 struct iris_resource
*res
= (void *) surf
->base
.texture
;
297 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
299 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
,
302 if (may_have_resolved_color
) {
303 union pipe_surface_desc
*desc
= &surf
->base
.u
;
304 unsigned num_layers
=
305 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
306 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
307 desc
->tex
.first_layer
, num_layers
,
314 * Clear the cache-tracking sets.
317 iris_cache_sets_clear(struct iris_batch
*batch
)
319 hash_table_foreach(batch
->cache
.render
, render_entry
)
320 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
322 set_foreach(batch
->cache
.depth
, depth_entry
)
323 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
327 * Emits an appropriate flush for a BO if it has been rendered to within the
328 * same batchbuffer as a read that's about to be emitted.
330 * The GPU has separate, incoherent caches for the render cache and the
331 * sampler cache, along with other caches. Usually data in the different
332 * caches don't interact (e.g. we don't render to our driver-generated
333 * immediate constant data), but for render-to-texture in FBOs we definitely
334 * do. When a batchbuffer is flushed, the kernel will ensure that everything
335 * necessary is flushed before another use of that BO, but for reuse from
336 * different caches within a batchbuffer, it's all our responsibility.
339 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
341 iris_emit_pipe_control_flush(batch
,
342 "cache tracker: render-to-texture",
343 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
344 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
345 PIPE_CONTROL_CS_STALL
);
347 iris_emit_pipe_control_flush(batch
,
348 "cache tracker: render-to-texture",
349 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
350 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
352 iris_cache_sets_clear(batch
);
356 iris_cache_flush_for_read(struct iris_batch
*batch
,
359 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
360 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
361 iris_flush_depth_and_render_caches(batch
);
365 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
367 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
371 iris_cache_flush_for_render(struct iris_batch
*batch
,
373 enum isl_format format
,
374 enum isl_aux_usage aux_usage
)
376 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
377 iris_flush_depth_and_render_caches(batch
);
379 /* Check to see if this bo has been used by a previous rendering operation
380 * but with a different format or aux usage. If it has, flush the render
381 * cache so we ensure that it's only in there with one format or aux usage
384 * Even though it's not obvious, this can easily happen in practice.
385 * Suppose a client is blending on a surface with sRGB encode enabled on
386 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
387 * then disables sRGB decode and continues blending we will flip on
388 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
389 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
390 * that we have fragments in-flight which are rendering with UNORM+CCS_E
391 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
392 * same time and the pixel scoreboard and color blender are trying to sort
393 * it all out. This ends badly (i.e. GPU hangs).
395 * To date, we have never observed GPU hangs or even corruption to be
396 * associated with switching the format, only the aux usage. However,
397 * there are comments in various docs which indicate that the render cache
398 * isn't 100% resilient to format changes. We may as well be conservative
399 * and flush on format changes too. We can always relax this later if we
400 * find it to be a performance problem.
402 struct hash_entry
*entry
=
403 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
404 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
405 iris_flush_depth_and_render_caches(batch
);
409 iris_render_cache_add_bo(struct iris_batch
*batch
,
411 enum isl_format format
,
412 enum isl_aux_usage aux_usage
)
415 struct hash_entry
*entry
=
416 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
418 /* Otherwise, someone didn't do a flush_for_render and that would be
421 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
425 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
426 format_aux_tuple(format
, aux_usage
));
430 iris_cache_flush_for_depth(struct iris_batch
*batch
,
433 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
434 iris_flush_depth_and_render_caches(batch
);
438 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
440 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
444 iris_resolve_color(struct iris_context
*ice
,
445 struct iris_batch
*batch
,
446 struct iris_resource
*res
,
447 unsigned level
, unsigned layer
,
448 enum isl_aux_op resolve_op
)
450 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
452 struct blorp_surf surf
;
453 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
456 iris_batch_maybe_flush(batch
, 1500);
458 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
460 * "Any transition from any value in {Clear, Render, Resolve} to a
461 * different value in {Clear, Render, Resolve} requires end of pipe
464 * In other words, fast clear ops are not properly synchronized with
465 * other drawing. We need to use a PIPE_CONTROL to ensure that the
466 * contents of the previous draw hit the render target before we resolve
467 * and again afterwards to ensure that the resolve is complete before we
468 * do any more regular drawing.
470 iris_emit_end_of_pipe_sync(batch
, "color resolve: pre-flush",
471 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
473 struct blorp_batch blorp_batch
;
474 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
475 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
476 isl_format_srgb_to_linear(res
->surf
.format
),
478 blorp_batch_finish(&blorp_batch
);
480 /* See comment above */
481 iris_emit_end_of_pipe_sync(batch
, "color resolve: post-flush",
482 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
486 iris_mcs_partial_resolve(struct iris_context
*ice
,
487 struct iris_batch
*batch
,
488 struct iris_resource
*res
,
489 uint32_t start_layer
,
492 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
493 //start_layer, start_layer + num_layers - 1);
495 assert(res
->aux
.usage
== ISL_AUX_USAGE_MCS
);
497 struct blorp_surf surf
;
498 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
501 struct blorp_batch blorp_batch
;
502 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
503 blorp_mcs_partial_resolve(&blorp_batch
, &surf
,
504 isl_format_srgb_to_linear(res
->surf
.format
),
505 start_layer
, num_layers
);
506 blorp_batch_finish(&blorp_batch
);
511 * Return true if the format that will be used to access the resource is
512 * CCS_E-compatible with the resource's linear/non-sRGB format.
514 * Why use the linear format? Well, although the resourcemay be specified
515 * with an sRGB format, the usage of that color space/format can be toggled.
516 * Since our HW tends to support more linear formats than sRGB ones, we use
517 * this format variant for check for CCS_E compatibility.
520 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
521 const struct iris_resource
*res
,
522 enum isl_format access_format
)
524 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
526 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
527 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
531 sample_with_hiz(const struct gen_device_info
*devinfo
,
532 const struct iris_resource
*res
)
534 if (!devinfo
->has_sample_with_hiz
)
537 if (res
->aux
.usage
!= ISL_AUX_USAGE_HIZ
)
540 /* It seems the hardware won't fallback to the depth buffer if some of the
541 * mipmap levels aren't available in the HiZ buffer. So we need all levels
542 * of the texture to be HiZ enabled.
544 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
545 if (!iris_resource_level_has_hiz(res
, level
))
549 /* If compressed multisampling is enabled, then we use it for the auxiliary
552 * From the BDW PRM (Volume 2d: Command Reference: Structures
553 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
555 * "If this field is set to AUX_HIZ, Number of Multisamples must be
556 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
558 * There is no such blurb for 1D textures, but there is sufficient evidence
559 * that this is broken on SKL+.
561 // XXX: i965 disables this for arrays too, is that reasonable?
562 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
566 * Perform a HiZ or depth resolve operation.
568 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
569 * PRM, Volume 1, Part 2:
570 * - 7.5.3.1 Depth Buffer Clear
571 * - 7.5.3.2 Depth Buffer Resolve
572 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
575 iris_hiz_exec(struct iris_context
*ice
,
576 struct iris_batch
*batch
,
577 struct iris_resource
*res
,
578 unsigned int level
, unsigned int start_layer
,
579 unsigned int num_layers
, enum isl_aux_op op
,
580 bool update_clear_depth
)
582 assert(iris_resource_level_has_hiz(res
, level
));
583 assert(op
!= ISL_AUX_OP_NONE
);
584 UNUSED
const char *name
= NULL
;
587 case ISL_AUX_OP_FULL_RESOLVE
:
588 name
= "depth resolve";
590 case ISL_AUX_OP_AMBIGUATE
:
591 name
= "hiz ambiguate";
593 case ISL_AUX_OP_FAST_CLEAR
:
594 name
= "depth clear";
596 case ISL_AUX_OP_PARTIAL_RESOLVE
:
597 case ISL_AUX_OP_NONE
:
598 unreachable("Invalid HiZ op");
601 //DBG("%s %s to mt %p level %d layers %d-%d\n",
602 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
604 /* The following stalls and flushes are only documented to be required
605 * for HiZ clear operations. However, they also seem to be required for
606 * resolve operations.
608 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
610 * "If other rendering operations have preceded this clear, a
611 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
612 * enabled must be issued before the rectangle primitive used for
613 * the depth buffer clear operation."
615 * Same applies for Gen8 and Gen9.
617 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
618 * PIPE_CONTROL, Depth Cache Flush Enable:
620 * "This bit must not be set when Depth Stall Enable bit is set in
623 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
625 * Therefore issue two pipe control flushes, one for cache flush and
626 * another for depth stall.
628 iris_emit_pipe_control_flush(batch
,
629 "hiz op: pre-flushes (1/2)",
630 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
631 PIPE_CONTROL_CS_STALL
);
633 iris_emit_pipe_control_flush(batch
, "hiz op: pre-flushes (2/2)",
634 PIPE_CONTROL_DEPTH_STALL
);
636 assert(res
->aux
.usage
== ISL_AUX_USAGE_HIZ
&& res
->aux
.bo
);
638 iris_batch_maybe_flush(batch
, 1500);
640 struct blorp_surf surf
;
641 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
,
642 ISL_AUX_USAGE_HIZ
, level
, true);
644 struct blorp_batch blorp_batch
;
645 enum blorp_batch_flags flags
= 0;
646 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
647 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
648 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
649 blorp_batch_finish(&blorp_batch
);
651 /* The following stalls and flushes are only documented to be required
652 * for HiZ clear operations. However, they also seem to be required for
653 * resolve operations.
655 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
657 * "Depth buffer clear pass using any of the methods (WM_STATE,
658 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
659 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
660 * "set" before starting to render. DepthStall and DepthFlush are
661 * not needed between consecutive depth clear passes nor is it
662 * required if the depth clear pass was done with
663 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
665 * TODO: Such as the spec says, this could be conditional.
667 iris_emit_pipe_control_flush(batch
,
668 "hiz op: post flush",
669 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
670 PIPE_CONTROL_DEPTH_STALL
);
674 * Does the resource's slice have hiz enabled?
677 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
679 iris_resource_check_level_layer(res
, level
, 0);
680 return res
->aux
.has_hiz
& 1 << level
;
683 /** \brief Assert that the level and layer are valid for the resource. */
685 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
686 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
688 assert(level
< res
->surf
.levels
);
689 assert(layer
< util_num_layers(&res
->base
, level
));
692 static inline uint32_t
693 miptree_level_range_length(const struct iris_resource
*res
,
694 uint32_t start_level
, uint32_t num_levels
)
696 assert(start_level
< res
->surf
.levels
);
698 if (num_levels
== INTEL_REMAINING_LAYERS
)
699 num_levels
= res
->surf
.levels
;
701 /* Check for overflow */
702 assert(start_level
+ num_levels
>= start_level
);
703 assert(start_level
+ num_levels
<= res
->surf
.levels
);
708 static inline uint32_t
709 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
710 uint32_t start_layer
, uint32_t num_layers
)
712 assert(level
<= res
->base
.last_level
);
714 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
715 assert(start_layer
< total_num_layers
);
716 if (num_layers
== INTEL_REMAINING_LAYERS
)
717 num_layers
= total_num_layers
- start_layer
;
718 /* Check for overflow */
719 assert(start_layer
+ num_layers
>= start_layer
);
720 assert(start_layer
+ num_layers
<= total_num_layers
);
726 iris_has_color_unresolved(const struct iris_resource
*res
,
727 unsigned start_level
, unsigned num_levels
,
728 unsigned start_layer
, unsigned num_layers
)
733 /* Clamp the level range to fit the resource */
734 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
736 for (uint32_t l
= 0; l
< num_levels
; l
++) {
737 const uint32_t level
= start_level
+ l
;
738 const uint32_t level_layers
=
739 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
740 for (unsigned a
= 0; a
< level_layers
; a
++) {
741 enum isl_aux_state aux_state
=
742 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
743 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
744 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
752 static enum isl_aux_op
753 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
754 enum isl_aux_usage aux_usage
,
755 bool fast_clear_supported
)
757 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
759 const bool ccs_supported
=
760 (aux_usage
== ISL_AUX_USAGE_CCS_D
) && fast_clear_supported
;
763 case ISL_AUX_STATE_CLEAR
:
764 case ISL_AUX_STATE_PARTIAL_CLEAR
:
766 return ISL_AUX_OP_FULL_RESOLVE
;
768 return ISL_AUX_OP_NONE
;
770 case ISL_AUX_STATE_PASS_THROUGH
:
771 return ISL_AUX_OP_NONE
;
773 case ISL_AUX_STATE_RESOLVED
:
774 case ISL_AUX_STATE_AUX_INVALID
:
775 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
776 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
780 unreachable("Invalid aux state for CCS_D");
783 static enum isl_aux_op
784 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
785 enum isl_aux_usage aux_usage
,
786 bool fast_clear_supported
)
788 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
789 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
790 aux_usage
== ISL_AUX_USAGE_CCS_D
||
791 aux_usage
== ISL_AUX_USAGE_CCS_E
);
794 case ISL_AUX_STATE_CLEAR
:
795 case ISL_AUX_STATE_PARTIAL_CLEAR
:
796 if (fast_clear_supported
)
797 return ISL_AUX_OP_NONE
;
798 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
799 return ISL_AUX_OP_PARTIAL_RESOLVE
;
801 return ISL_AUX_OP_FULL_RESOLVE
;
803 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
804 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
805 return ISL_AUX_OP_FULL_RESOLVE
;
806 else if (!fast_clear_supported
)
807 return ISL_AUX_OP_PARTIAL_RESOLVE
;
809 return ISL_AUX_OP_NONE
;
811 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
812 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
813 return ISL_AUX_OP_FULL_RESOLVE
;
815 return ISL_AUX_OP_NONE
;
817 case ISL_AUX_STATE_PASS_THROUGH
:
818 return ISL_AUX_OP_NONE
;
820 case ISL_AUX_STATE_RESOLVED
:
821 case ISL_AUX_STATE_AUX_INVALID
:
825 unreachable("Invalid aux state for CCS_E");
829 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
830 struct iris_batch
*batch
,
831 struct iris_resource
*res
,
832 uint32_t level
, uint32_t layer
,
833 enum isl_aux_usage aux_usage
,
834 bool fast_clear_supported
)
836 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
838 enum isl_aux_op resolve_op
;
839 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
840 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
841 fast_clear_supported
);
843 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
844 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
845 fast_clear_supported
);
848 if (resolve_op
!= ISL_AUX_OP_NONE
) {
849 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
851 switch (resolve_op
) {
852 case ISL_AUX_OP_FULL_RESOLVE
:
853 /* The CCS full resolve operation destroys the CCS and sets it to the
854 * pass-through state. (You can also think of this as being both a
855 * resolve and an ambiguate in one operation.)
857 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
858 ISL_AUX_STATE_PASS_THROUGH
);
861 case ISL_AUX_OP_PARTIAL_RESOLVE
:
862 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
863 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
867 unreachable("Invalid resolve op");
873 iris_resource_finish_ccs_write(struct iris_context
*ice
,
874 struct iris_resource
*res
,
875 uint32_t level
, uint32_t layer
,
876 enum isl_aux_usage aux_usage
)
878 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
879 aux_usage
== ISL_AUX_USAGE_CCS_D
||
880 aux_usage
== ISL_AUX_USAGE_CCS_E
);
882 enum isl_aux_state aux_state
=
883 iris_resource_get_aux_state(res
, level
, layer
);
885 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
887 case ISL_AUX_STATE_CLEAR
:
888 case ISL_AUX_STATE_PARTIAL_CLEAR
:
889 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
890 aux_usage
== ISL_AUX_USAGE_CCS_D
);
892 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
893 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
894 ISL_AUX_STATE_COMPRESSED_CLEAR
);
895 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
896 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
897 ISL_AUX_STATE_PARTIAL_CLEAR
);
901 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
902 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
903 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
904 break; /* Nothing to do */
906 case ISL_AUX_STATE_PASS_THROUGH
:
907 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
908 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
909 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
915 case ISL_AUX_STATE_RESOLVED
:
916 case ISL_AUX_STATE_AUX_INVALID
:
917 unreachable("Invalid aux state for CCS_E");
920 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
921 /* CCS_D is a bit simpler */
923 case ISL_AUX_STATE_CLEAR
:
924 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
925 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
926 ISL_AUX_STATE_PARTIAL_CLEAR
);
929 case ISL_AUX_STATE_PARTIAL_CLEAR
:
930 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
931 break; /* Nothing to do */
933 case ISL_AUX_STATE_PASS_THROUGH
:
937 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
938 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
939 case ISL_AUX_STATE_RESOLVED
:
940 case ISL_AUX_STATE_AUX_INVALID
:
941 unreachable("Invalid aux state for CCS_D");
947 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
948 struct iris_batch
*batch
,
949 struct iris_resource
*res
,
951 enum isl_aux_usage aux_usage
,
952 bool fast_clear_supported
)
954 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
956 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
957 case ISL_AUX_STATE_CLEAR
:
958 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
959 if (!fast_clear_supported
) {
960 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
961 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
962 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
966 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
967 break; /* Nothing to do */
969 case ISL_AUX_STATE_RESOLVED
:
970 case ISL_AUX_STATE_PASS_THROUGH
:
971 case ISL_AUX_STATE_AUX_INVALID
:
972 case ISL_AUX_STATE_PARTIAL_CLEAR
:
973 unreachable("Invalid aux state for MCS");
978 iris_resource_finish_mcs_write(struct iris_context
*ice
,
979 struct iris_resource
*res
,
981 enum isl_aux_usage aux_usage
)
983 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
985 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
986 case ISL_AUX_STATE_CLEAR
:
987 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
988 ISL_AUX_STATE_COMPRESSED_CLEAR
);
991 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
992 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
993 break; /* Nothing to do */
995 case ISL_AUX_STATE_RESOLVED
:
996 case ISL_AUX_STATE_PASS_THROUGH
:
997 case ISL_AUX_STATE_AUX_INVALID
:
998 case ISL_AUX_STATE_PARTIAL_CLEAR
:
999 unreachable("Invalid aux state for MCS");
1004 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
1005 struct iris_batch
*batch
,
1006 struct iris_resource
*res
,
1007 uint32_t level
, uint32_t layer
,
1008 enum isl_aux_usage aux_usage
,
1009 bool fast_clear_supported
)
1011 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1013 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
1014 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1015 case ISL_AUX_STATE_CLEAR
:
1016 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1017 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
1018 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1021 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1022 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
1023 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1026 case ISL_AUX_STATE_PASS_THROUGH
:
1027 case ISL_AUX_STATE_RESOLVED
:
1030 case ISL_AUX_STATE_AUX_INVALID
:
1031 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1032 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
1035 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1036 unreachable("Invalid HiZ state");
1039 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1040 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
, false);
1043 case ISL_AUX_OP_FULL_RESOLVE
:
1044 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1045 ISL_AUX_STATE_RESOLVED
);
1048 case ISL_AUX_OP_AMBIGUATE
:
1049 /* The HiZ resolve operation is actually an ambiguate */
1050 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1051 ISL_AUX_STATE_PASS_THROUGH
);
1055 unreachable("Invalid HiZ op");
1061 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1062 struct iris_resource
*res
,
1063 uint32_t level
, uint32_t layer
,
1064 enum isl_aux_usage aux_usage
)
1066 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1068 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1069 case ISL_AUX_STATE_CLEAR
:
1070 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1071 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1072 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1075 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1076 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1077 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1078 break; /* Nothing to do */
1080 case ISL_AUX_STATE_RESOLVED
:
1081 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1082 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1083 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1085 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1086 ISL_AUX_STATE_AUX_INVALID
);
1090 case ISL_AUX_STATE_PASS_THROUGH
:
1091 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1092 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1093 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1097 case ISL_AUX_STATE_AUX_INVALID
:
1098 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
1101 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1102 unreachable("Invalid HiZ state");
1107 iris_resource_prepare_access(struct iris_context
*ice
,
1108 struct iris_batch
*batch
,
1109 struct iris_resource
*res
,
1110 uint32_t start_level
, uint32_t num_levels
,
1111 uint32_t start_layer
, uint32_t num_layers
,
1112 enum isl_aux_usage aux_usage
,
1113 bool fast_clear_supported
)
1115 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1117 switch (res
->aux
.usage
) {
1118 case ISL_AUX_USAGE_NONE
:
1122 case ISL_AUX_USAGE_MCS
:
1123 assert(start_level
== 0 && num_levels
== 1);
1124 const uint32_t level_layers
=
1125 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1126 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1127 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1128 aux_usage
, fast_clear_supported
);
1132 case ISL_AUX_USAGE_CCS_D
:
1133 case ISL_AUX_USAGE_CCS_E
:
1134 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1135 const uint32_t level
= start_level
+ l
;
1136 const uint32_t level_layers
=
1137 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1138 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1139 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1141 aux_usage
, fast_clear_supported
);
1146 case ISL_AUX_USAGE_HIZ
:
1147 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1148 const uint32_t level
= start_level
+ l
;
1149 if (!iris_resource_level_has_hiz(res
, level
))
1152 const uint32_t level_layers
=
1153 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1154 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1155 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1156 start_layer
+ a
, aux_usage
,
1157 fast_clear_supported
);
1163 unreachable("Invalid aux usage");
1168 iris_resource_finish_write(struct iris_context
*ice
,
1169 struct iris_resource
*res
, uint32_t level
,
1170 uint32_t start_layer
, uint32_t num_layers
,
1171 enum isl_aux_usage aux_usage
)
1173 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1175 switch (res
->aux
.usage
) {
1176 case ISL_AUX_USAGE_NONE
:
1179 case ISL_AUX_USAGE_MCS
:
1180 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1181 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1186 case ISL_AUX_USAGE_CCS_D
:
1187 case ISL_AUX_USAGE_CCS_E
:
1188 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1189 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1194 case ISL_AUX_USAGE_HIZ
:
1195 if (!iris_resource_level_has_hiz(res
, level
))
1198 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1199 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1205 unreachable("Invavlid aux usage");
1210 iris_resource_get_aux_state(const struct iris_resource
*res
,
1211 uint32_t level
, uint32_t layer
)
1213 iris_resource_check_level_layer(res
, level
, layer
);
1215 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1216 assert(iris_resource_level_has_hiz(res
, level
));
1217 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1218 unreachable("Cannot get aux state for stencil");
1220 assert(res
->surf
.samples
== 1 ||
1221 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1224 return res
->aux
.state
[level
][layer
];
1228 iris_resource_set_aux_state(struct iris_context
*ice
,
1229 struct iris_resource
*res
, uint32_t level
,
1230 uint32_t start_layer
, uint32_t num_layers
,
1231 enum isl_aux_state aux_state
)
1233 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1235 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1236 assert(iris_resource_level_has_hiz(res
, level
));
1237 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1238 unreachable("Cannot set aux state for stencil");
1240 assert(res
->surf
.samples
== 1 ||
1241 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1244 for (unsigned a
= 0; a
< num_layers
; a
++) {
1245 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1246 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1247 /* XXX: Need to track which bindings to make dirty */
1248 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1253 /* On Gen9 color buffers may be compressed by the hardware (lossless
1254 * compression). There are, however, format restrictions and care needs to be
1255 * taken that the sampler engine is capable for re-interpreting a buffer with
1256 * format different the buffer was originally written with.
1258 * For example, SRGB formats are not compressible and the sampler engine isn't
1259 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1260 * color buffer needs to be resolved so that the sampling surface can be
1261 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1265 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1266 struct pipe_debug_callback
*dbg
,
1267 const struct iris_resource
*res
,
1268 enum isl_format view_format
)
1270 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1273 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1274 const struct isl_format_layout
*res_fmtl
=
1275 isl_format_get_layout(res
->surf
.format
);
1276 const struct isl_format_layout
*view_fmtl
=
1277 isl_format_get_layout(view_format
);
1279 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1280 view_fmtl
->name
, res_fmtl
->name
);
1289 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1290 const struct iris_resource
*res
,
1291 enum isl_format view_format
,
1292 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1294 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1295 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1297 assert(devinfo
->gen
== 9 || astc5x5_wa_bits
== 0);
1299 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
1300 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
1303 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
1304 res
->aux
.usage
!= ISL_AUX_USAGE_MCS
)
1305 return ISL_AUX_USAGE_NONE
;
1307 switch (res
->aux
.usage
) {
1308 case ISL_AUX_USAGE_HIZ
:
1309 if (sample_with_hiz(devinfo
, res
))
1310 return ISL_AUX_USAGE_HIZ
;
1313 case ISL_AUX_USAGE_MCS
:
1314 return ISL_AUX_USAGE_MCS
;
1316 case ISL_AUX_USAGE_CCS_D
:
1317 case ISL_AUX_USAGE_CCS_E
:
1318 /* If we don't have any unresolved color, report an aux usage of
1319 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1320 * aux surface and we can save some bandwidth.
1322 if (!iris_has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1323 0, INTEL_REMAINING_LAYERS
))
1324 return ISL_AUX_USAGE_NONE
;
1326 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1327 return ISL_AUX_USAGE_CCS_E
;
1334 return ISL_AUX_USAGE_NONE
;
1338 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1340 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1341 * values so sRGB curve application was a no-op for all fast-clearable
1344 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1345 * values, the hardware interprets the floats, not as what would be
1346 * returned from the sampler (or written by the shader), but as being
1347 * between format conversion and sRGB curve application. This means that
1348 * we can switch between sRGB and UNORM without having to whack the clear
1351 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1355 iris_resource_prepare_texture(struct iris_context
*ice
,
1356 struct iris_batch
*batch
,
1357 struct iris_resource
*res
,
1358 enum isl_format view_format
,
1359 uint32_t start_level
, uint32_t num_levels
,
1360 uint32_t start_layer
, uint32_t num_layers
,
1361 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1363 enum isl_aux_usage aux_usage
=
1364 iris_resource_texture_aux_usage(ice
, res
, view_format
, astc5x5_wa_bits
);
1366 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1368 /* Clear color is specified as ints or floats and the conversion is done by
1369 * the sampler. If we have a texture view, we would have to perform the
1370 * clear color conversion manually. Just disable clear color.
1372 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1373 clear_supported
= false;
1375 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1376 start_layer
, num_layers
,
1377 aux_usage
, clear_supported
);
1381 iris_resource_prepare_image(struct iris_context
*ice
,
1382 struct iris_batch
*batch
,
1383 struct iris_resource
*res
)
1385 /* The data port doesn't understand any compression */
1386 iris_resource_prepare_access(ice
, batch
, res
, 0, INTEL_REMAINING_LEVELS
,
1387 0, INTEL_REMAINING_LAYERS
,
1388 ISL_AUX_USAGE_NONE
, false);
1392 iris_resource_render_aux_usage(struct iris_context
*ice
,
1393 struct iris_resource
*res
,
1394 enum isl_format render_format
,
1396 bool draw_aux_disabled
)
1398 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1399 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1401 if (draw_aux_disabled
)
1402 return ISL_AUX_USAGE_NONE
;
1404 switch (res
->aux
.usage
) {
1405 case ISL_AUX_USAGE_MCS
:
1406 return ISL_AUX_USAGE_MCS
;
1408 case ISL_AUX_USAGE_CCS_D
:
1409 case ISL_AUX_USAGE_CCS_E
:
1410 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1411 * formats. However, there are issues with blending where it doesn't
1412 * properly apply the sRGB curve to the clear color when blending.
1414 if (devinfo
->gen
>= 9 && blend_enabled
&&
1415 isl_format_is_srgb(render_format
) &&
1416 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1417 return ISL_AUX_USAGE_NONE
;
1419 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1420 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1421 return ISL_AUX_USAGE_CCS_E
;
1423 /* Otherwise, we have to fall back to CCS_D */
1424 return ISL_AUX_USAGE_CCS_D
;
1427 return ISL_AUX_USAGE_NONE
;
1432 iris_resource_prepare_render(struct iris_context
*ice
,
1433 struct iris_batch
*batch
,
1434 struct iris_resource
*res
, uint32_t level
,
1435 uint32_t start_layer
, uint32_t layer_count
,
1436 enum isl_aux_usage aux_usage
)
1438 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1439 layer_count
, aux_usage
,
1440 aux_usage
!= ISL_AUX_USAGE_NONE
);
1444 iris_resource_finish_render(struct iris_context
*ice
,
1445 struct iris_resource
*res
, uint32_t level
,
1446 uint32_t start_layer
, uint32_t layer_count
,
1447 enum isl_aux_usage aux_usage
)
1449 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1454 iris_resource_prepare_depth(struct iris_context
*ice
,
1455 struct iris_batch
*batch
,
1456 struct iris_resource
*res
, uint32_t level
,
1457 uint32_t start_layer
, uint32_t layer_count
)
1459 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1460 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1464 iris_resource_finish_depth(struct iris_context
*ice
,
1465 struct iris_resource
*res
, uint32_t level
,
1466 uint32_t start_layer
, uint32_t layer_count
,
1469 if (depth_written
) {
1470 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,