2 * Copyright © 2017 Intel Corporation
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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
37 #include "compiler/nir/nir.h"
40 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
41 * or shader image. This causes a self-dependency, where both rendering
42 * and sampling may concurrently read or write the CCS buffer, causing
46 disable_rb_aux_buffer(struct iris_context
*ice
,
47 bool *draw_aux_buffer_disabled
,
48 struct iris_resource
*tex_res
,
49 unsigned min_level
, unsigned num_levels
,
52 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
55 /* We only need to worry about color compression and fast clears. */
56 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
57 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
60 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
61 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
65 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
67 if (rb_res
->bo
== tex_res
->bo
&&
68 surf
->base
.u
.tex
.level
>= min_level
&&
69 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
70 found
= draw_aux_buffer_disabled
[i
] = true;
76 "Disabling CCS because a renderbuffer is also bound %s.\n",
84 resolve_sampler_views(struct iris_context
*ice
,
85 struct iris_batch
*batch
,
86 struct iris_shader_state
*shs
,
87 const struct shader_info
*info
,
88 bool *draw_aux_buffer_disabled
,
89 bool consider_framebuffer
)
91 uint32_t views
= info
? (shs
->bound_sampler_views
& info
->textures_used
) : 0;
94 const int i
= u_bit_scan(&views
);
95 struct iris_sampler_view
*isv
= shs
->textures
[i
];
96 struct iris_resource
*res
= (void *) isv
->base
.texture
;
98 if (res
->base
.target
!= PIPE_BUFFER
) {
99 if (consider_framebuffer
) {
100 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
101 res
, isv
->view
.base_level
, isv
->view
.levels
,
105 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
106 isv
->view
.base_level
, isv
->view
.levels
,
107 isv
->view
.base_array_layer
,
108 isv
->view
.array_len
);
111 iris_cache_flush_for_read(batch
, res
->bo
);
116 resolve_image_views(struct iris_context
*ice
,
117 struct iris_batch
*batch
,
118 struct iris_shader_state
*shs
,
119 bool *draw_aux_buffer_disabled
,
120 bool consider_framebuffer
)
122 /* TODO: Consider images used by program */
123 uint32_t views
= shs
->bound_image_views
;
126 const int i
= u_bit_scan(&views
);
127 struct pipe_image_view
*pview
= &shs
->image
[i
].base
;
128 struct iris_resource
*res
= (void *) pview
->resource
;
130 if (res
->base
.target
!= PIPE_BUFFER
) {
131 if (consider_framebuffer
) {
132 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
133 res
, pview
->u
.tex
.level
, 1,
134 "as a shader image");
137 unsigned num_layers
=
138 pview
->u
.tex
.last_layer
- pview
->u
.tex
.first_layer
+ 1;
140 /* The data port doesn't understand any compression */
141 iris_resource_prepare_access(ice
, batch
, res
,
142 pview
->u
.tex
.level
, 1,
143 pview
->u
.tex
.first_layer
, num_layers
,
144 ISL_AUX_USAGE_NONE
, false);
147 iris_cache_flush_for_read(batch
, res
->bo
);
153 * \brief Resolve buffers before drawing.
155 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
156 * enabled depth texture, and flush the render cache for any dirty textures.
159 iris_predraw_resolve_inputs(struct iris_context
*ice
,
160 struct iris_batch
*batch
,
161 bool *draw_aux_buffer_disabled
,
162 gl_shader_stage stage
,
163 bool consider_framebuffer
)
165 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
166 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
168 uint64_t dirty
= (IRIS_DIRTY_BINDINGS_VS
<< stage
) |
169 (consider_framebuffer
? IRIS_DIRTY_BINDINGS_FS
: 0);
171 if (ice
->state
.dirty
& dirty
) {
172 resolve_sampler_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
173 consider_framebuffer
);
174 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
175 consider_framebuffer
);
180 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
181 struct iris_batch
*batch
,
182 bool *draw_aux_buffer_disabled
)
184 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
185 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
186 struct gen_device_info
*devinfo
= &screen
->devinfo
;
187 struct iris_uncompiled_shader
*ish
=
188 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
189 const nir_shader
*nir
= ish
->nir
;
191 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
192 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
195 struct iris_resource
*z_res
, *s_res
;
196 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
197 unsigned num_layers
=
198 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
201 iris_resource_prepare_depth(ice
, batch
, z_res
,
202 zs_surf
->u
.tex
.level
,
203 zs_surf
->u
.tex
.first_layer
,
205 iris_cache_flush_for_depth(batch
, z_res
->bo
);
209 iris_cache_flush_for_depth(batch
, s_res
->bo
);
214 if (devinfo
->gen
== 8 && nir
->info
.outputs_read
!= 0) {
215 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
216 if (cso_fb
->cbufs
[i
]) {
217 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
218 struct iris_resource
*res
= (void *) cso_fb
->cbufs
[i
]->texture
;
220 iris_resource_prepare_texture(ice
, batch
, res
, surf
->view
.format
,
221 surf
->view
.base_level
, 1,
222 surf
->view
.base_array_layer
,
223 surf
->view
.array_len
);
228 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
229 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
230 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
234 struct iris_resource
*res
= (void *) surf
->base
.texture
;
236 enum isl_aux_usage aux_usage
=
237 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
238 ice
->state
.blend_enables
& (1u << i
),
239 draw_aux_buffer_disabled
[i
]);
241 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
242 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
243 /* XXX: Need to track which bindings to make dirty */
244 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
247 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
248 surf
->view
.base_array_layer
,
249 surf
->view
.array_len
,
252 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
259 * \brief Call this after drawing to mark which buffers need resolving
261 * If the depth buffer was written to and if it has an accompanying HiZ
262 * buffer, then mark that it needs a depth resolve.
264 * If the color buffer is a multisample window system buffer, then
265 * mark that it needs a downsample.
267 * Also mark any render targets which will be textured as needing a render
271 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
272 struct iris_batch
*batch
)
274 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
276 // XXX: front buffer drawing?
278 bool may_have_resolved_depth
=
279 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
280 IRIS_DIRTY_WM_DEPTH_STENCIL
);
282 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
284 struct iris_resource
*z_res
, *s_res
;
285 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
286 unsigned num_layers
=
287 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
290 if (may_have_resolved_depth
) {
291 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
292 zs_surf
->u
.tex
.first_layer
, num_layers
,
293 ice
->state
.depth_writes_enabled
);
296 if (ice
->state
.depth_writes_enabled
)
297 iris_depth_cache_add_bo(batch
, z_res
->bo
);
301 if (may_have_resolved_depth
&& ice
->state
.stencil_writes_enabled
) {
302 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
303 zs_surf
->u
.tex
.first_layer
, num_layers
,
307 if (ice
->state
.stencil_writes_enabled
)
308 iris_depth_cache_add_bo(batch
, s_res
->bo
);
312 bool may_have_resolved_color
=
313 ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
);
315 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
316 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
320 struct iris_resource
*res
= (void *) surf
->base
.texture
;
321 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
323 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
,
326 if (may_have_resolved_color
) {
327 union pipe_surface_desc
*desc
= &surf
->base
.u
;
328 unsigned num_layers
=
329 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
330 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
331 desc
->tex
.first_layer
, num_layers
,
338 * Clear the cache-tracking sets.
341 iris_cache_sets_clear(struct iris_batch
*batch
)
343 hash_table_foreach(batch
->cache
.render
, render_entry
)
344 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
346 set_foreach(batch
->cache
.depth
, depth_entry
)
347 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
351 * Emits an appropriate flush for a BO if it has been rendered to within the
352 * same batchbuffer as a read that's about to be emitted.
354 * The GPU has separate, incoherent caches for the render cache and the
355 * sampler cache, along with other caches. Usually data in the different
356 * caches don't interact (e.g. we don't render to our driver-generated
357 * immediate constant data), but for render-to-texture in FBOs we definitely
358 * do. When a batchbuffer is flushed, the kernel will ensure that everything
359 * necessary is flushed before another use of that BO, but for reuse from
360 * different caches within a batchbuffer, it's all our responsibility.
363 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
365 iris_emit_pipe_control_flush(batch
,
366 "cache tracker: render-to-texture",
367 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
368 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
369 PIPE_CONTROL_CS_STALL
);
371 iris_emit_pipe_control_flush(batch
,
372 "cache tracker: render-to-texture",
373 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
374 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
376 iris_cache_sets_clear(batch
);
380 iris_cache_flush_for_read(struct iris_batch
*batch
,
383 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
384 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
385 iris_flush_depth_and_render_caches(batch
);
389 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
391 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
395 iris_cache_flush_for_render(struct iris_batch
*batch
,
397 enum isl_format format
,
398 enum isl_aux_usage aux_usage
)
400 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
401 iris_flush_depth_and_render_caches(batch
);
403 /* Check to see if this bo has been used by a previous rendering operation
404 * but with a different format or aux usage. If it has, flush the render
405 * cache so we ensure that it's only in there with one format or aux usage
408 * Even though it's not obvious, this can easily happen in practice.
409 * Suppose a client is blending on a surface with sRGB encode enabled on
410 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
411 * then disables sRGB decode and continues blending we will flip on
412 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
413 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
414 * that we have fragments in-flight which are rendering with UNORM+CCS_E
415 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
416 * same time and the pixel scoreboard and color blender are trying to sort
417 * it all out. This ends badly (i.e. GPU hangs).
419 * To date, we have never observed GPU hangs or even corruption to be
420 * associated with switching the format, only the aux usage. However,
421 * there are comments in various docs which indicate that the render cache
422 * isn't 100% resilient to format changes. We may as well be conservative
423 * and flush on format changes too. We can always relax this later if we
424 * find it to be a performance problem.
426 struct hash_entry
*entry
=
427 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
428 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
429 iris_flush_depth_and_render_caches(batch
);
433 iris_render_cache_add_bo(struct iris_batch
*batch
,
435 enum isl_format format
,
436 enum isl_aux_usage aux_usage
)
439 struct hash_entry
*entry
=
440 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
442 /* Otherwise, someone didn't do a flush_for_render and that would be
445 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
449 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
450 format_aux_tuple(format
, aux_usage
));
454 iris_cache_flush_for_depth(struct iris_batch
*batch
,
457 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
458 iris_flush_depth_and_render_caches(batch
);
462 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
464 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
468 iris_resolve_color(struct iris_context
*ice
,
469 struct iris_batch
*batch
,
470 struct iris_resource
*res
,
471 unsigned level
, unsigned layer
,
472 enum isl_aux_op resolve_op
)
474 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
476 struct blorp_surf surf
;
477 iris_blorp_surf_for_resource(&ice
->vtbl
, &batch
->screen
->isl_dev
, &surf
,
478 &res
->base
, res
->aux
.usage
, level
, true);
480 iris_batch_maybe_flush(batch
, 1500);
482 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
484 * "Any transition from any value in {Clear, Render, Resolve} to a
485 * different value in {Clear, Render, Resolve} requires end of pipe
488 * In other words, fast clear ops are not properly synchronized with
489 * other drawing. We need to use a PIPE_CONTROL to ensure that the
490 * contents of the previous draw hit the render target before we resolve
491 * and again afterwards to ensure that the resolve is complete before we
492 * do any more regular drawing.
494 iris_emit_end_of_pipe_sync(batch
, "color resolve: pre-flush",
495 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
497 struct blorp_batch blorp_batch
;
498 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
499 /* On Gen >= 12, Stencil buffer with lossless compression needs to be
500 * resolve with WM_HZ_OP packet.
502 if (isl_surf_usage_is_stencil(res
->surf
.usage
)) {
503 blorp_hiz_stencil_op(&blorp_batch
, &surf
, level
, layer
,
506 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
507 isl_format_srgb_to_linear(res
->surf
.format
),
510 blorp_batch_finish(&blorp_batch
);
512 /* See comment above */
513 iris_emit_end_of_pipe_sync(batch
, "color resolve: post-flush",
514 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
518 iris_mcs_partial_resolve(struct iris_context
*ice
,
519 struct iris_batch
*batch
,
520 struct iris_resource
*res
,
521 uint32_t start_layer
,
524 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
525 //start_layer, start_layer + num_layers - 1);
527 assert(isl_aux_usage_has_mcs(res
->aux
.usage
));
529 struct blorp_surf surf
;
530 iris_blorp_surf_for_resource(&ice
->vtbl
, &batch
->screen
->isl_dev
, &surf
,
531 &res
->base
, res
->aux
.usage
, 0, true);
533 struct blorp_batch blorp_batch
;
534 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
535 blorp_mcs_partial_resolve(&blorp_batch
, &surf
,
536 isl_format_srgb_to_linear(res
->surf
.format
),
537 start_layer
, num_layers
);
538 blorp_batch_finish(&blorp_batch
);
543 * Return true if the format that will be used to access the resource is
544 * CCS_E-compatible with the resource's linear/non-sRGB format.
546 * Why use the linear format? Well, although the resourcemay be specified
547 * with an sRGB format, the usage of that color space/format can be toggled.
548 * Since our HW tends to support more linear formats than sRGB ones, we use
549 * this format variant for check for CCS_E compatibility.
552 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
553 const struct iris_resource
*res
,
554 enum isl_format access_format
)
556 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
558 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
559 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
563 sample_with_depth_aux(const struct gen_device_info
*devinfo
,
564 const struct iris_resource
*res
)
566 switch (res
->aux
.usage
) {
567 case ISL_AUX_USAGE_HIZ
:
568 if (devinfo
->has_sample_with_hiz
)
571 case ISL_AUX_USAGE_HIZ_CCS
:
572 /* Write through mode must have been enabled for prior writes. */
573 if (isl_surf_supports_hiz_ccs_wt(devinfo
, &res
->surf
, res
->aux
.usage
))
580 /* It seems the hardware won't fallback to the depth buffer if some of the
581 * mipmap levels aren't available in the HiZ buffer. So we need all levels
582 * of the texture to be HiZ enabled.
584 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
585 if (!iris_resource_level_has_hiz(res
, level
))
589 /* If compressed multisampling is enabled, then we use it for the auxiliary
592 * From the BDW PRM (Volume 2d: Command Reference: Structures
593 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
595 * "If this field is set to AUX_HIZ, Number of Multisamples must be
596 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
598 * There is no such blurb for 1D textures, but there is sufficient evidence
599 * that this is broken on SKL+.
601 // XXX: i965 disables this for arrays too, is that reasonable?
602 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
606 * Perform a HiZ or depth resolve operation.
608 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
609 * PRM, Volume 1, Part 2:
610 * - 7.5.3.1 Depth Buffer Clear
611 * - 7.5.3.2 Depth Buffer Resolve
612 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
615 iris_hiz_exec(struct iris_context
*ice
,
616 struct iris_batch
*batch
,
617 struct iris_resource
*res
,
618 unsigned int level
, unsigned int start_layer
,
619 unsigned int num_layers
, enum isl_aux_op op
,
620 bool update_clear_depth
)
622 assert(iris_resource_level_has_hiz(res
, level
));
623 assert(op
!= ISL_AUX_OP_NONE
);
624 UNUSED
const char *name
= NULL
;
627 case ISL_AUX_OP_FULL_RESOLVE
:
628 name
= "depth resolve";
630 case ISL_AUX_OP_AMBIGUATE
:
631 name
= "hiz ambiguate";
633 case ISL_AUX_OP_FAST_CLEAR
:
634 name
= "depth clear";
636 case ISL_AUX_OP_PARTIAL_RESOLVE
:
637 case ISL_AUX_OP_NONE
:
638 unreachable("Invalid HiZ op");
641 //DBG("%s %s to mt %p level %d layers %d-%d\n",
642 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
644 /* The following stalls and flushes are only documented to be required
645 * for HiZ clear operations. However, they also seem to be required for
646 * resolve operations.
648 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
650 * "If other rendering operations have preceded this clear, a
651 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
652 * enabled must be issued before the rectangle primitive used for
653 * the depth buffer clear operation."
655 * Same applies for Gen8 and Gen9.
657 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
658 * PIPE_CONTROL, Depth Cache Flush Enable:
660 * "This bit must not be set when Depth Stall Enable bit is set in
663 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
665 * Therefore issue two pipe control flushes, one for cache flush and
666 * another for depth stall.
668 iris_emit_pipe_control_flush(batch
,
669 "hiz op: pre-flushes (1/2)",
670 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
671 PIPE_CONTROL_CS_STALL
);
673 iris_emit_pipe_control_flush(batch
, "hiz op: pre-flushes (2/2)",
674 PIPE_CONTROL_DEPTH_STALL
);
676 assert(isl_aux_usage_has_hiz(res
->aux
.usage
) && res
->aux
.bo
);
678 iris_batch_maybe_flush(batch
, 1500);
680 struct blorp_surf surf
;
681 iris_blorp_surf_for_resource(&ice
->vtbl
, &batch
->screen
->isl_dev
, &surf
,
682 &res
->base
, res
->aux
.usage
, level
, true);
684 struct blorp_batch blorp_batch
;
685 enum blorp_batch_flags flags
= 0;
686 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
687 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
688 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
689 blorp_batch_finish(&blorp_batch
);
691 /* The following stalls and flushes are only documented to be required
692 * for HiZ clear operations. However, they also seem to be required for
693 * resolve operations.
695 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
697 * "Depth buffer clear pass using any of the methods (WM_STATE,
698 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
699 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
700 * "set" before starting to render. DepthStall and DepthFlush are
701 * not needed between consecutive depth clear passes nor is it
702 * required if the depth clear pass was done with
703 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
705 * TODO: Such as the spec says, this could be conditional.
707 iris_emit_pipe_control_flush(batch
,
708 "hiz op: post flush",
709 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
710 PIPE_CONTROL_DEPTH_STALL
);
714 * Does the resource's slice have hiz enabled?
717 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
719 iris_resource_check_level_layer(res
, level
, 0);
720 return res
->aux
.has_hiz
& 1 << level
;
723 /** \brief Assert that the level and layer are valid for the resource. */
725 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
726 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
728 assert(level
< res
->surf
.levels
);
729 assert(layer
< util_num_layers(&res
->base
, level
));
732 static inline uint32_t
733 miptree_level_range_length(const struct iris_resource
*res
,
734 uint32_t start_level
, uint32_t num_levels
)
736 assert(start_level
< res
->surf
.levels
);
738 if (num_levels
== INTEL_REMAINING_LAYERS
)
739 num_levels
= res
->surf
.levels
;
741 /* Check for overflow */
742 assert(start_level
+ num_levels
>= start_level
);
743 assert(start_level
+ num_levels
<= res
->surf
.levels
);
748 static inline uint32_t
749 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
750 uint32_t start_layer
, uint32_t num_layers
)
752 assert(level
<= res
->base
.last_level
);
754 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
755 assert(start_layer
< total_num_layers
);
756 if (num_layers
== INTEL_REMAINING_LAYERS
)
757 num_layers
= total_num_layers
- start_layer
;
758 /* Check for overflow */
759 assert(start_layer
+ num_layers
>= start_layer
);
760 assert(start_layer
+ num_layers
<= total_num_layers
);
766 iris_has_color_unresolved(const struct iris_resource
*res
,
767 unsigned start_level
, unsigned num_levels
,
768 unsigned start_layer
, unsigned num_layers
)
773 /* Clamp the level range to fit the resource */
774 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
776 for (uint32_t l
= 0; l
< num_levels
; l
++) {
777 const uint32_t level
= start_level
+ l
;
778 const uint32_t level_layers
=
779 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
780 for (unsigned a
= 0; a
< level_layers
; a
++) {
781 enum isl_aux_state aux_state
=
782 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
783 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
784 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
792 static enum isl_aux_op
793 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
794 enum isl_aux_usage aux_usage
,
795 bool fast_clear_supported
)
797 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
799 const bool ccs_supported
=
800 (aux_usage
== ISL_AUX_USAGE_CCS_D
) && fast_clear_supported
;
803 case ISL_AUX_STATE_CLEAR
:
804 case ISL_AUX_STATE_PARTIAL_CLEAR
:
806 return ISL_AUX_OP_FULL_RESOLVE
;
808 return ISL_AUX_OP_NONE
;
810 case ISL_AUX_STATE_PASS_THROUGH
:
811 return ISL_AUX_OP_NONE
;
813 case ISL_AUX_STATE_RESOLVED
:
814 case ISL_AUX_STATE_AUX_INVALID
:
815 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
816 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
820 unreachable("Invalid aux state for CCS_D");
823 static enum isl_aux_op
824 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
825 enum isl_aux_usage aux_usage
,
826 bool fast_clear_supported
)
828 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
829 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
830 aux_usage
== ISL_AUX_USAGE_CCS_D
||
831 aux_usage
== ISL_AUX_USAGE_CCS_E
);
834 case ISL_AUX_STATE_CLEAR
:
835 case ISL_AUX_STATE_PARTIAL_CLEAR
:
836 if (fast_clear_supported
)
837 return ISL_AUX_OP_NONE
;
838 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
839 return ISL_AUX_OP_PARTIAL_RESOLVE
;
841 return ISL_AUX_OP_FULL_RESOLVE
;
843 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
844 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
845 return ISL_AUX_OP_FULL_RESOLVE
;
846 else if (!fast_clear_supported
)
847 return ISL_AUX_OP_PARTIAL_RESOLVE
;
849 return ISL_AUX_OP_NONE
;
851 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
852 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
853 return ISL_AUX_OP_FULL_RESOLVE
;
855 return ISL_AUX_OP_NONE
;
857 case ISL_AUX_STATE_PASS_THROUGH
:
858 return ISL_AUX_OP_NONE
;
860 case ISL_AUX_STATE_RESOLVED
:
861 case ISL_AUX_STATE_AUX_INVALID
:
865 unreachable("Invalid aux state for CCS_E");
869 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
870 struct iris_batch
*batch
,
871 struct iris_resource
*res
,
872 uint32_t level
, uint32_t layer
,
873 enum isl_aux_usage aux_usage
,
874 bool fast_clear_supported
)
876 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
878 enum isl_aux_op resolve_op
;
879 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
880 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
881 fast_clear_supported
);
883 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
884 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
885 fast_clear_supported
);
888 if (resolve_op
!= ISL_AUX_OP_NONE
) {
889 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
891 switch (resolve_op
) {
892 case ISL_AUX_OP_FULL_RESOLVE
:
893 /* The CCS full resolve operation destroys the CCS and sets it to the
894 * pass-through state. (You can also think of this as being both a
895 * resolve and an ambiguate in one operation.)
897 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
898 ISL_AUX_STATE_PASS_THROUGH
);
901 case ISL_AUX_OP_PARTIAL_RESOLVE
:
902 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
903 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
907 unreachable("Invalid resolve op");
913 iris_resource_finish_ccs_write(struct iris_context
*ice
,
914 struct iris_resource
*res
,
915 uint32_t level
, uint32_t layer
,
916 enum isl_aux_usage aux_usage
)
918 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
919 aux_usage
== ISL_AUX_USAGE_CCS_D
||
920 aux_usage
== ISL_AUX_USAGE_CCS_E
);
922 enum isl_aux_state aux_state
=
923 iris_resource_get_aux_state(res
, level
, layer
);
925 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
927 case ISL_AUX_STATE_CLEAR
:
928 case ISL_AUX_STATE_PARTIAL_CLEAR
:
929 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
930 aux_usage
== ISL_AUX_USAGE_CCS_D
);
932 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
933 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
934 ISL_AUX_STATE_COMPRESSED_CLEAR
);
935 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
936 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
937 ISL_AUX_STATE_PARTIAL_CLEAR
);
941 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
942 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
943 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
944 break; /* Nothing to do */
946 case ISL_AUX_STATE_PASS_THROUGH
:
947 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
948 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
949 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
955 case ISL_AUX_STATE_RESOLVED
:
956 case ISL_AUX_STATE_AUX_INVALID
:
957 unreachable("Invalid aux state for CCS_E");
960 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
961 /* CCS_D is a bit simpler */
963 case ISL_AUX_STATE_CLEAR
:
964 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
965 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
966 ISL_AUX_STATE_PARTIAL_CLEAR
);
969 case ISL_AUX_STATE_PARTIAL_CLEAR
:
970 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
971 break; /* Nothing to do */
973 case ISL_AUX_STATE_PASS_THROUGH
:
977 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
978 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
979 case ISL_AUX_STATE_RESOLVED
:
980 case ISL_AUX_STATE_AUX_INVALID
:
981 unreachable("Invalid aux state for CCS_D");
987 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
988 struct iris_batch
*batch
,
989 struct iris_resource
*res
,
991 enum isl_aux_usage aux_usage
,
992 bool fast_clear_supported
)
994 assert(isl_aux_usage_has_mcs(aux_usage
));
996 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
997 case ISL_AUX_STATE_CLEAR
:
998 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
999 if (!fast_clear_supported
) {
1000 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
1001 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
1002 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1006 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1007 break; /* Nothing to do */
1009 case ISL_AUX_STATE_RESOLVED
:
1010 case ISL_AUX_STATE_PASS_THROUGH
:
1011 case ISL_AUX_STATE_AUX_INVALID
:
1012 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1013 unreachable("Invalid aux state for MCS");
1018 iris_resource_finish_mcs_write(struct iris_context
*ice
,
1019 struct iris_resource
*res
,
1021 enum isl_aux_usage aux_usage
)
1023 assert(isl_aux_usage_has_mcs(aux_usage
));
1025 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
1026 case ISL_AUX_STATE_CLEAR
:
1027 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
1028 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1031 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1032 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1033 break; /* Nothing to do */
1035 case ISL_AUX_STATE_RESOLVED
:
1036 case ISL_AUX_STATE_PASS_THROUGH
:
1037 case ISL_AUX_STATE_AUX_INVALID
:
1038 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1039 unreachable("Invalid aux state for MCS");
1044 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
1045 struct iris_batch
*batch
,
1046 struct iris_resource
*res
,
1047 uint32_t level
, uint32_t layer
,
1048 enum isl_aux_usage aux_usage
,
1049 bool fast_clear_supported
)
1051 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1052 aux_usage
== ISL_AUX_USAGE_HIZ
||
1053 aux_usage
== ISL_AUX_USAGE_HIZ_CCS
||
1054 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1056 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
1057 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1058 case ISL_AUX_STATE_CLEAR
:
1059 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1060 if (aux_usage
== ISL_AUX_USAGE_NONE
|| !fast_clear_supported
)
1061 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1064 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1065 if (aux_usage
== ISL_AUX_USAGE_NONE
)
1066 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1069 case ISL_AUX_STATE_PASS_THROUGH
:
1070 case ISL_AUX_STATE_RESOLVED
:
1073 case ISL_AUX_STATE_AUX_INVALID
:
1074 if (aux_usage
!= ISL_AUX_USAGE_NONE
)
1075 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
1078 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1079 unreachable("Invalid HiZ state");
1082 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1083 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
, false);
1086 case ISL_AUX_OP_FULL_RESOLVE
:
1087 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1088 ISL_AUX_STATE_RESOLVED
);
1091 case ISL_AUX_OP_AMBIGUATE
:
1092 /* The HiZ resolve operation is actually an ambiguate */
1093 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1094 ISL_AUX_STATE_PASS_THROUGH
);
1098 unreachable("Invalid HiZ op");
1104 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1105 struct iris_resource
*res
,
1106 uint32_t level
, uint32_t layer
,
1107 enum isl_aux_usage aux_usage
)
1109 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1110 isl_aux_usage_has_hiz(aux_usage
));
1112 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1113 case ISL_AUX_STATE_CLEAR
:
1114 assert(isl_aux_usage_has_hiz(aux_usage
));
1115 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1116 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1119 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1120 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1121 assert(isl_aux_usage_has_hiz(aux_usage
));
1122 break; /* Nothing to do */
1124 case ISL_AUX_STATE_RESOLVED
:
1125 if (isl_aux_usage_has_hiz(aux_usage
)) {
1126 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1127 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1129 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1130 ISL_AUX_STATE_AUX_INVALID
);
1134 case ISL_AUX_STATE_PASS_THROUGH
:
1135 if (isl_aux_usage_has_hiz(aux_usage
)) {
1136 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1137 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1141 case ISL_AUX_STATE_AUX_INVALID
:
1142 assert(!isl_aux_usage_has_hiz(aux_usage
));
1145 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1146 unreachable("Invalid HiZ state");
1151 iris_resource_prepare_access(struct iris_context
*ice
,
1152 struct iris_batch
*batch
,
1153 struct iris_resource
*res
,
1154 uint32_t start_level
, uint32_t num_levels
,
1155 uint32_t start_layer
, uint32_t num_layers
,
1156 enum isl_aux_usage aux_usage
,
1157 bool fast_clear_supported
)
1159 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1161 switch (res
->aux
.usage
) {
1162 case ISL_AUX_USAGE_NONE
:
1166 case ISL_AUX_USAGE_MCS
:
1167 case ISL_AUX_USAGE_MCS_CCS
:
1168 assert(start_level
== 0 && num_levels
== 1);
1169 const uint32_t level_layers
=
1170 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1171 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1172 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1173 aux_usage
, fast_clear_supported
);
1177 case ISL_AUX_USAGE_CCS_D
:
1178 case ISL_AUX_USAGE_CCS_E
:
1179 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1180 const uint32_t level
= start_level
+ l
;
1181 const uint32_t level_layers
=
1182 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1183 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1184 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1186 aux_usage
, fast_clear_supported
);
1191 case ISL_AUX_USAGE_HIZ
:
1192 case ISL_AUX_USAGE_HIZ_CCS
:
1193 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1194 const uint32_t level
= start_level
+ l
;
1195 if (!iris_resource_level_has_hiz(res
, level
))
1198 const uint32_t level_layers
=
1199 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1200 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1201 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1202 start_layer
+ a
, aux_usage
,
1203 fast_clear_supported
);
1209 unreachable("Invalid aux usage");
1214 iris_resource_finish_write(struct iris_context
*ice
,
1215 struct iris_resource
*res
, uint32_t level
,
1216 uint32_t start_layer
, uint32_t num_layers
,
1217 enum isl_aux_usage aux_usage
)
1219 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1221 switch (res
->aux
.usage
) {
1222 case ISL_AUX_USAGE_NONE
:
1225 case ISL_AUX_USAGE_MCS
:
1226 case ISL_AUX_USAGE_MCS_CCS
:
1227 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1228 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1233 case ISL_AUX_USAGE_CCS_D
:
1234 case ISL_AUX_USAGE_CCS_E
:
1235 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1236 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1241 case ISL_AUX_USAGE_HIZ
:
1242 case ISL_AUX_USAGE_HIZ_CCS
:
1243 if (!iris_resource_level_has_hiz(res
, level
))
1246 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1247 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1253 unreachable("Invavlid aux usage");
1258 iris_resource_get_aux_state(const struct iris_resource
*res
,
1259 uint32_t level
, uint32_t layer
)
1261 iris_resource_check_level_layer(res
, level
, layer
);
1263 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1264 assert(iris_resource_level_has_hiz(res
, level
));
1266 assert(res
->surf
.samples
== 1 ||
1267 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1270 return res
->aux
.state
[level
][layer
];
1274 iris_resource_set_aux_state(struct iris_context
*ice
,
1275 struct iris_resource
*res
, uint32_t level
,
1276 uint32_t start_layer
, uint32_t num_layers
,
1277 enum isl_aux_state aux_state
)
1279 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1281 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1282 assert(iris_resource_level_has_hiz(res
, level
));
1284 assert(res
->surf
.samples
== 1 ||
1285 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1288 for (unsigned a
= 0; a
< num_layers
; a
++) {
1289 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1290 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1291 /* XXX: Need to track which bindings to make dirty */
1292 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1297 /* On Gen9 color buffers may be compressed by the hardware (lossless
1298 * compression). There are, however, format restrictions and care needs to be
1299 * taken that the sampler engine is capable for re-interpreting a buffer with
1300 * format different the buffer was originally written with.
1302 * For example, SRGB formats are not compressible and the sampler engine isn't
1303 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1304 * color buffer needs to be resolved so that the sampling surface can be
1305 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1309 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1310 struct pipe_debug_callback
*dbg
,
1311 const struct iris_resource
*res
,
1312 enum isl_format view_format
)
1314 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1317 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1318 const struct isl_format_layout
*res_fmtl
=
1319 isl_format_get_layout(res
->surf
.format
);
1320 const struct isl_format_layout
*view_fmtl
=
1321 isl_format_get_layout(view_format
);
1323 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1324 view_fmtl
->name
, res_fmtl
->name
);
1333 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1334 const struct iris_resource
*res
,
1335 enum isl_format view_format
)
1337 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1338 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1340 switch (res
->aux
.usage
) {
1341 case ISL_AUX_USAGE_HIZ
:
1342 if (sample_with_depth_aux(devinfo
, res
))
1343 return ISL_AUX_USAGE_HIZ
;
1346 case ISL_AUX_USAGE_HIZ_CCS
:
1347 if (sample_with_depth_aux(devinfo
, res
))
1348 return ISL_AUX_USAGE_CCS_E
;
1351 case ISL_AUX_USAGE_MCS
:
1352 case ISL_AUX_USAGE_MCS_CCS
:
1353 return res
->aux
.usage
;
1355 case ISL_AUX_USAGE_CCS_D
:
1356 case ISL_AUX_USAGE_CCS_E
:
1357 /* If we don't have any unresolved color, report an aux usage of
1358 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1359 * aux surface and we can save some bandwidth.
1361 if (!iris_has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1362 0, INTEL_REMAINING_LAYERS
))
1363 return ISL_AUX_USAGE_NONE
;
1365 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1366 return ISL_AUX_USAGE_CCS_E
;
1373 return ISL_AUX_USAGE_NONE
;
1377 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1379 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1380 * values so sRGB curve application was a no-op for all fast-clearable
1383 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1384 * values, the hardware interprets the floats, not as what would be
1385 * returned from the sampler (or written by the shader), but as being
1386 * between format conversion and sRGB curve application. This means that
1387 * we can switch between sRGB and UNORM without having to whack the clear
1390 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1394 iris_resource_prepare_texture(struct iris_context
*ice
,
1395 struct iris_batch
*batch
,
1396 struct iris_resource
*res
,
1397 enum isl_format view_format
,
1398 uint32_t start_level
, uint32_t num_levels
,
1399 uint32_t start_layer
, uint32_t num_layers
)
1401 enum isl_aux_usage aux_usage
=
1402 iris_resource_texture_aux_usage(ice
, res
, view_format
);
1404 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1406 /* Clear color is specified as ints or floats and the conversion is done by
1407 * the sampler. If we have a texture view, we would have to perform the
1408 * clear color conversion manually. Just disable clear color.
1410 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1411 clear_supported
= false;
1413 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1414 start_layer
, num_layers
,
1415 aux_usage
, clear_supported
);
1419 iris_resource_render_aux_usage(struct iris_context
*ice
,
1420 struct iris_resource
*res
,
1421 enum isl_format render_format
,
1423 bool draw_aux_disabled
)
1425 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1426 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1428 if (draw_aux_disabled
)
1429 return ISL_AUX_USAGE_NONE
;
1431 switch (res
->aux
.usage
) {
1432 case ISL_AUX_USAGE_MCS
:
1433 case ISL_AUX_USAGE_MCS_CCS
:
1434 return res
->aux
.usage
;
1436 case ISL_AUX_USAGE_CCS_D
:
1437 case ISL_AUX_USAGE_CCS_E
:
1438 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1439 * formats. However, there are issues with blending where it doesn't
1440 * properly apply the sRGB curve to the clear color when blending.
1442 if (devinfo
->gen
>= 9 && blend_enabled
&&
1443 isl_format_is_srgb(render_format
) &&
1444 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1445 return ISL_AUX_USAGE_NONE
;
1447 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1448 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1449 return ISL_AUX_USAGE_CCS_E
;
1451 /* Otherwise, we try to fall back to CCS_D */
1452 if (isl_format_supports_ccs_d(devinfo
, render_format
))
1453 return ISL_AUX_USAGE_CCS_D
;
1456 return ISL_AUX_USAGE_NONE
;
1461 iris_resource_prepare_render(struct iris_context
*ice
,
1462 struct iris_batch
*batch
,
1463 struct iris_resource
*res
, uint32_t level
,
1464 uint32_t start_layer
, uint32_t layer_count
,
1465 enum isl_aux_usage aux_usage
)
1467 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1468 layer_count
, aux_usage
,
1469 aux_usage
!= ISL_AUX_USAGE_NONE
);
1473 iris_resource_finish_render(struct iris_context
*ice
,
1474 struct iris_resource
*res
, uint32_t level
,
1475 uint32_t start_layer
, uint32_t layer_count
,
1476 enum isl_aux_usage aux_usage
)
1478 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1483 iris_resource_prepare_depth(struct iris_context
*ice
,
1484 struct iris_batch
*batch
,
1485 struct iris_resource
*res
, uint32_t level
,
1486 uint32_t start_layer
, uint32_t layer_count
)
1488 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1489 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1493 iris_resource_finish_depth(struct iris_context
*ice
,
1494 struct iris_resource
*res
, uint32_t level
,
1495 uint32_t start_layer
, uint32_t layer_count
,
1498 if (depth_written
) {
1499 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,