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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
37 #include "compiler/nir/nir.h"
40 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
41 * or shader image. This causes a self-dependency, where both rendering
42 * and sampling may concurrently read or write the CCS buffer, causing
46 disable_rb_aux_buffer(struct iris_context
*ice
,
47 bool *draw_aux_buffer_disabled
,
48 struct iris_resource
*tex_res
,
49 unsigned min_level
, unsigned num_levels
,
52 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
55 /* We only need to worry about color compression and fast clears. */
56 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
57 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
60 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
61 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
65 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
67 if (rb_res
->bo
== tex_res
->bo
&&
68 surf
->base
.u
.tex
.level
>= min_level
&&
69 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
70 found
= draw_aux_buffer_disabled
[i
] = true;
76 "Disabling CCS because a renderbuffer is also bound %s.\n",
84 resolve_sampler_views(struct iris_context
*ice
,
85 struct iris_batch
*batch
,
86 struct iris_shader_state
*shs
,
87 const struct shader_info
*info
,
88 bool *draw_aux_buffer_disabled
,
89 bool consider_framebuffer
)
91 uint32_t views
= info
? (shs
->bound_sampler_views
& info
->textures_used
) : 0;
93 unsigned astc5x5_wa_bits
= 0; // XXX: actual tracking
96 const int i
= u_bit_scan(&views
);
97 struct iris_sampler_view
*isv
= shs
->textures
[i
];
98 struct iris_resource
*res
= (void *) isv
->base
.texture
;
100 if (res
->base
.target
!= PIPE_BUFFER
) {
101 if (consider_framebuffer
) {
102 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
103 res
, isv
->view
.base_level
, isv
->view
.levels
,
107 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
108 isv
->view
.base_level
, isv
->view
.levels
,
109 isv
->view
.base_array_layer
,
114 iris_cache_flush_for_read(batch
, res
->bo
);
119 resolve_image_views(struct iris_context
*ice
,
120 struct iris_batch
*batch
,
121 struct iris_shader_state
*shs
,
122 bool *draw_aux_buffer_disabled
,
123 bool consider_framebuffer
)
125 /* TODO: Consider images used by program */
126 uint32_t views
= shs
->bound_image_views
;
129 const int i
= u_bit_scan(&views
);
130 struct pipe_image_view
*pview
= &shs
->image
[i
].base
;
131 struct iris_resource
*res
= (void *) pview
->resource
;
133 if (res
->base
.target
!= PIPE_BUFFER
) {
134 if (consider_framebuffer
) {
135 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
136 res
, pview
->u
.tex
.level
, 1,
137 "as a shader image");
140 unsigned num_layers
=
141 pview
->u
.tex
.last_layer
- pview
->u
.tex
.first_layer
+ 1;
143 /* The data port doesn't understand any compression */
144 iris_resource_prepare_access(ice
, batch
, res
,
145 pview
->u
.tex
.level
, 1,
146 pview
->u
.tex
.first_layer
, num_layers
,
147 ISL_AUX_USAGE_NONE
, false);
150 iris_cache_flush_for_read(batch
, res
->bo
);
156 * \brief Resolve buffers before drawing.
158 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
159 * enabled depth texture, and flush the render cache for any dirty textures.
162 iris_predraw_resolve_inputs(struct iris_context
*ice
,
163 struct iris_batch
*batch
,
164 bool *draw_aux_buffer_disabled
,
165 gl_shader_stage stage
,
166 bool consider_framebuffer
)
168 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
169 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
171 uint64_t dirty
= (IRIS_DIRTY_BINDINGS_VS
<< stage
) |
172 (consider_framebuffer
? IRIS_DIRTY_BINDINGS_FS
: 0);
174 if (ice
->state
.dirty
& dirty
) {
175 resolve_sampler_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
176 consider_framebuffer
);
177 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
,
178 consider_framebuffer
);
185 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
186 struct iris_batch
*batch
,
187 bool *draw_aux_buffer_disabled
)
189 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
190 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
191 struct gen_device_info
*devinfo
= &screen
->devinfo
;
192 struct iris_uncompiled_shader
*ish
=
193 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
194 const nir_shader
*nir
= ish
->nir
;
196 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
197 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
200 struct iris_resource
*z_res
, *s_res
;
201 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
202 unsigned num_layers
=
203 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
206 iris_resource_prepare_depth(ice
, batch
, z_res
,
207 zs_surf
->u
.tex
.level
,
208 zs_surf
->u
.tex
.first_layer
,
210 iris_cache_flush_for_depth(batch
, z_res
->bo
);
214 iris_cache_flush_for_depth(batch
, s_res
->bo
);
219 if (devinfo
->gen
== 8 && nir
->info
.outputs_read
!= 0) {
220 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
221 if (cso_fb
->cbufs
[i
]) {
222 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
223 struct iris_resource
*res
= (void *) cso_fb
->cbufs
[i
]->texture
;
225 iris_resource_prepare_texture(ice
, batch
, res
, surf
->view
.format
,
226 surf
->view
.base_level
, 1,
227 surf
->view
.base_array_layer
,
228 surf
->view
.array_len
,
234 if (ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
)) {
235 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
236 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
240 struct iris_resource
*res
= (void *) surf
->base
.texture
;
242 enum isl_aux_usage aux_usage
=
243 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
244 ice
->state
.blend_enables
& (1u << i
),
245 draw_aux_buffer_disabled
[i
]);
247 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
248 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
249 /* XXX: Need to track which bindings to make dirty */
250 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
253 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
254 surf
->view
.base_array_layer
,
255 surf
->view
.array_len
,
258 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
265 * \brief Call this after drawing to mark which buffers need resolving
267 * If the depth buffer was written to and if it has an accompanying HiZ
268 * buffer, then mark that it needs a depth resolve.
270 * If the color buffer is a multisample window system buffer, then
271 * mark that it needs a downsample.
273 * Also mark any render targets which will be textured as needing a render
277 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
278 struct iris_batch
*batch
)
280 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
282 // XXX: front buffer drawing?
284 bool may_have_resolved_depth
=
285 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
286 IRIS_DIRTY_WM_DEPTH_STENCIL
);
288 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
290 struct iris_resource
*z_res
, *s_res
;
291 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
292 unsigned num_layers
=
293 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
296 if (may_have_resolved_depth
) {
297 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
298 zs_surf
->u
.tex
.first_layer
, num_layers
,
299 ice
->state
.depth_writes_enabled
);
302 if (ice
->state
.depth_writes_enabled
)
303 iris_depth_cache_add_bo(batch
, z_res
->bo
);
307 if (may_have_resolved_depth
) {
308 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
309 zs_surf
->u
.tex
.first_layer
, num_layers
,
313 if (ice
->state
.stencil_writes_enabled
)
314 iris_depth_cache_add_bo(batch
, s_res
->bo
);
318 bool may_have_resolved_color
=
319 ice
->state
.dirty
& (IRIS_DIRTY_BINDINGS_FS
| IRIS_DIRTY_BLEND_STATE
);
321 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
322 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
326 struct iris_resource
*res
= (void *) surf
->base
.texture
;
327 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
329 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
,
332 if (may_have_resolved_color
) {
333 union pipe_surface_desc
*desc
= &surf
->base
.u
;
334 unsigned num_layers
=
335 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
336 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
337 desc
->tex
.first_layer
, num_layers
,
344 * Clear the cache-tracking sets.
347 iris_cache_sets_clear(struct iris_batch
*batch
)
349 hash_table_foreach(batch
->cache
.render
, render_entry
)
350 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
352 set_foreach(batch
->cache
.depth
, depth_entry
)
353 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
357 * Emits an appropriate flush for a BO if it has been rendered to within the
358 * same batchbuffer as a read that's about to be emitted.
360 * The GPU has separate, incoherent caches for the render cache and the
361 * sampler cache, along with other caches. Usually data in the different
362 * caches don't interact (e.g. we don't render to our driver-generated
363 * immediate constant data), but for render-to-texture in FBOs we definitely
364 * do. When a batchbuffer is flushed, the kernel will ensure that everything
365 * necessary is flushed before another use of that BO, but for reuse from
366 * different caches within a batchbuffer, it's all our responsibility.
369 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
371 iris_emit_pipe_control_flush(batch
,
372 "cache tracker: render-to-texture",
373 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
374 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
375 PIPE_CONTROL_CS_STALL
);
377 iris_emit_pipe_control_flush(batch
,
378 "cache tracker: render-to-texture",
379 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
380 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
382 iris_cache_sets_clear(batch
);
386 iris_cache_flush_for_read(struct iris_batch
*batch
,
389 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
390 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
391 iris_flush_depth_and_render_caches(batch
);
395 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
397 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
401 iris_cache_flush_for_render(struct iris_batch
*batch
,
403 enum isl_format format
,
404 enum isl_aux_usage aux_usage
)
406 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
407 iris_flush_depth_and_render_caches(batch
);
409 /* Check to see if this bo has been used by a previous rendering operation
410 * but with a different format or aux usage. If it has, flush the render
411 * cache so we ensure that it's only in there with one format or aux usage
414 * Even though it's not obvious, this can easily happen in practice.
415 * Suppose a client is blending on a surface with sRGB encode enabled on
416 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
417 * then disables sRGB decode and continues blending we will flip on
418 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
419 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
420 * that we have fragments in-flight which are rendering with UNORM+CCS_E
421 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
422 * same time and the pixel scoreboard and color blender are trying to sort
423 * it all out. This ends badly (i.e. GPU hangs).
425 * To date, we have never observed GPU hangs or even corruption to be
426 * associated with switching the format, only the aux usage. However,
427 * there are comments in various docs which indicate that the render cache
428 * isn't 100% resilient to format changes. We may as well be conservative
429 * and flush on format changes too. We can always relax this later if we
430 * find it to be a performance problem.
432 struct hash_entry
*entry
=
433 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
434 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
435 iris_flush_depth_and_render_caches(batch
);
439 iris_render_cache_add_bo(struct iris_batch
*batch
,
441 enum isl_format format
,
442 enum isl_aux_usage aux_usage
)
445 struct hash_entry
*entry
=
446 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
448 /* Otherwise, someone didn't do a flush_for_render and that would be
451 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
455 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
456 format_aux_tuple(format
, aux_usage
));
460 iris_cache_flush_for_depth(struct iris_batch
*batch
,
463 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
464 iris_flush_depth_and_render_caches(batch
);
468 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
470 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
474 iris_resolve_color(struct iris_context
*ice
,
475 struct iris_batch
*batch
,
476 struct iris_resource
*res
,
477 unsigned level
, unsigned layer
,
478 enum isl_aux_op resolve_op
)
480 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
482 struct blorp_surf surf
;
483 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
486 iris_batch_maybe_flush(batch
, 1500);
488 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
490 * "Any transition from any value in {Clear, Render, Resolve} to a
491 * different value in {Clear, Render, Resolve} requires end of pipe
494 * In other words, fast clear ops are not properly synchronized with
495 * other drawing. We need to use a PIPE_CONTROL to ensure that the
496 * contents of the previous draw hit the render target before we resolve
497 * and again afterwards to ensure that the resolve is complete before we
498 * do any more regular drawing.
500 iris_emit_end_of_pipe_sync(batch
, "color resolve: pre-flush",
501 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
503 struct blorp_batch blorp_batch
;
504 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
505 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
506 isl_format_srgb_to_linear(res
->surf
.format
),
508 blorp_batch_finish(&blorp_batch
);
510 /* See comment above */
511 iris_emit_end_of_pipe_sync(batch
, "color resolve: post-flush",
512 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
516 iris_mcs_partial_resolve(struct iris_context
*ice
,
517 struct iris_batch
*batch
,
518 struct iris_resource
*res
,
519 uint32_t start_layer
,
522 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
523 //start_layer, start_layer + num_layers - 1);
525 assert(res
->aux
.usage
== ISL_AUX_USAGE_MCS
);
527 struct blorp_surf surf
;
528 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
531 struct blorp_batch blorp_batch
;
532 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
533 blorp_mcs_partial_resolve(&blorp_batch
, &surf
,
534 isl_format_srgb_to_linear(res
->surf
.format
),
535 start_layer
, num_layers
);
536 blorp_batch_finish(&blorp_batch
);
541 * Return true if the format that will be used to access the resource is
542 * CCS_E-compatible with the resource's linear/non-sRGB format.
544 * Why use the linear format? Well, although the resourcemay be specified
545 * with an sRGB format, the usage of that color space/format can be toggled.
546 * Since our HW tends to support more linear formats than sRGB ones, we use
547 * this format variant for check for CCS_E compatibility.
550 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
551 const struct iris_resource
*res
,
552 enum isl_format access_format
)
554 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
556 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
557 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
561 sample_with_depth_aux(const struct gen_device_info
*devinfo
,
562 const struct iris_resource
*res
)
564 switch (res
->aux
.usage
) {
565 case ISL_AUX_USAGE_HIZ
:
566 if (devinfo
->has_sample_with_hiz
)
569 case ISL_AUX_USAGE_HIZ_CCS
:
570 /* Write through mode must have been enabled for prior writes. */
571 if (isl_surf_supports_hiz_ccs_wt(devinfo
, &res
->surf
, res
->aux
.usage
))
578 /* It seems the hardware won't fallback to the depth buffer if some of the
579 * mipmap levels aren't available in the HiZ buffer. So we need all levels
580 * of the texture to be HiZ enabled.
582 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
583 if (!iris_resource_level_has_hiz(res
, level
))
587 /* If compressed multisampling is enabled, then we use it for the auxiliary
590 * From the BDW PRM (Volume 2d: Command Reference: Structures
591 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
593 * "If this field is set to AUX_HIZ, Number of Multisamples must be
594 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
596 * There is no such blurb for 1D textures, but there is sufficient evidence
597 * that this is broken on SKL+.
599 // XXX: i965 disables this for arrays too, is that reasonable?
600 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
604 * Perform a HiZ or depth resolve operation.
606 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
607 * PRM, Volume 1, Part 2:
608 * - 7.5.3.1 Depth Buffer Clear
609 * - 7.5.3.2 Depth Buffer Resolve
610 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
613 iris_hiz_exec(struct iris_context
*ice
,
614 struct iris_batch
*batch
,
615 struct iris_resource
*res
,
616 unsigned int level
, unsigned int start_layer
,
617 unsigned int num_layers
, enum isl_aux_op op
,
618 bool update_clear_depth
)
620 assert(iris_resource_level_has_hiz(res
, level
));
621 assert(op
!= ISL_AUX_OP_NONE
);
622 UNUSED
const char *name
= NULL
;
625 case ISL_AUX_OP_FULL_RESOLVE
:
626 name
= "depth resolve";
628 case ISL_AUX_OP_AMBIGUATE
:
629 name
= "hiz ambiguate";
631 case ISL_AUX_OP_FAST_CLEAR
:
632 name
= "depth clear";
634 case ISL_AUX_OP_PARTIAL_RESOLVE
:
635 case ISL_AUX_OP_NONE
:
636 unreachable("Invalid HiZ op");
639 //DBG("%s %s to mt %p level %d layers %d-%d\n",
640 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
642 /* The following stalls and flushes are only documented to be required
643 * for HiZ clear operations. However, they also seem to be required for
644 * resolve operations.
646 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
648 * "If other rendering operations have preceded this clear, a
649 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
650 * enabled must be issued before the rectangle primitive used for
651 * the depth buffer clear operation."
653 * Same applies for Gen8 and Gen9.
655 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
656 * PIPE_CONTROL, Depth Cache Flush Enable:
658 * "This bit must not be set when Depth Stall Enable bit is set in
661 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
663 * Therefore issue two pipe control flushes, one for cache flush and
664 * another for depth stall.
666 iris_emit_pipe_control_flush(batch
,
667 "hiz op: pre-flushes (1/2)",
668 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
669 PIPE_CONTROL_CS_STALL
);
671 iris_emit_pipe_control_flush(batch
, "hiz op: pre-flushes (2/2)",
672 PIPE_CONTROL_DEPTH_STALL
);
674 assert(isl_aux_usage_has_hiz(res
->aux
.usage
) && res
->aux
.bo
);
676 iris_batch_maybe_flush(batch
, 1500);
678 struct blorp_surf surf
;
679 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
,
680 res
->aux
.usage
, level
, true);
682 struct blorp_batch blorp_batch
;
683 enum blorp_batch_flags flags
= 0;
684 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
685 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
686 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
687 blorp_batch_finish(&blorp_batch
);
689 /* The following stalls and flushes are only documented to be required
690 * for HiZ clear operations. However, they also seem to be required for
691 * resolve operations.
693 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
695 * "Depth buffer clear pass using any of the methods (WM_STATE,
696 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
697 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
698 * "set" before starting to render. DepthStall and DepthFlush are
699 * not needed between consecutive depth clear passes nor is it
700 * required if the depth clear pass was done with
701 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
703 * TODO: Such as the spec says, this could be conditional.
705 iris_emit_pipe_control_flush(batch
,
706 "hiz op: post flush",
707 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
708 PIPE_CONTROL_DEPTH_STALL
);
712 * Does the resource's slice have hiz enabled?
715 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
717 iris_resource_check_level_layer(res
, level
, 0);
718 return res
->aux
.has_hiz
& 1 << level
;
721 /** \brief Assert that the level and layer are valid for the resource. */
723 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
724 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
726 assert(level
< res
->surf
.levels
);
727 assert(layer
< util_num_layers(&res
->base
, level
));
730 static inline uint32_t
731 miptree_level_range_length(const struct iris_resource
*res
,
732 uint32_t start_level
, uint32_t num_levels
)
734 assert(start_level
< res
->surf
.levels
);
736 if (num_levels
== INTEL_REMAINING_LAYERS
)
737 num_levels
= res
->surf
.levels
;
739 /* Check for overflow */
740 assert(start_level
+ num_levels
>= start_level
);
741 assert(start_level
+ num_levels
<= res
->surf
.levels
);
746 static inline uint32_t
747 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
748 uint32_t start_layer
, uint32_t num_layers
)
750 assert(level
<= res
->base
.last_level
);
752 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
753 assert(start_layer
< total_num_layers
);
754 if (num_layers
== INTEL_REMAINING_LAYERS
)
755 num_layers
= total_num_layers
- start_layer
;
756 /* Check for overflow */
757 assert(start_layer
+ num_layers
>= start_layer
);
758 assert(start_layer
+ num_layers
<= total_num_layers
);
764 iris_has_color_unresolved(const struct iris_resource
*res
,
765 unsigned start_level
, unsigned num_levels
,
766 unsigned start_layer
, unsigned num_layers
)
771 /* Clamp the level range to fit the resource */
772 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
774 for (uint32_t l
= 0; l
< num_levels
; l
++) {
775 const uint32_t level
= start_level
+ l
;
776 const uint32_t level_layers
=
777 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
778 for (unsigned a
= 0; a
< level_layers
; a
++) {
779 enum isl_aux_state aux_state
=
780 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
781 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
782 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
790 static enum isl_aux_op
791 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
792 enum isl_aux_usage aux_usage
,
793 bool fast_clear_supported
)
795 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
797 const bool ccs_supported
=
798 (aux_usage
== ISL_AUX_USAGE_CCS_D
) && fast_clear_supported
;
801 case ISL_AUX_STATE_CLEAR
:
802 case ISL_AUX_STATE_PARTIAL_CLEAR
:
804 return ISL_AUX_OP_FULL_RESOLVE
;
806 return ISL_AUX_OP_NONE
;
808 case ISL_AUX_STATE_PASS_THROUGH
:
809 return ISL_AUX_OP_NONE
;
811 case ISL_AUX_STATE_RESOLVED
:
812 case ISL_AUX_STATE_AUX_INVALID
:
813 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
814 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
818 unreachable("Invalid aux state for CCS_D");
821 static enum isl_aux_op
822 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
823 enum isl_aux_usage aux_usage
,
824 bool fast_clear_supported
)
826 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
827 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
828 aux_usage
== ISL_AUX_USAGE_CCS_D
||
829 aux_usage
== ISL_AUX_USAGE_CCS_E
);
832 case ISL_AUX_STATE_CLEAR
:
833 case ISL_AUX_STATE_PARTIAL_CLEAR
:
834 if (fast_clear_supported
)
835 return ISL_AUX_OP_NONE
;
836 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
837 return ISL_AUX_OP_PARTIAL_RESOLVE
;
839 return ISL_AUX_OP_FULL_RESOLVE
;
841 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
842 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
843 return ISL_AUX_OP_FULL_RESOLVE
;
844 else if (!fast_clear_supported
)
845 return ISL_AUX_OP_PARTIAL_RESOLVE
;
847 return ISL_AUX_OP_NONE
;
849 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
850 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
851 return ISL_AUX_OP_FULL_RESOLVE
;
853 return ISL_AUX_OP_NONE
;
855 case ISL_AUX_STATE_PASS_THROUGH
:
856 return ISL_AUX_OP_NONE
;
858 case ISL_AUX_STATE_RESOLVED
:
859 case ISL_AUX_STATE_AUX_INVALID
:
863 unreachable("Invalid aux state for CCS_E");
867 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
868 struct iris_batch
*batch
,
869 struct iris_resource
*res
,
870 uint32_t level
, uint32_t layer
,
871 enum isl_aux_usage aux_usage
,
872 bool fast_clear_supported
)
874 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
876 enum isl_aux_op resolve_op
;
877 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
878 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
879 fast_clear_supported
);
881 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
882 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
883 fast_clear_supported
);
886 if (resolve_op
!= ISL_AUX_OP_NONE
) {
887 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
889 switch (resolve_op
) {
890 case ISL_AUX_OP_FULL_RESOLVE
:
891 /* The CCS full resolve operation destroys the CCS and sets it to the
892 * pass-through state. (You can also think of this as being both a
893 * resolve and an ambiguate in one operation.)
895 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
896 ISL_AUX_STATE_PASS_THROUGH
);
899 case ISL_AUX_OP_PARTIAL_RESOLVE
:
900 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
901 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
905 unreachable("Invalid resolve op");
911 iris_resource_finish_ccs_write(struct iris_context
*ice
,
912 struct iris_resource
*res
,
913 uint32_t level
, uint32_t layer
,
914 enum isl_aux_usage aux_usage
)
916 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
917 aux_usage
== ISL_AUX_USAGE_CCS_D
||
918 aux_usage
== ISL_AUX_USAGE_CCS_E
);
920 enum isl_aux_state aux_state
=
921 iris_resource_get_aux_state(res
, level
, layer
);
923 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
925 case ISL_AUX_STATE_CLEAR
:
926 case ISL_AUX_STATE_PARTIAL_CLEAR
:
927 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
928 aux_usage
== ISL_AUX_USAGE_CCS_D
);
930 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
931 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
932 ISL_AUX_STATE_COMPRESSED_CLEAR
);
933 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
934 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
935 ISL_AUX_STATE_PARTIAL_CLEAR
);
939 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
940 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
941 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
942 break; /* Nothing to do */
944 case ISL_AUX_STATE_PASS_THROUGH
:
945 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
946 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
947 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
953 case ISL_AUX_STATE_RESOLVED
:
954 case ISL_AUX_STATE_AUX_INVALID
:
955 unreachable("Invalid aux state for CCS_E");
958 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
959 /* CCS_D is a bit simpler */
961 case ISL_AUX_STATE_CLEAR
:
962 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
963 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
964 ISL_AUX_STATE_PARTIAL_CLEAR
);
967 case ISL_AUX_STATE_PARTIAL_CLEAR
:
968 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
969 break; /* Nothing to do */
971 case ISL_AUX_STATE_PASS_THROUGH
:
975 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
976 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
977 case ISL_AUX_STATE_RESOLVED
:
978 case ISL_AUX_STATE_AUX_INVALID
:
979 unreachable("Invalid aux state for CCS_D");
985 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
986 struct iris_batch
*batch
,
987 struct iris_resource
*res
,
989 enum isl_aux_usage aux_usage
,
990 bool fast_clear_supported
)
992 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
994 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
995 case ISL_AUX_STATE_CLEAR
:
996 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
997 if (!fast_clear_supported
) {
998 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
999 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
1000 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1004 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1005 break; /* Nothing to do */
1007 case ISL_AUX_STATE_RESOLVED
:
1008 case ISL_AUX_STATE_PASS_THROUGH
:
1009 case ISL_AUX_STATE_AUX_INVALID
:
1010 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1011 unreachable("Invalid aux state for MCS");
1016 iris_resource_finish_mcs_write(struct iris_context
*ice
,
1017 struct iris_resource
*res
,
1019 enum isl_aux_usage aux_usage
)
1021 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
1023 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
1024 case ISL_AUX_STATE_CLEAR
:
1025 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
1026 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1029 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1030 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1031 break; /* Nothing to do */
1033 case ISL_AUX_STATE_RESOLVED
:
1034 case ISL_AUX_STATE_PASS_THROUGH
:
1035 case ISL_AUX_STATE_AUX_INVALID
:
1036 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1037 unreachable("Invalid aux state for MCS");
1042 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
1043 struct iris_batch
*batch
,
1044 struct iris_resource
*res
,
1045 uint32_t level
, uint32_t layer
,
1046 enum isl_aux_usage aux_usage
,
1047 bool fast_clear_supported
)
1049 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1050 aux_usage
== ISL_AUX_USAGE_HIZ
||
1051 aux_usage
== ISL_AUX_USAGE_HIZ_CCS
||
1052 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1054 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
1055 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1056 case ISL_AUX_STATE_CLEAR
:
1057 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1058 if (aux_usage
== ISL_AUX_USAGE_NONE
|| !fast_clear_supported
)
1059 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1062 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1063 if (aux_usage
== ISL_AUX_USAGE_NONE
)
1064 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
1067 case ISL_AUX_STATE_PASS_THROUGH
:
1068 case ISL_AUX_STATE_RESOLVED
:
1071 case ISL_AUX_STATE_AUX_INVALID
:
1072 if (aux_usage
!= ISL_AUX_USAGE_NONE
)
1073 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
1076 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1077 unreachable("Invalid HiZ state");
1080 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1081 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
, false);
1084 case ISL_AUX_OP_FULL_RESOLVE
:
1085 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1086 ISL_AUX_STATE_RESOLVED
);
1089 case ISL_AUX_OP_AMBIGUATE
:
1090 /* The HiZ resolve operation is actually an ambiguate */
1091 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1092 ISL_AUX_STATE_PASS_THROUGH
);
1096 unreachable("Invalid HiZ op");
1102 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1103 struct iris_resource
*res
,
1104 uint32_t level
, uint32_t layer
,
1105 enum isl_aux_usage aux_usage
)
1107 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1108 isl_aux_usage_has_hiz(aux_usage
));
1110 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1111 case ISL_AUX_STATE_CLEAR
:
1112 assert(isl_aux_usage_has_hiz(aux_usage
));
1113 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1114 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1117 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1118 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1119 assert(isl_aux_usage_has_hiz(aux_usage
));
1120 break; /* Nothing to do */
1122 case ISL_AUX_STATE_RESOLVED
:
1123 if (isl_aux_usage_has_hiz(aux_usage
)) {
1124 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1125 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1127 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1128 ISL_AUX_STATE_AUX_INVALID
);
1132 case ISL_AUX_STATE_PASS_THROUGH
:
1133 if (isl_aux_usage_has_hiz(aux_usage
)) {
1134 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1135 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1139 case ISL_AUX_STATE_AUX_INVALID
:
1140 assert(!isl_aux_usage_has_hiz(aux_usage
));
1143 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1144 unreachable("Invalid HiZ state");
1149 iris_resource_prepare_access(struct iris_context
*ice
,
1150 struct iris_batch
*batch
,
1151 struct iris_resource
*res
,
1152 uint32_t start_level
, uint32_t num_levels
,
1153 uint32_t start_layer
, uint32_t num_layers
,
1154 enum isl_aux_usage aux_usage
,
1155 bool fast_clear_supported
)
1157 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1159 switch (res
->aux
.usage
) {
1160 case ISL_AUX_USAGE_NONE
:
1164 case ISL_AUX_USAGE_MCS
:
1165 assert(start_level
== 0 && num_levels
== 1);
1166 const uint32_t level_layers
=
1167 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1168 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1169 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1170 aux_usage
, fast_clear_supported
);
1174 case ISL_AUX_USAGE_CCS_D
:
1175 case ISL_AUX_USAGE_CCS_E
:
1176 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1177 const uint32_t level
= start_level
+ l
;
1178 const uint32_t level_layers
=
1179 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1180 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1181 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1183 aux_usage
, fast_clear_supported
);
1188 case ISL_AUX_USAGE_HIZ
:
1189 case ISL_AUX_USAGE_HIZ_CCS
:
1190 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1191 const uint32_t level
= start_level
+ l
;
1192 if (!iris_resource_level_has_hiz(res
, level
))
1195 const uint32_t level_layers
=
1196 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1197 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1198 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1199 start_layer
+ a
, aux_usage
,
1200 fast_clear_supported
);
1206 unreachable("Invalid aux usage");
1211 iris_resource_finish_write(struct iris_context
*ice
,
1212 struct iris_resource
*res
, uint32_t level
,
1213 uint32_t start_layer
, uint32_t num_layers
,
1214 enum isl_aux_usage aux_usage
)
1216 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1218 switch (res
->aux
.usage
) {
1219 case ISL_AUX_USAGE_NONE
:
1222 case ISL_AUX_USAGE_MCS
:
1223 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1224 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1229 case ISL_AUX_USAGE_CCS_D
:
1230 case ISL_AUX_USAGE_CCS_E
:
1231 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1232 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1237 case ISL_AUX_USAGE_HIZ
:
1238 case ISL_AUX_USAGE_HIZ_CCS
:
1239 if (!iris_resource_level_has_hiz(res
, level
))
1242 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1243 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1249 unreachable("Invavlid aux usage");
1254 iris_resource_get_aux_state(const struct iris_resource
*res
,
1255 uint32_t level
, uint32_t layer
)
1257 iris_resource_check_level_layer(res
, level
, layer
);
1259 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1260 assert(iris_resource_level_has_hiz(res
, level
));
1261 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1262 unreachable("Cannot get aux state for stencil");
1264 assert(res
->surf
.samples
== 1 ||
1265 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1268 return res
->aux
.state
[level
][layer
];
1272 iris_resource_set_aux_state(struct iris_context
*ice
,
1273 struct iris_resource
*res
, uint32_t level
,
1274 uint32_t start_layer
, uint32_t num_layers
,
1275 enum isl_aux_state aux_state
)
1277 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1279 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1280 assert(iris_resource_level_has_hiz(res
, level
));
1281 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1282 unreachable("Cannot set aux state for stencil");
1284 assert(res
->surf
.samples
== 1 ||
1285 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1288 for (unsigned a
= 0; a
< num_layers
; a
++) {
1289 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1290 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1291 /* XXX: Need to track which bindings to make dirty */
1292 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1297 /* On Gen9 color buffers may be compressed by the hardware (lossless
1298 * compression). There are, however, format restrictions and care needs to be
1299 * taken that the sampler engine is capable for re-interpreting a buffer with
1300 * format different the buffer was originally written with.
1302 * For example, SRGB formats are not compressible and the sampler engine isn't
1303 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1304 * color buffer needs to be resolved so that the sampling surface can be
1305 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1309 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1310 struct pipe_debug_callback
*dbg
,
1311 const struct iris_resource
*res
,
1312 enum isl_format view_format
)
1314 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1317 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1318 const struct isl_format_layout
*res_fmtl
=
1319 isl_format_get_layout(res
->surf
.format
);
1320 const struct isl_format_layout
*view_fmtl
=
1321 isl_format_get_layout(view_format
);
1323 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1324 view_fmtl
->name
, res_fmtl
->name
);
1333 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1334 const struct iris_resource
*res
,
1335 enum isl_format view_format
,
1336 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1338 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1339 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1341 assert(devinfo
->gen
== 9 || astc5x5_wa_bits
== 0);
1343 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
1344 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
1347 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
1348 res
->aux
.usage
!= ISL_AUX_USAGE_MCS
)
1349 return ISL_AUX_USAGE_NONE
;
1351 switch (res
->aux
.usage
) {
1352 case ISL_AUX_USAGE_HIZ
:
1353 if (sample_with_depth_aux(devinfo
, res
))
1354 return ISL_AUX_USAGE_HIZ
;
1357 case ISL_AUX_USAGE_HIZ_CCS
:
1358 if (sample_with_depth_aux(devinfo
, res
))
1359 return ISL_AUX_USAGE_CCS_E
;
1362 case ISL_AUX_USAGE_MCS
:
1363 return ISL_AUX_USAGE_MCS
;
1365 case ISL_AUX_USAGE_CCS_D
:
1366 case ISL_AUX_USAGE_CCS_E
:
1367 /* If we don't have any unresolved color, report an aux usage of
1368 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1369 * aux surface and we can save some bandwidth.
1371 if (!iris_has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1372 0, INTEL_REMAINING_LAYERS
))
1373 return ISL_AUX_USAGE_NONE
;
1375 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1376 return ISL_AUX_USAGE_CCS_E
;
1383 return ISL_AUX_USAGE_NONE
;
1387 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1389 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1390 * values so sRGB curve application was a no-op for all fast-clearable
1393 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1394 * values, the hardware interprets the floats, not as what would be
1395 * returned from the sampler (or written by the shader), but as being
1396 * between format conversion and sRGB curve application. This means that
1397 * we can switch between sRGB and UNORM without having to whack the clear
1400 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1404 iris_resource_prepare_texture(struct iris_context
*ice
,
1405 struct iris_batch
*batch
,
1406 struct iris_resource
*res
,
1407 enum isl_format view_format
,
1408 uint32_t start_level
, uint32_t num_levels
,
1409 uint32_t start_layer
, uint32_t num_layers
,
1410 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1412 enum isl_aux_usage aux_usage
=
1413 iris_resource_texture_aux_usage(ice
, res
, view_format
, astc5x5_wa_bits
);
1415 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1417 /* Clear color is specified as ints or floats and the conversion is done by
1418 * the sampler. If we have a texture view, we would have to perform the
1419 * clear color conversion manually. Just disable clear color.
1421 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1422 clear_supported
= false;
1424 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1425 start_layer
, num_layers
,
1426 aux_usage
, clear_supported
);
1430 iris_resource_render_aux_usage(struct iris_context
*ice
,
1431 struct iris_resource
*res
,
1432 enum isl_format render_format
,
1434 bool draw_aux_disabled
)
1436 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1437 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1439 if (draw_aux_disabled
)
1440 return ISL_AUX_USAGE_NONE
;
1442 switch (res
->aux
.usage
) {
1443 case ISL_AUX_USAGE_MCS
:
1444 return ISL_AUX_USAGE_MCS
;
1446 case ISL_AUX_USAGE_CCS_D
:
1447 case ISL_AUX_USAGE_CCS_E
:
1448 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1449 * formats. However, there are issues with blending where it doesn't
1450 * properly apply the sRGB curve to the clear color when blending.
1452 if (devinfo
->gen
>= 9 && blend_enabled
&&
1453 isl_format_is_srgb(render_format
) &&
1454 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1455 return ISL_AUX_USAGE_NONE
;
1457 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1458 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1459 return ISL_AUX_USAGE_CCS_E
;
1461 /* Otherwise, we try to fall back to CCS_D */
1462 if (isl_format_supports_ccs_d(devinfo
, render_format
))
1463 return ISL_AUX_USAGE_CCS_D
;
1466 return ISL_AUX_USAGE_NONE
;
1471 iris_resource_prepare_render(struct iris_context
*ice
,
1472 struct iris_batch
*batch
,
1473 struct iris_resource
*res
, uint32_t level
,
1474 uint32_t start_layer
, uint32_t layer_count
,
1475 enum isl_aux_usage aux_usage
)
1477 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1478 layer_count
, aux_usage
,
1479 aux_usage
!= ISL_AUX_USAGE_NONE
);
1483 iris_resource_finish_render(struct iris_context
*ice
,
1484 struct iris_resource
*res
, uint32_t level
,
1485 uint32_t start_layer
, uint32_t layer_count
,
1486 enum isl_aux_usage aux_usage
)
1488 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1493 iris_resource_prepare_depth(struct iris_context
*ice
,
1494 struct iris_batch
*batch
,
1495 struct iris_resource
*res
, uint32_t level
,
1496 uint32_t start_layer
, uint32_t layer_count
)
1498 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1499 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1503 iris_resource_finish_depth(struct iris_context
*ice
,
1504 struct iris_resource
*res
, uint32_t level
,
1505 uint32_t start_layer
, uint32_t layer_count
,
1508 if (depth_written
) {
1509 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,