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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
39 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
40 * or shader image. This causes a self-dependency, where both rendering
41 * and sampling may concurrently read or write the CCS buffer, causing
45 disable_rb_aux_buffer(struct iris_context
*ice
,
46 bool *draw_aux_buffer_disabled
,
47 struct iris_resource
*tex_res
,
48 unsigned min_level
, unsigned num_levels
,
51 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
54 /* We only need to worry about color compression and fast clears. */
55 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
56 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
59 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
60 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
64 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
66 if (rb_res
->bo
== tex_res
->bo
&&
67 surf
->base
.u
.tex
.level
>= min_level
&&
68 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
69 found
= draw_aux_buffer_disabled
[i
] = true;
75 "Disabling CCS because a renderbuffer is also bound %s.\n",
83 resolve_sampler_views(struct iris_context
*ice
,
84 struct iris_batch
*batch
,
85 struct iris_shader_state
*shs
,
86 bool *draw_aux_buffer_disabled
,
87 bool consider_framebuffer
)
89 uint32_t views
= shs
->bound_sampler_views
;
91 unsigned astc5x5_wa_bits
= 0; // XXX: actual tracking
94 const int i
= u_bit_scan(&views
);
95 struct iris_sampler_view
*isv
= shs
->textures
[i
];
96 struct iris_resource
*res
= (void *) isv
->base
.texture
;
98 if (res
->base
.target
!= PIPE_BUFFER
) {
99 if (consider_framebuffer
) {
100 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
101 res
, isv
->view
.base_level
, isv
->view
.levels
,
105 iris_resource_prepare_texture(ice
, batch
, res
, isv
->view
.format
,
106 isv
->view
.base_level
, isv
->view
.levels
,
107 isv
->view
.base_array_layer
,
112 iris_cache_flush_for_read(batch
, res
->bo
);
117 resolve_image_views(struct iris_context
*ice
,
118 struct iris_batch
*batch
,
119 struct iris_shader_state
*shs
,
120 bool *draw_aux_buffer_disabled
,
121 bool consider_framebuffer
)
123 uint32_t views
= shs
->bound_image_views
;
126 const int i
= u_bit_scan(&views
);
127 struct iris_resource
*res
= (void *) shs
->image
[i
].res
;
129 if (res
->base
.target
!= PIPE_BUFFER
) {
130 if (consider_framebuffer
) {
131 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
132 res
, 0, ~0, "as a shader image");
135 iris_resource_prepare_image(ice
, batch
, res
);
138 iris_cache_flush_for_read(batch
, res
->bo
);
144 * \brief Resolve buffers before drawing.
146 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
147 * enabled depth texture, and flush the render cache for any dirty textures.
150 iris_predraw_resolve_inputs(struct iris_context
*ice
,
151 struct iris_batch
*batch
,
152 struct iris_shader_state
*shs
,
153 bool *draw_aux_buffer_disabled
,
154 bool consider_framebuffer
)
156 resolve_sampler_views(ice
, batch
, shs
, draw_aux_buffer_disabled
, consider_framebuffer
);
157 resolve_image_views(ice
, batch
, shs
, draw_aux_buffer_disabled
, consider_framebuffer
);
163 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
164 struct iris_batch
*batch
,
165 bool *draw_aux_buffer_disabled
)
167 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
168 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
171 struct iris_resource
*z_res
, *s_res
;
172 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
173 unsigned num_layers
=
174 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
177 iris_resource_prepare_depth(ice
, batch
, z_res
, zs_surf
->u
.tex
.level
,
178 zs_surf
->u
.tex
.first_layer
, num_layers
);
179 iris_cache_flush_for_depth(batch
, z_res
->bo
);
183 iris_cache_flush_for_depth(batch
, s_res
->bo
);
187 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
188 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
192 struct iris_resource
*res
= (void *) surf
->base
.texture
;
194 enum isl_aux_usage aux_usage
=
195 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
196 ice
->state
.blend_enables
& (1u << i
),
197 draw_aux_buffer_disabled
[i
]);
199 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
200 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
201 /* XXX: Need to track which bindings to make dirty */
202 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
205 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
206 surf
->view
.base_array_layer
,
207 surf
->view
.array_len
,
210 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
216 * \brief Call this after drawing to mark which buffers need resolving
218 * If the depth buffer was written to and if it has an accompanying HiZ
219 * buffer, then mark that it needs a depth resolve.
221 * If the color buffer is a multisample window system buffer, then
222 * mark that it needs a downsample.
224 * Also mark any render targets which will be textured as needing a render
228 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
229 struct iris_batch
*batch
)
231 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
232 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
234 // XXX: front buffer drawing?
237 struct iris_resource
*z_res
, *s_res
;
238 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
239 unsigned num_layers
=
240 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
243 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
244 zs_surf
->u
.tex
.first_layer
, num_layers
,
245 ice
->state
.depth_writes_enabled
);
247 if (ice
->state
.depth_writes_enabled
)
248 iris_depth_cache_add_bo(batch
, z_res
->bo
);
252 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
253 zs_surf
->u
.tex
.first_layer
, num_layers
,
256 if (ice
->state
.stencil_writes_enabled
)
257 iris_depth_cache_add_bo(batch
, s_res
->bo
);
261 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
262 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
266 struct iris_resource
*res
= (void *) surf
->base
.texture
;
267 union pipe_surface_desc
*desc
= &surf
->base
.u
;
268 unsigned num_layers
= desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
269 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
271 iris_render_cache_add_bo(batch
, res
->bo
, surf
->view
.format
, aux_usage
);
273 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
274 desc
->tex
.first_layer
, num_layers
,
280 * Clear the cache-tracking sets.
283 iris_cache_sets_clear(struct iris_batch
*batch
)
285 hash_table_foreach(batch
->cache
.render
, render_entry
)
286 _mesa_hash_table_remove(batch
->cache
.render
, render_entry
);
288 set_foreach(batch
->cache
.depth
, depth_entry
)
289 _mesa_set_remove(batch
->cache
.depth
, depth_entry
);
293 * Emits an appropriate flush for a BO if it has been rendered to within the
294 * same batchbuffer as a read that's about to be emitted.
296 * The GPU has separate, incoherent caches for the render cache and the
297 * sampler cache, along with other caches. Usually data in the different
298 * caches don't interact (e.g. we don't render to our driver-generated
299 * immediate constant data), but for render-to-texture in FBOs we definitely
300 * do. When a batchbuffer is flushed, the kernel will ensure that everything
301 * necessary is flushed before another use of that BO, but for reuse from
302 * different caches within a batchbuffer, it's all our responsibility.
305 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
307 iris_emit_pipe_control_flush(batch
,
308 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
309 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
310 PIPE_CONTROL_CS_STALL
);
312 iris_emit_pipe_control_flush(batch
,
313 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
314 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
316 iris_cache_sets_clear(batch
);
320 iris_cache_flush_for_read(struct iris_batch
*batch
,
323 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
) ||
324 _mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
325 iris_flush_depth_and_render_caches(batch
);
329 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
331 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
335 iris_cache_flush_for_render(struct iris_batch
*batch
,
337 enum isl_format format
,
338 enum isl_aux_usage aux_usage
)
340 if (_mesa_set_search_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
))
341 iris_flush_depth_and_render_caches(batch
);
343 /* Check to see if this bo has been used by a previous rendering operation
344 * but with a different format or aux usage. If it has, flush the render
345 * cache so we ensure that it's only in there with one format or aux usage
348 * Even though it's not obvious, this can easily happen in practice.
349 * Suppose a client is blending on a surface with sRGB encode enabled on
350 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
351 * then disables sRGB decode and continues blending we will flip on
352 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
353 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
354 * that we have fragments in-flight which are rendering with UNORM+CCS_E
355 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
356 * same time and the pixel scoreboard and color blender are trying to sort
357 * it all out. This ends badly (i.e. GPU hangs).
359 * To date, we have never observed GPU hangs or even corruption to be
360 * associated with switching the format, only the aux usage. However,
361 * there are comments in various docs which indicate that the render cache
362 * isn't 100% resilient to format changes. We may as well be conservative
363 * and flush on format changes too. We can always relax this later if we
364 * find it to be a performance problem.
366 struct hash_entry
*entry
=
367 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
368 if (entry
&& entry
->data
!= format_aux_tuple(format
, aux_usage
))
369 iris_flush_depth_and_render_caches(batch
);
373 iris_render_cache_add_bo(struct iris_batch
*batch
,
375 enum isl_format format
,
376 enum isl_aux_usage aux_usage
)
379 struct hash_entry
*entry
=
380 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
382 /* Otherwise, someone didn't do a flush_for_render and that would be
385 assert(entry
->data
== format_aux_tuple(format
, aux_usage
));
389 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
390 format_aux_tuple(format
, aux_usage
));
394 iris_cache_flush_for_depth(struct iris_batch
*batch
,
397 if (_mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
))
398 iris_flush_depth_and_render_caches(batch
);
402 iris_depth_cache_add_bo(struct iris_batch
*batch
, struct iris_bo
*bo
)
404 _mesa_set_add_pre_hashed(batch
->cache
.depth
, bo
->hash
, bo
);
408 iris_resolve_color(struct iris_context
*ice
,
409 struct iris_batch
*batch
,
410 struct iris_resource
*res
,
411 unsigned level
, unsigned layer
,
412 enum isl_aux_op resolve_op
)
414 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
416 struct blorp_surf surf
;
417 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
420 iris_batch_maybe_flush(batch
, 1500);
422 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
424 * "Any transition from any value in {Clear, Render, Resolve} to a
425 * different value in {Clear, Render, Resolve} requires end of pipe
428 * In other words, fast clear ops are not properly synchronized with
429 * other drawing. We need to use a PIPE_CONTROL to ensure that the
430 * contents of the previous draw hit the render target before we resolve
431 * and again afterwards to ensure that the resolve is complete before we
432 * do any more regular drawing.
434 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
436 struct blorp_batch blorp_batch
;
437 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
438 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
439 isl_format_srgb_to_linear(res
->surf
.format
),
441 blorp_batch_finish(&blorp_batch
);
443 /* See comment above */
444 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
448 iris_mcs_partial_resolve(struct iris_context
*ice
,
449 struct iris_batch
*batch
,
450 struct iris_resource
*res
,
451 uint32_t start_layer
,
454 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
455 //start_layer, start_layer + num_layers - 1);
457 assert(res
->aux
.usage
== ISL_AUX_USAGE_MCS
);
459 struct blorp_surf surf
;
460 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
, res
->aux
.usage
,
463 struct blorp_batch blorp_batch
;
464 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
465 blorp_mcs_partial_resolve(&blorp_batch
, &surf
, res
->surf
.format
,
466 start_layer
, num_layers
);
467 blorp_batch_finish(&blorp_batch
);
472 * Return true if the format that will be used to access the resource is
473 * CCS_E-compatible with the resource's linear/non-sRGB format.
475 * Why use the linear format? Well, although the resourcemay be specified
476 * with an sRGB format, the usage of that color space/format can be toggled.
477 * Since our HW tends to support more linear formats than sRGB ones, we use
478 * this format variant for check for CCS_E compatibility.
481 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
482 const struct iris_resource
*res
,
483 enum isl_format access_format
)
485 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
487 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
488 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
492 sample_with_hiz(const struct gen_device_info
*devinfo
,
493 const struct iris_resource
*res
)
495 if (!devinfo
->has_sample_with_hiz
)
498 if (res
->aux
.usage
!= ISL_AUX_USAGE_HIZ
)
501 /* It seems the hardware won't fallback to the depth buffer if some of the
502 * mipmap levels aren't available in the HiZ buffer. So we need all levels
503 * of the texture to be HiZ enabled.
505 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
506 if (!iris_resource_level_has_hiz(res
, level
))
510 /* If compressed multisampling is enabled, then we use it for the auxiliary
513 * From the BDW PRM (Volume 2d: Command Reference: Structures
514 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
516 * "If this field is set to AUX_HIZ, Number of Multisamples must be
517 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
519 * There is no such blurb for 1D textures, but there is sufficient evidence
520 * that this is broken on SKL+.
522 // XXX: i965 disables this for arrays too, is that reasonable?
523 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
527 * Perform a HiZ or depth resolve operation.
529 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
530 * PRM, Volume 1, Part 2:
531 * - 7.5.3.1 Depth Buffer Clear
532 * - 7.5.3.2 Depth Buffer Resolve
533 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
536 iris_hiz_exec(struct iris_context
*ice
,
537 struct iris_batch
*batch
,
538 struct iris_resource
*res
,
539 unsigned int level
, unsigned int start_layer
,
540 unsigned int num_layers
, enum isl_aux_op op
)
542 assert(iris_resource_level_has_hiz(res
, level
));
543 assert(op
!= ISL_AUX_OP_NONE
);
544 const char *name
= NULL
;
547 case ISL_AUX_OP_FULL_RESOLVE
:
548 name
= "depth resolve";
550 case ISL_AUX_OP_AMBIGUATE
:
551 name
= "hiz ambiguate";
553 case ISL_AUX_OP_FAST_CLEAR
:
554 name
= "depth clear";
556 case ISL_AUX_OP_PARTIAL_RESOLVE
:
557 case ISL_AUX_OP_NONE
:
558 unreachable("Invalid HiZ op");
561 //DBG("%s %s to mt %p level %d layers %d-%d\n",
562 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
564 /* The following stalls and flushes are only documented to be required
565 * for HiZ clear operations. However, they also seem to be required for
566 * resolve operations.
568 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
570 * "If other rendering operations have preceded this clear, a
571 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
572 * enabled must be issued before the rectangle primitive used for
573 * the depth buffer clear operation."
575 * Same applies for Gen8 and Gen9.
577 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
578 * PIPE_CONTROL, Depth Cache Flush Enable:
580 * "This bit must not be set when Depth Stall Enable bit is set in
583 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
585 * Therefore issue two pipe control flushes, one for cache flush and
586 * another for depth stall.
588 iris_emit_pipe_control_flush(batch
,
589 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
590 PIPE_CONTROL_CS_STALL
);
592 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_DEPTH_STALL
);
594 assert(res
->aux
.usage
== ISL_AUX_USAGE_HIZ
&& res
->aux
.bo
);
596 iris_batch_maybe_flush(batch
, 1500);
598 struct blorp_surf surf
;
599 iris_blorp_surf_for_resource(&ice
->vtbl
, &surf
, &res
->base
,
600 ISL_AUX_USAGE_HIZ
, level
, true);
602 struct blorp_batch blorp_batch
;
603 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
,
604 BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
);
605 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
606 blorp_batch_finish(&blorp_batch
);
608 /* The following stalls and flushes are only documented to be required
609 * for HiZ clear operations. However, they also seem to be required for
610 * resolve operations.
612 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
614 * "Depth buffer clear pass using any of the methods (WM_STATE,
615 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
616 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
617 * "set" before starting to render. DepthStall and DepthFlush are
618 * not needed between consecutive depth clear passes nor is it
619 * required if the depth clear pass was done with
620 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
622 * TODO: Such as the spec says, this could be conditional.
624 iris_emit_pipe_control_flush(batch
,
625 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
626 PIPE_CONTROL_DEPTH_STALL
);
630 * Does the resource's slice have hiz enabled?
633 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
635 iris_resource_check_level_layer(res
, level
, 0);
636 return res
->aux
.has_hiz
& 1 << level
;
639 /** \brief Assert that the level and layer are valid for the resource. */
641 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
642 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
644 assert(level
< res
->surf
.levels
);
645 assert(layer
< util_num_layers(&res
->base
, level
));
648 static inline uint32_t
649 miptree_level_range_length(const struct iris_resource
*res
,
650 uint32_t start_level
, uint32_t num_levels
)
652 assert(start_level
< res
->surf
.levels
);
654 if (num_levels
== INTEL_REMAINING_LAYERS
)
655 num_levels
= res
->surf
.levels
;
657 /* Check for overflow */
658 assert(start_level
+ num_levels
>= start_level
);
659 assert(start_level
+ num_levels
<= res
->surf
.levels
);
664 static inline uint32_t
665 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
666 uint32_t start_layer
, uint32_t num_layers
)
668 assert(level
<= res
->base
.last_level
);
670 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
671 assert(start_layer
< total_num_layers
);
672 if (num_layers
== INTEL_REMAINING_LAYERS
)
673 num_layers
= total_num_layers
- start_layer
;
674 /* Check for overflow */
675 assert(start_layer
+ num_layers
>= start_layer
);
676 assert(start_layer
+ num_layers
<= total_num_layers
);
682 has_color_unresolved(const struct iris_resource
*res
,
683 unsigned start_level
, unsigned num_levels
,
684 unsigned start_layer
, unsigned num_layers
)
689 /* Clamp the level range to fit the resource */
690 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
692 for (uint32_t l
= 0; l
< num_levels
; l
++) {
693 const uint32_t level
= start_level
+ l
;
694 const uint32_t level_layers
=
695 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
696 for (unsigned a
= 0; a
< level_layers
; a
++) {
697 enum isl_aux_state aux_state
=
698 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
699 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
700 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
708 static enum isl_aux_op
709 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
710 enum isl_aux_usage aux_usage
,
711 bool fast_clear_supported
)
713 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
715 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
717 assert(ccs_supported
== fast_clear_supported
);
720 case ISL_AUX_STATE_CLEAR
:
721 case ISL_AUX_STATE_PARTIAL_CLEAR
:
723 return ISL_AUX_OP_FULL_RESOLVE
;
725 return ISL_AUX_OP_NONE
;
727 case ISL_AUX_STATE_PASS_THROUGH
:
728 return ISL_AUX_OP_NONE
;
730 case ISL_AUX_STATE_RESOLVED
:
731 case ISL_AUX_STATE_AUX_INVALID
:
732 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
733 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
737 unreachable("Invalid aux state for CCS_D");
740 static enum isl_aux_op
741 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
742 enum isl_aux_usage aux_usage
,
743 bool fast_clear_supported
)
745 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
746 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
747 aux_usage
== ISL_AUX_USAGE_CCS_D
||
748 aux_usage
== ISL_AUX_USAGE_CCS_E
);
750 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
751 assert(fast_clear_supported
);
754 case ISL_AUX_STATE_CLEAR
:
755 case ISL_AUX_STATE_PARTIAL_CLEAR
:
756 if (fast_clear_supported
)
757 return ISL_AUX_OP_NONE
;
758 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
759 return ISL_AUX_OP_PARTIAL_RESOLVE
;
761 return ISL_AUX_OP_FULL_RESOLVE
;
763 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
764 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
765 return ISL_AUX_OP_FULL_RESOLVE
;
766 else if (!fast_clear_supported
)
767 return ISL_AUX_OP_PARTIAL_RESOLVE
;
769 return ISL_AUX_OP_NONE
;
771 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
772 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
773 return ISL_AUX_OP_FULL_RESOLVE
;
775 return ISL_AUX_OP_NONE
;
777 case ISL_AUX_STATE_PASS_THROUGH
:
778 return ISL_AUX_OP_NONE
;
780 case ISL_AUX_STATE_RESOLVED
:
781 case ISL_AUX_STATE_AUX_INVALID
:
785 unreachable("Invalid aux state for CCS_E");
789 iris_resource_prepare_ccs_access(struct iris_context
*ice
,
790 struct iris_batch
*batch
,
791 struct iris_resource
*res
,
792 uint32_t level
, uint32_t layer
,
793 enum isl_aux_usage aux_usage
,
794 bool fast_clear_supported
)
796 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, level
, layer
);
798 enum isl_aux_op resolve_op
;
799 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
800 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
801 fast_clear_supported
);
803 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
804 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
805 fast_clear_supported
);
808 if (resolve_op
!= ISL_AUX_OP_NONE
) {
809 iris_resolve_color(ice
, batch
, res
, level
, layer
, resolve_op
);
811 switch (resolve_op
) {
812 case ISL_AUX_OP_FULL_RESOLVE
:
813 /* The CCS full resolve operation destroys the CCS and sets it to the
814 * pass-through state. (You can also think of this as being both a
815 * resolve and an ambiguate in one operation.)
817 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
818 ISL_AUX_STATE_PASS_THROUGH
);
821 case ISL_AUX_OP_PARTIAL_RESOLVE
:
822 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
823 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
827 unreachable("Invalid resolve op");
833 iris_resource_finish_ccs_write(struct iris_context
*ice
,
834 struct iris_resource
*res
,
835 uint32_t level
, uint32_t layer
,
836 enum isl_aux_usage aux_usage
)
838 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
839 aux_usage
== ISL_AUX_USAGE_CCS_D
||
840 aux_usage
== ISL_AUX_USAGE_CCS_E
);
842 enum isl_aux_state aux_state
=
843 iris_resource_get_aux_state(res
, level
, layer
);
845 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) {
847 case ISL_AUX_STATE_CLEAR
:
848 case ISL_AUX_STATE_PARTIAL_CLEAR
:
849 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
850 aux_usage
== ISL_AUX_USAGE_CCS_D
);
852 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
853 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
854 ISL_AUX_STATE_COMPRESSED_CLEAR
);
855 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
856 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
857 ISL_AUX_STATE_PARTIAL_CLEAR
);
861 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
862 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
863 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
864 break; /* Nothing to do */
866 case ISL_AUX_STATE_PASS_THROUGH
:
867 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
868 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
869 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
875 case ISL_AUX_STATE_RESOLVED
:
876 case ISL_AUX_STATE_AUX_INVALID
:
877 unreachable("Invalid aux state for CCS_E");
880 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
);
881 /* CCS_D is a bit simpler */
883 case ISL_AUX_STATE_CLEAR
:
884 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
885 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
886 ISL_AUX_STATE_PARTIAL_CLEAR
);
889 case ISL_AUX_STATE_PARTIAL_CLEAR
:
890 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
891 break; /* Nothing to do */
893 case ISL_AUX_STATE_PASS_THROUGH
:
897 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
898 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
899 case ISL_AUX_STATE_RESOLVED
:
900 case ISL_AUX_STATE_AUX_INVALID
:
901 unreachable("Invalid aux state for CCS_D");
907 iris_resource_prepare_mcs_access(struct iris_context
*ice
,
908 struct iris_batch
*batch
,
909 struct iris_resource
*res
,
911 enum isl_aux_usage aux_usage
,
912 bool fast_clear_supported
)
914 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
916 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
917 case ISL_AUX_STATE_CLEAR
:
918 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
919 if (!fast_clear_supported
) {
920 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
921 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
922 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
926 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
927 break; /* Nothing to do */
929 case ISL_AUX_STATE_RESOLVED
:
930 case ISL_AUX_STATE_PASS_THROUGH
:
931 case ISL_AUX_STATE_AUX_INVALID
:
932 case ISL_AUX_STATE_PARTIAL_CLEAR
:
933 unreachable("Invalid aux state for MCS");
938 iris_resource_finish_mcs_write(struct iris_context
*ice
,
939 struct iris_resource
*res
,
941 enum isl_aux_usage aux_usage
)
943 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
945 switch (iris_resource_get_aux_state(res
, 0, layer
)) {
946 case ISL_AUX_STATE_CLEAR
:
947 iris_resource_set_aux_state(ice
, res
, 0, layer
, 1,
948 ISL_AUX_STATE_COMPRESSED_CLEAR
);
951 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
952 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
953 break; /* Nothing to do */
955 case ISL_AUX_STATE_RESOLVED
:
956 case ISL_AUX_STATE_PASS_THROUGH
:
957 case ISL_AUX_STATE_AUX_INVALID
:
958 case ISL_AUX_STATE_PARTIAL_CLEAR
:
959 unreachable("Invalid aux state for MCS");
964 iris_resource_prepare_hiz_access(struct iris_context
*ice
,
965 struct iris_batch
*batch
,
966 struct iris_resource
*res
,
967 uint32_t level
, uint32_t layer
,
968 enum isl_aux_usage aux_usage
,
969 bool fast_clear_supported
)
971 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
973 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
974 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
975 case ISL_AUX_STATE_CLEAR
:
976 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
977 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
978 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
981 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
982 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
983 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
986 case ISL_AUX_STATE_PASS_THROUGH
:
987 case ISL_AUX_STATE_RESOLVED
:
990 case ISL_AUX_STATE_AUX_INVALID
:
991 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
992 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
995 case ISL_AUX_STATE_PARTIAL_CLEAR
:
996 unreachable("Invalid HiZ state");
999 if (hiz_op
!= ISL_AUX_OP_NONE
) {
1000 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, hiz_op
);
1003 case ISL_AUX_OP_FULL_RESOLVE
:
1004 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1005 ISL_AUX_STATE_RESOLVED
);
1008 case ISL_AUX_OP_AMBIGUATE
:
1009 /* The HiZ resolve operation is actually an ambiguate */
1010 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1011 ISL_AUX_STATE_PASS_THROUGH
);
1015 unreachable("Invalid HiZ op");
1021 iris_resource_finish_hiz_write(struct iris_context
*ice
,
1022 struct iris_resource
*res
,
1023 uint32_t level
, uint32_t layer
,
1024 enum isl_aux_usage aux_usage
)
1026 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
1028 switch (iris_resource_get_aux_state(res
, level
, layer
)) {
1029 case ISL_AUX_STATE_CLEAR
:
1030 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1031 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1032 ISL_AUX_STATE_COMPRESSED_CLEAR
);
1035 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1036 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1037 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
1038 break; /* Nothing to do */
1040 case ISL_AUX_STATE_RESOLVED
:
1041 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1042 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1043 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1045 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1046 ISL_AUX_STATE_AUX_INVALID
);
1050 case ISL_AUX_STATE_PASS_THROUGH
:
1051 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1052 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1,
1053 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
1057 case ISL_AUX_STATE_AUX_INVALID
:
1058 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
1061 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1062 unreachable("Invalid HiZ state");
1067 iris_resource_prepare_access(struct iris_context
*ice
,
1068 struct iris_batch
*batch
,
1069 struct iris_resource
*res
,
1070 uint32_t start_level
, uint32_t num_levels
,
1071 uint32_t start_layer
, uint32_t num_layers
,
1072 enum isl_aux_usage aux_usage
,
1073 bool fast_clear_supported
)
1075 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
1077 switch (res
->aux
.usage
) {
1078 case ISL_AUX_USAGE_NONE
:
1082 case ISL_AUX_USAGE_MCS
:
1083 assert(start_level
== 0 && num_levels
== 1);
1084 const uint32_t level_layers
=
1085 miptree_layer_range_length(res
, 0, start_layer
, num_layers
);
1086 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1087 iris_resource_prepare_mcs_access(ice
, batch
, res
, start_layer
+ a
,
1088 aux_usage
, fast_clear_supported
);
1092 case ISL_AUX_USAGE_CCS_D
:
1093 case ISL_AUX_USAGE_CCS_E
:
1094 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1095 const uint32_t level
= start_level
+ l
;
1096 const uint32_t level_layers
=
1097 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1098 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1099 iris_resource_prepare_ccs_access(ice
, batch
, res
, level
,
1101 aux_usage
, fast_clear_supported
);
1106 case ISL_AUX_USAGE_HIZ
:
1107 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1108 const uint32_t level
= start_level
+ l
;
1109 if (!iris_resource_level_has_hiz(res
, level
))
1112 const uint32_t level_layers
=
1113 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1114 for (uint32_t a
= 0; a
< level_layers
; a
++) {
1115 iris_resource_prepare_hiz_access(ice
, batch
, res
, level
,
1116 start_layer
+ a
, aux_usage
,
1117 fast_clear_supported
);
1123 unreachable("Invalid aux usage");
1128 iris_resource_finish_write(struct iris_context
*ice
,
1129 struct iris_resource
*res
, uint32_t level
,
1130 uint32_t start_layer
, uint32_t num_layers
,
1131 enum isl_aux_usage aux_usage
)
1133 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1135 switch (res
->aux
.usage
) {
1136 case ISL_AUX_USAGE_NONE
:
1139 case ISL_AUX_USAGE_MCS
:
1140 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1141 iris_resource_finish_mcs_write(ice
, res
, start_layer
+ a
,
1146 case ISL_AUX_USAGE_CCS_D
:
1147 case ISL_AUX_USAGE_CCS_E
:
1148 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1149 iris_resource_finish_ccs_write(ice
, res
, level
, start_layer
+ a
,
1154 case ISL_AUX_USAGE_HIZ
:
1155 if (!iris_resource_level_has_hiz(res
, level
))
1158 for (uint32_t a
= 0; a
< num_layers
; a
++) {
1159 iris_resource_finish_hiz_write(ice
, res
, level
, start_layer
+ a
,
1165 unreachable("Invavlid aux usage");
1170 iris_resource_get_aux_state(const struct iris_resource
*res
,
1171 uint32_t level
, uint32_t layer
)
1173 iris_resource_check_level_layer(res
, level
, layer
);
1175 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1176 assert(iris_resource_level_has_hiz(res
, level
));
1177 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1178 unreachable("Cannot get aux state for stencil");
1180 assert(res
->surf
.samples
== 1 ||
1181 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1184 return res
->aux
.state
[level
][layer
];
1188 iris_resource_set_aux_state(struct iris_context
*ice
,
1189 struct iris_resource
*res
, uint32_t level
,
1190 uint32_t start_layer
, uint32_t num_layers
,
1191 enum isl_aux_state aux_state
)
1193 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
1195 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1196 assert(iris_resource_level_has_hiz(res
, level
));
1197 } else if (res
->surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1198 unreachable("Cannot set aux state for stencil");
1200 assert(res
->surf
.samples
== 1 ||
1201 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1204 for (unsigned a
= 0; a
< num_layers
; a
++) {
1205 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
1206 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
1207 /* XXX: Need to track which bindings to make dirty */
1208 ice
->state
.dirty
|= IRIS_ALL_DIRTY_BINDINGS
;
1213 /* On Gen9 color buffers may be compressed by the hardware (lossless
1214 * compression). There are, however, format restrictions and care needs to be
1215 * taken that the sampler engine is capable for re-interpreting a buffer with
1216 * format different the buffer was originally written with.
1218 * For example, SRGB formats are not compressible and the sampler engine isn't
1219 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
1220 * color buffer needs to be resolved so that the sampling surface can be
1221 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
1225 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
1226 struct pipe_debug_callback
*dbg
,
1227 const struct iris_resource
*res
,
1228 enum isl_format view_format
)
1230 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
1233 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
1234 const struct isl_format_layout
*res_fmtl
=
1235 isl_format_get_layout(res
->surf
.format
);
1236 const struct isl_format_layout
*view_fmtl
=
1237 isl_format_get_layout(view_format
);
1239 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
1240 view_fmtl
->name
, res_fmtl
->name
);
1249 iris_resource_texture_aux_usage(struct iris_context
*ice
,
1250 const struct iris_resource
*res
,
1251 enum isl_format view_format
,
1252 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1254 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1255 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1257 assert(devinfo
->gen
== 9 || astc5x5_wa_bits
== 0);
1259 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
1260 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
1263 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
1264 res
->aux
.usage
!= ISL_AUX_USAGE_MCS
)
1265 return ISL_AUX_USAGE_NONE
;
1267 switch (res
->aux
.usage
) {
1268 case ISL_AUX_USAGE_HIZ
:
1269 if (sample_with_hiz(devinfo
, res
))
1270 return ISL_AUX_USAGE_HIZ
;
1273 case ISL_AUX_USAGE_MCS
:
1274 return ISL_AUX_USAGE_MCS
;
1276 case ISL_AUX_USAGE_CCS_D
:
1277 case ISL_AUX_USAGE_CCS_E
:
1278 /* If we don't have any unresolved color, report an aux usage of
1279 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
1280 * aux surface and we can save some bandwidth.
1282 if (!has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
1283 0, INTEL_REMAINING_LAYERS
))
1284 return ISL_AUX_USAGE_NONE
;
1286 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
1287 return ISL_AUX_USAGE_CCS_E
;
1294 return ISL_AUX_USAGE_NONE
;
1298 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
1300 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
1301 * values so sRGB curve application was a no-op for all fast-clearable
1304 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
1305 * values, the hardware interprets the floats, not as what would be
1306 * returned from the sampler (or written by the shader), but as being
1307 * between format conversion and sRGB curve application. This means that
1308 * we can switch between sRGB and UNORM without having to whack the clear
1311 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
1315 iris_resource_prepare_texture(struct iris_context
*ice
,
1316 struct iris_batch
*batch
,
1317 struct iris_resource
*res
,
1318 enum isl_format view_format
,
1319 uint32_t start_level
, uint32_t num_levels
,
1320 uint32_t start_layer
, uint32_t num_layers
,
1321 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
1323 enum isl_aux_usage aux_usage
=
1324 iris_resource_texture_aux_usage(ice
, res
, view_format
, astc5x5_wa_bits
);
1326 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
1328 /* Clear color is specified as ints or floats and the conversion is done by
1329 * the sampler. If we have a texture view, we would have to perform the
1330 * clear color conversion manually. Just disable clear color.
1332 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1333 clear_supported
= false;
1335 iris_resource_prepare_access(ice
, batch
, res
, start_level
, num_levels
,
1336 start_layer
, num_layers
,
1337 aux_usage
, clear_supported
);
1341 iris_resource_prepare_image(struct iris_context
*ice
,
1342 struct iris_batch
*batch
,
1343 struct iris_resource
*res
)
1345 /* The data port doesn't understand any compression */
1346 iris_resource_prepare_access(ice
, batch
, res
, 0, INTEL_REMAINING_LEVELS
,
1347 0, INTEL_REMAINING_LAYERS
,
1348 ISL_AUX_USAGE_NONE
, false);
1352 iris_resource_render_aux_usage(struct iris_context
*ice
,
1353 struct iris_resource
*res
,
1354 enum isl_format render_format
,
1356 bool draw_aux_disabled
)
1358 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1359 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1361 if (draw_aux_disabled
)
1362 return ISL_AUX_USAGE_NONE
;
1364 switch (res
->aux
.usage
) {
1365 case ISL_AUX_USAGE_MCS
:
1366 return ISL_AUX_USAGE_MCS
;
1368 case ISL_AUX_USAGE_CCS_D
:
1369 case ISL_AUX_USAGE_CCS_E
:
1370 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1371 * formats. However, there are issues with blending where it doesn't
1372 * properly apply the sRGB curve to the clear color when blending.
1375 if (devinfo->gen >= 9 && blend_enabled &&
1376 isl_format_is_srgb(render_format) &&
1377 !isl_color_value_is_zero_one(res->fast_clear_color, render_format))
1378 return ISL_AUX_USAGE_NONE;
1381 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1382 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1383 return ISL_AUX_USAGE_CCS_E
;
1385 /* Otherwise, we have to fall back to CCS_D */
1386 return ISL_AUX_USAGE_CCS_D
;
1389 return ISL_AUX_USAGE_NONE
;
1394 iris_resource_prepare_render(struct iris_context
*ice
,
1395 struct iris_batch
*batch
,
1396 struct iris_resource
*res
, uint32_t level
,
1397 uint32_t start_layer
, uint32_t layer_count
,
1398 enum isl_aux_usage aux_usage
)
1400 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1401 layer_count
, aux_usage
,
1402 aux_usage
!= ISL_AUX_USAGE_NONE
);
1406 iris_resource_finish_render(struct iris_context
*ice
,
1407 struct iris_resource
*res
, uint32_t level
,
1408 uint32_t start_layer
, uint32_t layer_count
,
1409 enum isl_aux_usage aux_usage
)
1411 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1416 iris_resource_prepare_depth(struct iris_context
*ice
,
1417 struct iris_batch
*batch
,
1418 struct iris_resource
*res
, uint32_t level
,
1419 uint32_t start_layer
, uint32_t layer_count
)
1421 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, start_layer
,
1422 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1426 iris_resource_finish_depth(struct iris_context
*ice
,
1427 struct iris_resource
*res
, uint32_t level
,
1428 uint32_t start_layer
, uint32_t layer_count
,
1431 if (depth_written
) {
1432 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,