2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_transfer.h"
42 #include "util/u_transfer_helper.h"
43 #include "util/u_upload_mgr.h"
44 #include "util/ralloc.h"
45 #include "iris_batch.h"
46 #include "iris_context.h"
47 #include "iris_resource.h"
48 #include "iris_screen.h"
49 #include "intel/dev/gen_debug.h"
51 #include "drm-uapi/drm_fourcc.h"
52 #include "drm-uapi/i915_drm.h"
54 enum modifier_priority
{
55 MODIFIER_PRIORITY_INVALID
= 0,
56 MODIFIER_PRIORITY_LINEAR
,
59 MODIFIER_PRIORITY_Y_CCS
,
62 static const uint64_t priority_to_modifier
[] = {
63 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
64 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
65 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
66 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
67 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
71 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 /* XXX: do something real */
76 case I915_FORMAT_MOD_Y_TILED
:
77 case I915_FORMAT_MOD_X_TILED
:
78 case DRM_FORMAT_MOD_LINEAR
:
80 case I915_FORMAT_MOD_Y_TILED_CCS
:
81 case DRM_FORMAT_MOD_INVALID
:
88 select_best_modifier(struct gen_device_info
*devinfo
,
89 const uint64_t *modifiers
,
92 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
94 for (int i
= 0; i
< count
; i
++) {
95 if (!modifier_is_supported(devinfo
, modifiers
[i
]))
98 switch (modifiers
[i
]) {
99 case I915_FORMAT_MOD_Y_TILED_CCS
:
100 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
102 case I915_FORMAT_MOD_Y_TILED
:
103 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
105 case I915_FORMAT_MOD_X_TILED
:
106 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
108 case DRM_FORMAT_MOD_LINEAR
:
109 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
111 case DRM_FORMAT_MOD_INVALID
:
117 return priority_to_modifier
[prio
];
120 static enum isl_surf_dim
121 target_to_isl_surf_dim(enum pipe_texture_target target
)
125 case PIPE_TEXTURE_1D
:
126 case PIPE_TEXTURE_1D_ARRAY
:
127 return ISL_SURF_DIM_1D
;
128 case PIPE_TEXTURE_2D
:
129 case PIPE_TEXTURE_CUBE
:
130 case PIPE_TEXTURE_RECT
:
131 case PIPE_TEXTURE_2D_ARRAY
:
132 case PIPE_TEXTURE_CUBE_ARRAY
:
133 return ISL_SURF_DIM_2D
;
134 case PIPE_TEXTURE_3D
:
135 return ISL_SURF_DIM_3D
;
136 case PIPE_MAX_TEXTURE_TYPES
:
139 unreachable("invalid texture type");
143 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
144 enum pipe_format pfmt
,
147 unsigned int *external_only
,
150 struct iris_screen
*screen
= (void *) pscreen
;
151 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
153 uint64_t all_modifiers
[] = {
154 DRM_FORMAT_MOD_LINEAR
,
155 I915_FORMAT_MOD_X_TILED
,
156 I915_FORMAT_MOD_Y_TILED
,
157 // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
160 int supported_mods
= 0;
162 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
163 if (!modifier_is_supported(devinfo
, all_modifiers
[i
]))
166 if (supported_mods
< max
) {
168 modifiers
[supported_mods
] = all_modifiers
[i
];
171 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
177 *count
= supported_mods
;
180 static isl_surf_usage_flags_t
181 pipe_bind_to_isl_usage(unsigned bindings
)
183 isl_surf_usage_flags_t usage
= 0;
185 if (bindings
& PIPE_BIND_RENDER_TARGET
)
186 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
188 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
189 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
191 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
192 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
194 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
195 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
200 struct pipe_resource
*
201 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
203 /* For packed depth-stencil, we treat depth as the primary resource
204 * and store S8 as the "second plane" resource.
210 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
211 struct pipe_resource
*stencil
)
213 assert(util_format_has_depth(util_format_description(p_res
->format
)));
214 pipe_resource_reference(&p_res
->next
, stencil
);
218 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
219 struct iris_resource
**out_z
,
220 struct iris_resource
**out_s
)
228 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
229 *out_z
= (void *) res
;
230 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
233 *out_s
= (void *) res
;
238 iris_resource_disable_aux(struct iris_resource
*res
)
240 iris_bo_unreference(res
->aux
.bo
);
241 iris_bo_unreference(res
->aux
.clear_color_bo
);
242 free(res
->aux
.state
);
244 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
245 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
246 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
247 res
->aux
.surf
.size_B
= 0;
249 res
->aux
.clear_color_bo
= NULL
;
250 res
->aux
.state
= NULL
;
254 iris_resource_destroy(struct pipe_screen
*screen
,
255 struct pipe_resource
*resource
)
257 struct iris_resource
*res
= (struct iris_resource
*)resource
;
259 iris_resource_disable_aux(res
);
261 iris_bo_unreference(res
->bo
);
265 static struct iris_resource
*
266 iris_alloc_resource(struct pipe_screen
*pscreen
,
267 const struct pipe_resource
*templ
)
269 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
274 res
->base
.screen
= pscreen
;
275 pipe_reference_init(&res
->base
.reference
, 1);
277 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
278 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
284 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
286 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
287 return minify(res
->surf
.logical_level0_px
.depth
, level
);
289 return res
->surf
.logical_level0_px
.array_len
;
292 static enum isl_aux_state
**
293 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
295 uint32_t total_slices
= 0;
296 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
297 total_slices
+= iris_get_num_logical_layers(res
, level
);
299 const size_t per_level_array_size
=
300 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
302 /* We're going to allocate a single chunk of data for both the per-level
303 * reference array and the arrays of aux_state. This makes cleanup
304 * significantly easier.
306 const size_t total_size
=
307 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
309 void *data
= malloc(total_size
);
313 enum isl_aux_state
**per_level_arr
= data
;
314 enum isl_aux_state
*s
= data
+ per_level_array_size
;
315 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
316 per_level_arr
[level
] = s
;
317 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
318 for (uint32_t a
= 0; a
< level_layers
; a
++)
321 assert((void *)s
== data
+ total_size
);
323 return per_level_arr
;
327 * Allocate the initial aux surface for a resource based on aux.usage
330 iris_resource_alloc_aux(struct iris_screen
*screen
, struct iris_resource
*res
)
332 struct isl_device
*isl_dev
= &screen
->isl_dev
;
333 enum isl_aux_state initial_state
;
334 UNUSED
bool ok
= false;
335 uint8_t memset_value
= 0;
336 uint32_t alloc_flags
= 0;
337 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
338 const unsigned clear_color_state_size
= devinfo
->gen
>= 10 ?
339 screen
->isl_dev
.ss
.clear_color_state_size
:
340 (devinfo
->gen
>= 9 ? screen
->isl_dev
.ss
.clear_value_size
: 0);
342 assert(!res
->aux
.bo
);
344 switch (res
->aux
.usage
) {
345 case ISL_AUX_USAGE_NONE
:
346 res
->aux
.surf
.size_B
= 0;
348 case ISL_AUX_USAGE_HIZ
:
349 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
351 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
353 case ISL_AUX_USAGE_MCS
:
354 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
356 * "When MCS buffer is enabled and bound to MSRT, it is required
357 * that it is cleared prior to any rendering."
359 * Since we only use the MCS buffer for rendering, we just clear it
360 * immediately on allocation. The clear value for MCS buffers is all
361 * 1's, so we simply memset it to 0xff.
363 initial_state
= ISL_AUX_STATE_CLEAR
;
365 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
367 case ISL_AUX_USAGE_CCS_D
:
368 case ISL_AUX_USAGE_CCS_E
:
369 /* When CCS_E is used, we need to ensure that the CCS starts off in
370 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
373 * "If Software wants to enable Color Compression without Fast
374 * clear, Software needs to initialize MCS with zeros."
376 * A CCS value of 0 indicates that the corresponding block is in the
377 * pass-through state which is what we want.
379 * For CCS_D, do the same thing. On Gen9+, this avoids having any
380 * undefined bits in the aux buffer.
382 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
383 alloc_flags
|= BO_ALLOC_ZEROED
;
384 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
388 /* No work is needed for a zero-sized auxiliary buffer. */
389 if (res
->aux
.surf
.size_B
== 0)
392 /* Assert that ISL gave us a valid aux surf */
395 /* Create the aux_state for the auxiliary buffer. */
396 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
400 uint64_t size
= res
->aux
.surf
.size_B
;
402 /* Allocate space in the buffer for storing the clear color. On modern
403 * platforms (gen > 9), we can read it directly from such buffer.
405 * On gen <= 9, we are going to store the clear color on the buffer
406 * anyways, and copy it back to the surface state during state emission.
408 res
->aux
.clear_color_offset
= size
;
409 size
+= clear_color_state_size
;
411 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
412 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
413 * of bytes instead of trying to recalculate based on different format
416 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
,
417 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
418 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
423 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
424 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
427 iris_resource_disable_aux(res
);
431 if (memset_value
!= 0)
432 memset(map
, memset_value
, res
->aux
.surf
.size_B
);
434 /* Zero the indirect clear color to match ::fast_clear_color. */
435 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
436 clear_color_state_size
);
438 iris_bo_unmap(res
->aux
.bo
);
441 if (clear_color_state_size
> 0) {
442 res
->aux
.clear_color_bo
= res
->aux
.bo
;
443 iris_bo_reference(res
->aux
.clear_color_bo
);
446 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
447 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
448 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
449 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
451 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
452 * For LOD == 0, we can grow the dimensions to make it work.
454 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
455 res
->aux
.has_hiz
|= 1 << level
;
463 supports_mcs(const struct isl_surf
*surf
)
465 /* MCS compression only applies to multisampled resources. */
466 if (surf
->samples
<= 1)
469 /* See isl_surf_get_mcs_surf for details. */
470 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
473 /* Depth and stencil buffers use the IMS (interleaved) layout. */
474 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
481 supports_ccs(const struct gen_device_info
*devinfo
,
482 const struct isl_surf
*surf
)
484 /* Gen9+ only supports CCS for Y-tiled buffers. */
485 if (surf
->tiling
!= ISL_TILING_Y0
)
488 /* CCS only supports singlesampled resources. */
489 if (surf
->samples
> 1)
492 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
493 * work for 3D textures until Gen9 where the layout of 3D textures changes
494 * to match 2D array textures.
496 if (devinfo
->gen
< 9 && surf
->dim
!= ISL_SURF_DIM_2D
)
499 /* Note: still need to check the format! */
504 static struct pipe_resource
*
505 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
506 const struct pipe_resource
*templ
)
508 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
509 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
511 assert(templ
->target
== PIPE_BUFFER
);
512 assert(templ
->height0
<= 1);
513 assert(templ
->depth0
<= 1);
514 assert(templ
->format
== PIPE_FORMAT_NONE
||
515 util_format_get_blocksize(templ
->format
) == 1);
517 res
->internal_format
= templ
->format
;
518 res
->surf
.tiling
= ISL_TILING_LINEAR
;
520 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
521 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
522 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
523 memzone
= IRIS_MEMZONE_SHADER
;
524 name
= "shader kernels";
525 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
526 memzone
= IRIS_MEMZONE_SURFACE
;
527 name
= "surface state";
528 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
529 memzone
= IRIS_MEMZONE_DYNAMIC
;
530 name
= "dynamic state";
533 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
535 iris_resource_destroy(pscreen
, &res
->base
);
542 static struct pipe_resource
*
543 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
544 const struct pipe_resource
*templ
,
545 const uint64_t *modifiers
,
548 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
549 struct gen_device_info
*devinfo
= &screen
->devinfo
;
550 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
555 const struct util_format_description
*format_desc
=
556 util_format_description(templ
->format
);
557 const bool has_depth
= util_format_has_depth(format_desc
);
559 select_best_modifier(devinfo
, modifiers
, modifiers_count
);
561 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
563 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
564 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
566 tiling_flags
= 1 << res
->mod_info
->tiling
;
568 if (modifiers_count
> 0) {
569 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
573 /* No modifiers - we can select our own tiling. */
576 /* Depth must be Y-tiled */
577 tiling_flags
= ISL_TILING_Y0_BIT
;
578 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
579 /* Stencil must be W-tiled */
580 tiling_flags
= ISL_TILING_W_BIT
;
581 } else if (templ
->target
== PIPE_BUFFER
||
582 templ
->target
== PIPE_TEXTURE_1D
||
583 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
584 /* Use linear for buffers and 1D textures */
585 tiling_flags
= ISL_TILING_LINEAR_BIT
;
588 /* Use linear for staging buffers */
589 if (templ
->usage
== PIPE_USAGE_STAGING
||
590 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
591 tiling_flags
= ISL_TILING_LINEAR_BIT
;
594 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
596 if (templ
->target
== PIPE_TEXTURE_CUBE
||
597 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
598 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
600 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
601 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
602 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
604 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
607 enum pipe_format pfmt
= templ
->format
;
608 res
->internal_format
= pfmt
;
610 /* Should be handled by u_transfer_helper */
611 assert(!util_format_is_depth_and_stencil(pfmt
));
613 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
614 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
616 UNUSED
const bool isl_surf_created_successfully
=
617 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
618 .dim
= target_to_isl_surf_dim(templ
->target
),
620 .width
= templ
->width0
,
621 .height
= templ
->height0
,
622 .depth
= templ
->depth0
,
623 .levels
= templ
->last_level
+ 1,
624 .array_len
= templ
->array_size
,
625 .samples
= MAX2(templ
->nr_samples
, 1),
626 .min_alignment_B
= 0,
629 .tiling_flags
= tiling_flags
);
630 assert(isl_surf_created_successfully
);
633 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
634 } else if (supports_mcs(&res
->surf
)) {
635 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
636 } else if (has_depth
) {
637 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
638 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
639 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
640 supports_ccs(devinfo
, &res
->surf
)) {
641 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
642 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
644 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
645 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
648 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
650 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
652 /* We don't always support sampling with hiz. But when we do, it must be
655 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
656 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
659 const char *name
= "miptree";
660 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
662 unsigned int flags
= 0;
663 if (templ
->usage
== PIPE_USAGE_STAGING
)
664 flags
|= BO_ALLOC_COHERENT
;
666 /* These are for u_upload_mgr buffers only */
667 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
668 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
669 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
671 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, res
->surf
.size_B
,
673 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
674 res
->surf
.row_pitch_B
, flags
);
679 if (!iris_resource_alloc_aux(screen
, res
))
685 fprintf(stderr
, "XXX: resource creation failed\n");
686 iris_resource_destroy(pscreen
, &res
->base
);
691 static struct pipe_resource
*
692 iris_resource_create(struct pipe_screen
*pscreen
,
693 const struct pipe_resource
*templ
)
695 if (templ
->target
== PIPE_BUFFER
)
696 return iris_resource_create_for_buffer(pscreen
, templ
);
698 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
702 tiling_to_modifier(uint32_t tiling
)
704 static const uint64_t map
[] = {
705 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
706 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
707 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
710 assert(tiling
< ARRAY_SIZE(map
));
715 static struct pipe_resource
*
716 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
717 const struct pipe_resource
*templ
,
720 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
721 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
722 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
726 assert(templ
->target
== PIPE_BUFFER
);
728 res
->internal_format
= templ
->format
;
729 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
730 user_memory
, templ
->width0
,
740 static struct pipe_resource
*
741 iris_resource_from_handle(struct pipe_screen
*pscreen
,
742 const struct pipe_resource
*templ
,
743 struct winsys_handle
*whandle
,
746 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
747 struct gen_device_info
*devinfo
= &screen
->devinfo
;
748 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
749 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
753 if (whandle
->offset
!= 0) {
754 dbg_printf("Attempt to import unsupported winsys offset %u\n",
759 switch (whandle
->type
) {
760 case WINSYS_HANDLE_TYPE_FD
:
761 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
763 case WINSYS_HANDLE_TYPE_SHARED
:
764 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
768 unreachable("invalid winsys handle type");
773 uint64_t modifier
= whandle
->modifier
;
774 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
775 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
777 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
778 assert(res
->mod_info
);
780 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
782 const struct iris_format_info fmt
=
783 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
784 res
->internal_format
= templ
->format
;
786 if (templ
->target
== PIPE_BUFFER
) {
787 res
->surf
.tiling
= ISL_TILING_LINEAR
;
789 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
790 .dim
= target_to_isl_surf_dim(templ
->target
),
792 .width
= templ
->width0
,
793 .height
= templ
->height0
,
794 .depth
= templ
->depth0
,
795 .levels
= templ
->last_level
+ 1,
796 .array_len
= templ
->array_size
,
797 .samples
= MAX2(templ
->nr_samples
, 1),
798 .min_alignment_B
= 0,
799 .row_pitch_B
= whandle
->stride
,
801 .tiling_flags
= 1 << res
->mod_info
->tiling
);
803 assert(res
->bo
->tiling_mode
==
804 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
806 // XXX: create_ccs_buf_for_image?
807 if (!iris_resource_alloc_aux(screen
, res
))
814 iris_resource_destroy(pscreen
, &res
->base
);
819 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
821 struct iris_context
*ice
= (struct iris_context
*)ctx
;
822 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
823 struct iris_resource
*res
= (void *) resource
;
824 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
826 iris_resource_prepare_access(ice
, render_batch
, res
,
827 0, INTEL_REMAINING_LEVELS
,
828 0, INTEL_REMAINING_LAYERS
,
829 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
830 mod
? mod
->supports_clear_color
: false);
834 iris_resource_get_handle(struct pipe_screen
*pscreen
,
835 struct pipe_context
*ctx
,
836 struct pipe_resource
*resource
,
837 struct winsys_handle
*whandle
,
840 struct iris_resource
*res
= (struct iris_resource
*)resource
;
842 /* Disable aux usage if explicit flush not set and this is the
843 * first time we are dealing with this resource.
845 if ((!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0)) {
846 if (p_atomic_read(&resource
->reference
.count
) == 1)
847 iris_resource_disable_aux(res
);
850 /* If this is a buffer, stride should be 0 - no need to special case */
851 whandle
->stride
= res
->surf
.row_pitch_B
;
853 res
->mod_info
? res
->mod_info
->modifier
854 : tiling_to_modifier(res
->bo
->tiling_mode
);
857 enum isl_aux_usage allowed_usage
=
858 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
860 if (res
->aux
.usage
!= allowed_usage
) {
861 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
862 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
863 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
867 switch (whandle
->type
) {
868 case WINSYS_HANDLE_TYPE_SHARED
:
869 return iris_bo_flink(res
->bo
, &whandle
->handle
) == 0;
870 case WINSYS_HANDLE_TYPE_KMS
:
871 whandle
->handle
= iris_bo_export_gem_handle(res
->bo
);
873 case WINSYS_HANDLE_TYPE_FD
:
874 return iris_bo_export_dmabuf(res
->bo
, (int *) &whandle
->handle
) == 0;
881 iris_flush_staging_region(struct pipe_transfer
*xfer
,
882 const struct pipe_box
*flush_box
)
884 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
887 struct iris_transfer
*map
= (void *) xfer
;
889 struct pipe_box src_box
= *flush_box
;
891 /* Account for extra alignment padding in staging buffer */
892 if (xfer
->resource
->target
== PIPE_BUFFER
)
893 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
895 struct pipe_box dst_box
= (struct pipe_box
) {
896 .x
= xfer
->box
.x
+ flush_box
->x
,
897 .y
= xfer
->box
.y
+ flush_box
->y
,
898 .z
= xfer
->box
.z
+ flush_box
->z
,
899 .width
= flush_box
->width
,
900 .height
= flush_box
->height
,
901 .depth
= flush_box
->depth
,
904 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
905 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
910 iris_unmap_copy_region(struct iris_transfer
*map
)
912 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
918 iris_map_copy_region(struct iris_transfer
*map
)
920 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
921 struct pipe_transfer
*xfer
= &map
->base
;
922 struct pipe_box
*box
= &xfer
->box
;
923 struct iris_resource
*res
= (void *) xfer
->resource
;
925 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
926 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
928 struct pipe_resource templ
= (struct pipe_resource
) {
929 .usage
= PIPE_USAGE_STAGING
,
930 .width0
= box
->width
+ extra
,
931 .height0
= box
->height
,
933 .nr_samples
= xfer
->resource
->nr_samples
,
934 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
935 .array_size
= box
->depth
,
938 if (xfer
->resource
->target
== PIPE_BUFFER
)
939 templ
.target
= PIPE_BUFFER
;
940 else if (templ
.array_size
> 1)
941 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
943 templ
.target
= PIPE_TEXTURE_2D
;
945 /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
946 * xfer->resource->format directly. Pick a bpb compatible format so
947 * resource creation will succeed; blorp_copy will override it anyway.
949 switch (util_format_get_blocksizebits(res
->internal_format
)) {
950 case 8: templ
.format
= PIPE_FORMAT_R8_UINT
; break;
951 case 16: templ
.format
= PIPE_FORMAT_R8G8_UINT
; break;
952 case 24: templ
.format
= PIPE_FORMAT_R8G8B8_UINT
; break;
953 case 32: templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
; break;
954 case 48: templ
.format
= PIPE_FORMAT_R16G16B16_UINT
; break;
955 case 64: templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; break;
956 case 96: templ
.format
= PIPE_FORMAT_R32G32B32_UINT
; break;
957 case 128: templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; break;
958 default: unreachable("Invalid bpb");
961 map
->staging
= iris_resource_create(pscreen
, &templ
);
962 assert(map
->staging
);
964 if (templ
.target
!= PIPE_BUFFER
) {
965 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
966 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
967 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
970 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
971 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
972 xfer
->resource
, xfer
->level
, box
);
973 /* Ensure writes to the staging BO land before we map it below. */
974 iris_emit_pipe_control_flush(map
->batch
,
975 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
976 PIPE_CONTROL_CS_STALL
);
979 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
981 if (iris_batch_references(map
->batch
, staging_bo
))
982 iris_batch_flush(map
->batch
);
985 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
987 map
->unmap
= iris_unmap_copy_region
;
991 get_image_offset_el(struct isl_surf
*surf
, unsigned level
, unsigned z
,
992 unsigned *out_x0_el
, unsigned *out_y0_el
)
994 if (surf
->dim
== ISL_SURF_DIM_3D
) {
995 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
997 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1002 * Get pointer offset into stencil buffer.
1004 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1005 * must decode the tile's layout in software.
1008 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1010 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1012 * Even though the returned offset is always positive, the return type is
1014 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1015 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1018 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1020 uint32_t tile_size
= 4096;
1021 uint32_t tile_width
= 64;
1022 uint32_t tile_height
= 64;
1023 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1025 uint32_t tile_x
= x
/ tile_width
;
1026 uint32_t tile_y
= y
/ tile_height
;
1028 /* The byte's address relative to the tile's base addres. */
1029 uint32_t byte_x
= x
% tile_width
;
1030 uint32_t byte_y
= y
% tile_height
;
1032 uintptr_t u
= tile_y
* row_size
1033 + tile_x
* tile_size
1034 + 512 * (byte_x
/ 8)
1036 + 32 * ((byte_y
/ 4) % 2)
1037 + 16 * ((byte_x
/ 4) % 2)
1038 + 8 * ((byte_y
/ 2) % 2)
1039 + 4 * ((byte_x
/ 2) % 2)
1044 /* adjust for bit6 swizzling */
1045 if (((byte_x
/ 8) % 2) == 1) {
1046 if (((byte_y
/ 8) % 2) == 0) {
1058 iris_unmap_s8(struct iris_transfer
*map
)
1060 struct pipe_transfer
*xfer
= &map
->base
;
1061 const struct pipe_box
*box
= &xfer
->box
;
1062 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1063 struct isl_surf
*surf
= &res
->surf
;
1064 const bool has_swizzling
= false;
1066 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1067 uint8_t *untiled_s8_map
= map
->ptr
;
1068 uint8_t *tiled_s8_map
=
1069 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1071 for (int s
= 0; s
< box
->depth
; s
++) {
1072 unsigned x0_el
, y0_el
;
1073 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1075 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1076 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1077 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1081 tiled_s8_map
[offset
] =
1082 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1092 iris_map_s8(struct iris_transfer
*map
)
1094 struct pipe_transfer
*xfer
= &map
->base
;
1095 const struct pipe_box
*box
= &xfer
->box
;
1096 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1097 struct isl_surf
*surf
= &res
->surf
;
1099 xfer
->stride
= surf
->row_pitch_B
;
1100 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1102 /* The tiling and detiling functions require that the linear buffer has
1103 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1104 * over-allocate the linear buffer to get the proper alignment.
1106 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1107 assert(map
->buffer
);
1109 const bool has_swizzling
= false;
1111 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1112 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1113 * invalidate is set, since we'll be writing the whole rectangle from our
1114 * temporary buffer back out.
1116 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1117 uint8_t *untiled_s8_map
= map
->ptr
;
1118 uint8_t *tiled_s8_map
=
1119 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1121 for (int s
= 0; s
< box
->depth
; s
++) {
1122 unsigned x0_el
, y0_el
;
1123 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1125 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1126 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1127 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1131 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1132 tiled_s8_map
[offset
];
1138 map
->unmap
= iris_unmap_s8
;
1141 /* Compute extent parameters for use with tiled_memcpy functions.
1142 * xs are in units of bytes and ys are in units of strides.
1145 tile_extents(struct isl_surf
*surf
,
1146 const struct pipe_box
*box
,
1147 unsigned level
, int z
,
1148 unsigned *x1_B
, unsigned *x2_B
,
1149 unsigned *y1_el
, unsigned *y2_el
)
1151 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1152 const unsigned cpp
= fmtl
->bpb
/ 8;
1154 assert(box
->x
% fmtl
->bw
== 0);
1155 assert(box
->y
% fmtl
->bh
== 0);
1157 unsigned x0_el
, y0_el
;
1158 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1160 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1161 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1162 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1163 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1167 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1169 struct pipe_transfer
*xfer
= &map
->base
;
1170 const struct pipe_box
*box
= &xfer
->box
;
1171 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1172 struct isl_surf
*surf
= &res
->surf
;
1174 const bool has_swizzling
= false;
1176 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1178 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1180 for (int s
= 0; s
< box
->depth
; s
++) {
1181 unsigned x1
, x2
, y1
, y2
;
1182 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1184 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1186 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1187 surf
->row_pitch_B
, xfer
->stride
,
1188 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1191 os_free_aligned(map
->buffer
);
1192 map
->buffer
= map
->ptr
= NULL
;
1196 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1198 struct pipe_transfer
*xfer
= &map
->base
;
1199 const struct pipe_box
*box
= &xfer
->box
;
1200 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1201 struct isl_surf
*surf
= &res
->surf
;
1203 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1204 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1206 unsigned x1
, x2
, y1
, y2
;
1207 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1209 /* The tiling and detiling functions require that the linear buffer has
1210 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1211 * over-allocate the linear buffer to get the proper alignment.
1214 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1215 assert(map
->buffer
);
1216 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1218 const bool has_swizzling
= false;
1220 // XXX: PIPE_TRANSFER_READ?
1221 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1223 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1225 for (int s
= 0; s
< box
->depth
; s
++) {
1226 unsigned x1
, x2
, y1
, y2
;
1227 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1229 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1230 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1232 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1233 surf
->row_pitch_B
, has_swizzling
,
1234 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1238 map
->unmap
= iris_unmap_tiled_memcpy
;
1242 iris_map_direct(struct iris_transfer
*map
)
1244 struct pipe_transfer
*xfer
= &map
->base
;
1245 struct pipe_box
*box
= &xfer
->box
;
1246 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1248 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1250 if (res
->base
.target
== PIPE_BUFFER
) {
1252 xfer
->layer_stride
= 0;
1254 map
->ptr
= ptr
+ box
->x
;
1256 struct isl_surf
*surf
= &res
->surf
;
1257 const struct isl_format_layout
*fmtl
=
1258 isl_format_get_layout(surf
->format
);
1259 const unsigned cpp
= fmtl
->bpb
/ 8;
1260 unsigned x0_el
, y0_el
;
1262 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1264 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1265 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1267 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1272 iris_transfer_map(struct pipe_context
*ctx
,
1273 struct pipe_resource
*resource
,
1275 enum pipe_transfer_usage usage
,
1276 const struct pipe_box
*box
,
1277 struct pipe_transfer
**ptransfer
)
1279 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1280 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1281 struct isl_surf
*surf
= &res
->surf
;
1283 /* If we can discard the whole resource, we can also discard the
1284 * subrange being accessed.
1286 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
)
1287 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1289 bool map_would_stall
= false;
1291 if (resource
->target
!= PIPE_BUFFER
) {
1292 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1293 level
, box
->z
, box
->depth
,
1294 usage
& PIPE_TRANSFER_WRITE
);
1297 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1298 map_would_stall
= iris_bo_busy(res
->bo
);
1300 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1301 map_would_stall
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1303 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1304 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1308 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1309 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1312 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1313 struct pipe_transfer
*xfer
= &map
->base
;
1318 memset(map
, 0, sizeof(*map
));
1319 map
->dbg
= &ice
->dbg
;
1321 pipe_resource_reference(&xfer
->resource
, resource
);
1322 xfer
->level
= level
;
1323 xfer
->usage
= usage
;
1327 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1328 * there is to access them simultaneously on the CPU & GPU. This also
1329 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1330 * contain state we're constructing for a GPU draw call, which would
1331 * kill us with infinite stack recursion.
1333 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1334 PIPE_TRANSFER_COHERENT
|
1335 PIPE_TRANSFER_MAP_DIRECTLY
);
1337 /* GPU copies are not useful for buffer reads. Instead of stalling to
1338 * read from the original buffer, we'd simply copy it to a temporary...
1339 * then stall (a bit longer) to read from that buffer.
1341 * Images are less clear-cut. Color resolves are destructive, removing
1342 * the underlying compression, so we'd rather blit the data to a linear
1343 * temporary and map that, to avoid the resolve. (It might be better to
1344 * a tiled temporary and use the tiled_memcpy paths...)
1346 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
1347 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
&&
1348 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) {
1352 if (map_would_stall
&& !no_gpu
) {
1353 /* If we need a synchronous mapping and the resource is busy,
1354 * we copy to/from a linear temporary buffer using the GPU.
1356 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1357 map
->blorp
= &ice
->blorp
;
1358 iris_map_copy_region(map
);
1360 /* Otherwise we're free to map on the CPU. Flush if needed. */
1361 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1362 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1363 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1364 iris_batch_flush(&ice
->batches
[i
]);
1368 if (surf
->tiling
== ISL_TILING_W
) {
1369 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1371 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1372 iris_map_tiled_memcpy(map
);
1374 iris_map_direct(map
);
1382 iris_transfer_flush_region(struct pipe_context
*ctx
,
1383 struct pipe_transfer
*xfer
,
1384 const struct pipe_box
*box
)
1386 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1387 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1388 struct iris_transfer
*map
= (void *) xfer
;
1391 iris_flush_staging_region(xfer
, box
);
1393 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1394 if (ice
->batches
[i
].contains_draw
||
1395 ice
->batches
[i
].cache
.render
->entries
) {
1396 iris_batch_maybe_flush(&ice
->batches
[i
], 24);
1397 iris_flush_and_dirty_for_history(ice
, &ice
->batches
[i
], res
);
1401 /* Make sure we flag constants dirty even if there's no need to emit
1402 * any PIPE_CONTROLs to a batch.
1404 iris_flush_and_dirty_for_history(ice
, NULL
, res
);
1408 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1410 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1411 struct iris_transfer
*map
= (void *) xfer
;
1413 if (!(xfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
1414 struct pipe_box flush_box
= {
1415 .x
= 0, .y
= 0, .z
= 0,
1416 .width
= xfer
->box
.width
,
1417 .height
= xfer
->box
.height
,
1418 .depth
= xfer
->box
.depth
,
1420 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1426 pipe_resource_reference(&xfer
->resource
, NULL
);
1427 slab_free(&ice
->transfer_pool
, map
);
1431 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1432 struct iris_batch
*batch
,
1433 struct iris_resource
*res
)
1435 if (res
->base
.target
!= PIPE_BUFFER
)
1438 unsigned flush
= PIPE_CONTROL_CS_STALL
;
1440 /* We've likely used the rendering engine (i.e. BLORP) to write to this
1441 * surface. Flush the render cache so the data actually lands.
1443 if (batch
&& batch
->name
!= IRIS_BATCH_COMPUTE
)
1444 flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1446 uint64_t dirty
= 0ull;
1448 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1449 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1450 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1451 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1452 IRIS_DIRTY_CONSTANTS_TCS
|
1453 IRIS_DIRTY_CONSTANTS_TES
|
1454 IRIS_DIRTY_CONSTANTS_GS
|
1455 IRIS_DIRTY_CONSTANTS_FS
|
1456 IRIS_DIRTY_CONSTANTS_CS
|
1457 IRIS_ALL_DIRTY_BINDINGS
;
1460 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1461 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1463 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1464 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1466 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1467 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1470 iris_emit_pipe_control_flush(batch
, flush
);
1472 ice
->state
.dirty
|= dirty
;
1476 iris_resource_set_clear_color(struct iris_context
*ice
,
1477 struct iris_resource
*res
,
1478 union isl_color_value color
)
1480 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1481 res
->aux
.clear_color
= color
;
1488 union isl_color_value
1489 iris_resource_get_clear_color(const struct iris_resource
*res
,
1490 struct iris_bo
**clear_color_bo
,
1491 uint64_t *clear_color_offset
)
1493 assert(res
->aux
.bo
);
1496 *clear_color_bo
= res
->aux
.clear_color_bo
;
1497 if (clear_color_offset
)
1498 *clear_color_offset
= res
->aux
.clear_color_offset
;
1499 return res
->aux
.clear_color
;
1502 static enum pipe_format
1503 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1505 struct iris_resource
*res
= (void *) p_res
;
1506 return res
->internal_format
;
1509 static const struct u_transfer_vtbl transfer_vtbl
= {
1510 .resource_create
= iris_resource_create
,
1511 .resource_destroy
= iris_resource_destroy
,
1512 .transfer_map
= iris_transfer_map
,
1513 .transfer_unmap
= iris_transfer_unmap
,
1514 .transfer_flush_region
= iris_transfer_flush_region
,
1515 .get_internal_format
= iris_resource_get_internal_format
,
1516 .set_stencil
= iris_resource_set_separate_stencil
,
1517 .get_stencil
= iris_resource_get_separate_stencil
,
1521 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1523 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
1524 pscreen
->resource_create_with_modifiers
=
1525 iris_resource_create_with_modifiers
;
1526 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1527 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1528 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1529 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1530 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1531 pscreen
->transfer_helper
=
1532 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1536 iris_init_resource_functions(struct pipe_context
*ctx
)
1538 ctx
->flush_resource
= iris_flush_resource
;
1539 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1540 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1541 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1542 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1543 ctx
->texture_subdata
= u_default_texture_subdata
;